Data transmission circuit and memory

Abstract

The present invention relates to a data transmission circuit and a memory, wherein the data transmission circuit comprises: a normal reading module connected to a normal storage array, used to read data from the normal storage array and output it; a redundant reading module connected to a redundant storage array, used to read data from the redundant storage array and output it; an error detection operation module connected to the normal reading module and the redundant reading module, respectively, used to synchronously receive the read data output by the normal reading module and the redundant reading module, and perform error detection operation on the read data. In an embodiment of the present application, the normal reading module and the redundant reading module send the read data to the error detection operation module in parallel, that is, no matter whether the normal storage array is damaged or not, there is no need to first perform the step of querying the address of the damaged normal storage array, which simplifies the serial steps of data reading, thereby realizing a data transmission circuit with a faster reading speed.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a data transmission circuit and a memory. Background Art

[0002] Semiconductor memory is a memory that uses semiconductor circuits for access. Among them, dynamic random access memory (DRAM) is widely used in various fields due to its fast storage speed and high integration.

[0003] In order to obtain higher flexibility and reliability, a certain number of redundant memory arrays are usually set in the dynamic random access memory to serve as substitutes when the normal memory array is damaged. However, the current data transmission circuit takes a long time to process when reading the redundant memory array, thus greatly reducing the processing speed of the dynamic random access memory. Summary of the invention

[0004] Based on this, it is necessary to provide a data transmission circuit and a memory to address the problem that the data transmission circuit takes a long time to operate when reading and writing a redundant memory array.

[0005] A data transmission circuit, the data transmission circuit comprising:

[0006] A normal reading module, connected to the normal storage array, for reading data from the normal storage array and outputting the data;

[0007] A redundant reading module, connected to the redundant storage array, for reading data from the redundant storage array and outputting the data;

[0008] The error detection operation module is connected to the normal reading module and the redundant reading module respectively, and is used for synchronously receiving the read data output by the normal reading module and the redundant reading module, and performing error detection operation on the read data.

[0009] In one embodiment, the normal storage array includes a flag bit storage array and a plurality of data bit storage arrays, and the normal reading module includes:

[0010] A plurality of data bit reading units, each of which is connected to the data bit storage array in a one-to-one correspondence and is used to read data information from the corresponding data bit storage array;

[0011] The flag position reading unit is connected to the flag position storage array and is used for reading flag information from the flag position storage array.

[0012] In one embodiment, it also includes:

[0013] A plurality of logic operation units, wherein one input end of the logic operation unit is connected to one of the data bit reading unit, the flag bit reading unit and the redundant reading module, another input end of the logic operation unit is connected to an enable signal, an output end of the logic operation unit is connected to the error detection operation module, and the logic operation unit is used to perform a preset operation on the data input from the two input ends and send the operation result to the error detection operation module.

[0014] In one embodiment, the logic operation unit is a logic AND unit, one input end of the logic AND unit is connected to one of the data bit reading unit, the flag bit reading unit and the redundant reading module, the other input end of the logic AND unit is connected to the enable signal, the output end of the logic AND unit is connected to the error detection operation module, and the logic operation unit is used to perform a logic AND operation on the data input from the two input ends, and send the operation result to the error detection operation module.

[0015] In one embodiment, it also includes:

[0016] An enable control module is connected to the plurality of logic AND units respectively, the enable control module is used to generate a redundant read enable signal and a plurality of data bit read enable signals, the data bit read enable signal corresponds to the data bit read unit one-to-one, the redundant read enable signal corresponds to the redundant read module, and the enable control module is further used to send the redundant read enable signal and the data bit read enable signal to the logic AND unit one-to-one;

[0017] When the redundant read enable signal is valid, one of the multiple data bit read enable signals is invalid; when the redundant read enable signal is invalid, all of the multiple data bit read enable signals are valid.

[0018] In one embodiment, the error detection operation module is used to output a plurality of error detection information, the error detection information corresponds to the data bit reading unit one by one, and the data transmission circuit further includes:

[0019] A normal error correction unit, connected to the data bit reading unit in a one-to-one correspondence, and also connected to the error detection operation module, the normal error correction unit is used to receive the error detection information, and update the corresponding data information output by the data bit reading unit according to the error detection information;

[0020] A redundant data bus connected to the redundant reading module and used for receiving data output by the redundant reading module;

[0021] A plurality of first multiplexers, wherein the first multiplexers correspond one-to-one to the normal error correction units, one input end of the first multiplexer is connected to the corresponding normal error correction unit, another input end of the first multiplexer is connected to the redundant data bus, and the first multiplexer is used to receive a data bit read enable signal and select to output data input from any of the input ends under the control of the data bit read enable signal.

[0022] In one of the embodiments, the normal error correction unit is used to send the data information output by the data bit reading unit to the first multiplexer when the error detection information is invalid.

[0023] In one of the embodiments, the normal error correction unit is used to correct the data information output by the data bit reading unit according to the error detection information when the error detection information is valid, so as to update the data information, and send the updated data information to the first multiplexer.

[0024] In one of the embodiments, the normal error correction unit is further configured to send the updated data information to the corresponding data bit storage array when the error detection information is valid, so as to update the data information stored in the normal storage array.

[0025] In one of the embodiments, the redundant read module is used to send the data read by the redundant read module to the redundant data bus when the redundant read enable signal is valid;

[0026] The first multiplexer is used for selecting and outputting data on a redundant data bus when the data bit read enable signal is invalid.

[0027] In one embodiment, the error detection operation module is further used to output error detection information corresponding to the redundant reading module, and the data transmission circuit further includes:

[0028] A redundant error correction unit, wherein the redundant error correction unit is respectively connected to the redundant read module, the error detection operation module and the redundant data bus, and the redundant error correction unit is used to update the data output by the redundant read module according to the error detection information when the error detection information is valid and the redundant read enable signal is valid, and send the updated data to the redundant data bus.

[0029] In one embodiment, it also includes:

[0030] A plurality of data bit writing units are connected to the plurality of data bit storage arrays in a one-to-one correspondence and are also connected to the redundant data bus, and are used to send data information to the data bit storage array or the redundant data bus;

[0031] a flag bit writing unit, connected to the flag bit storage array and the redundant data bus respectively, and used for sending flag information to the flag bit storage array or the redundant data bus;

[0032] The redundant writing module is connected to the redundant storage array and the redundant data bus respectively, and is used for writing the data on the redundant data bus into the redundant storage array.

[0033] In one embodiment, it also includes:

[0034] The flag encoding module is connected to the data bit writing unit and the flag writing unit respectively, and is used to receive the data information output by the data bit writing unit, encode the data to generate the flag information, and send the flag information to the flag writing unit.

[0035] A memory, comprising:

[0036] Multiple normal storage arrays;

[0037] Redundant storage arrays;

[0038] A plurality of data pin areas, wherein the data pin areas correspond one to one with the normal storage array;

[0039] As the data transmission circuit mentioned above, the data transmission circuit is connected to the redundant memory array, the normal memory array and the data pin area respectively.

[0040] The data transmission circuit includes: a normal reading module connected to a normal storage array, used to read data from the normal storage array and output; a redundant reading module connected to a redundant storage array, used to read data from the redundant storage array and output; an error detection operation module connected to the normal reading module and the redundant reading module, respectively, used to synchronously receive the read data output by the normal reading module and the redundant reading module, and perform error detection operation on the read data. In an embodiment of the present application, both the normal reading module and the redundant reading module are connected to the error detection operation module, and the read data are sent to the error detection operation module in parallel, that is, regardless of whether the normal storage array is damaged, the normal reading module reads the normal storage array, and the redundant reading module synchronously reads the redundant storage array. After the reading is completed, the normal reading module and the redundant reading module synchronously send the read data to the error detection operation module. Therefore, there is no need to first perform the step of querying the address of the damaged normal storage array, which simplifies the serial step of data reading, thereby realizing a data transmission circuit with a faster reading speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a structural block diagram of a data transmission circuit according to an embodiment;

[0042] Figure 2 is a structural diagram of a data transmission circuit according to another embodiment;

[0043] Figure 3 is a structural diagram of a data transmission circuit according to another embodiment;

[0044] Figure 4 FIG. 4 is a structural diagram of a data transmission circuit according to another embodiment.

[0045] Component number description:

[0046] Normal read module: 100; data bit read unit: 111; flag bit read unit: 112; redundant read module: 113; data bit write unit: 121; flag bit write unit: 122; redundant write module: 123; logic operation unit: 131; first multiplexer: 141; normal error correction unit: 151; redundant error correction unit: 152; write operation unit: 161; second multiplexer: 171; normal storage array: 200; data bit storage array: 210; flag bit storage array: 220; redundant storage array: 230; data pin area: 240; error detection operation module: 300; redundant data bus: 400; flag bit encoding module: 500; enable control module: 600 DETAILED DESCRIPTION

[0047] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0049] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the method or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0050] In the prior art, when a redundant storage array is needed to replace a damaged normal storage array for data reading, it is necessary to first query whether the normal storage array currently accessed is a repaired storage array. If the normal storage array corresponding to the current access address is a repaired storage array, the repaired address is not accessed, but the address of the redundant storage array as a replacement is accessed, thereby realizing data reading. It can be understood that in the prior art, the query of the repaired address and the reading of the redundant storage array are serial, resulting in a slow processing speed.

[0051] Furthermore, if the repair of column redundancy is not limited to a small range, but a relatively large range, for example, a global repair is performed within the range of a whole read / write operation, then it is necessary to first query the address of the damaged normal storage array, and then read the corresponding redundant storage array for replacement. Therefore, the required operation time will be greatly increased, and the subsequent error detection operation will also take a long time, which together lead to a decrease in the access speed of the memory.

[0052] Figure 1 is a structural block diagram of a data transmission circuit according to an embodiment, Figure 1 In this embodiment, the data transmission circuit includes a normal reading module 100 , a redundant reading module 113 and an error detection operation module 300 .

[0053] The normal reading module 100 is connected to the normal storage array 200, and is used to read and output data from the normal storage array 200. The normal storage array 200 refers to a storage array used when the memory operates normally, and the memory includes multiple normal storage arrays 200.

[0054] The redundant read module 113 is connected to the redundant storage array 230, and is used to read data from the redundant storage array 230 and output it. The redundant storage array 230 refers to a storage array used to replace when the normal storage array 200 is damaged. The damage of the normal storage array 200 includes damage caused during the preparation of the memory and damage during the use of the memory. The normal storage array 200 and the redundant storage array 230 are prepared at the same time. Usually, multiple normal storage arrays 200 correspond to one redundant storage array 230. When the normal storage array 200 is found to be damaged by the detection means, the redundant storage array 230 is used to replace the damaged normal storage array 200 through the repair process, thereby realizing the repair of the storage array. After the storage array is repaired, the data to be stored in the damaged normal storage array 200 will be stored in the redundant storage array 230, and if it is necessary to read the data in the damaged normal storage array 200, it will be read from the corresponding redundant storage array 230.

[0055] The error detection operation module 300 is connected to the normal reading module 100 and the redundant reading module 113 respectively, and is used to synchronously receive the read data output by the normal reading module 100 and the redundant reading module 113, and perform error detection operation on the read data.

[0056] In this embodiment, both the normal reading module 100 and the redundant reading module 113 are connected to the error detection operation module 300, and the read data are sent to the error detection operation module 300 in parallel, that is, regardless of whether the normal storage array 200 is damaged, the normal reading module 100 reads the normal storage array 200, and the redundant reading module 113 synchronously reads the redundant storage array 230. After the reading is completed, the normal reading module 100 and the redundant reading module 113 synchronously send the read data to the error detection operation module 300. Therefore, there is no need to first perform the step of querying the address of the damaged normal storage array 200, thereby simplifying the serial steps of data reading, and realizing a data transmission circuit with a faster reading speed.

[0057] In one embodiment, continue to refer to Figure 1 The normal storage array 200 includes a flag bit storage array 220 and a plurality of data bit storage arrays 210 , and the normal reading module 100 includes a flag bit reading unit 112 and a plurality of data bit reading units 111 .

[0058] The data bit reading unit 111 is connected to the data bit storage array 210 in a one-to-one correspondence, and is used to read data information from the corresponding data bit storage array 210 .

[0059] The flag reading unit 112 is connected to the flag storage array 220 and is used to read the flag information from the flag storage array 220. The flag information corresponds to the data information, that is, unique flag information can be generated according to the data information, and according to the flag information, it is also possible to reversely judge whether the corresponding data information is wrong. That is, if the data information changes, the flag information will also change accordingly. Therefore, by comparing the flag information corresponding to the written data information with the flag information corresponding to the read data information, it can be determined whether the written data information and the read data information are the same.

[0060] It should be noted that, for the data bit storage array 210, the read data information needs to be the same as the written data information in order to have an effective data reading and writing process, otherwise the read data information will be wrong. Therefore, if the two flag information when writing and reading are the same, it means that the written data information is the same as the read data information, and the data reading and writing process is effective; if the two flag information when writing and reading are different, it means that the written data information is different from the read data information, that is, the data information changes during the writing and / or reading process, and the changed data needs to be corrected to generate the correct read data information. In this embodiment, the error detection operation circuit determines whether it is necessary to correct the read data information by comparing the flag information corresponding to the written data information with the flag information corresponding to the read data information, thereby improving the accuracy of the read data.

[0061] Further, a plurality of data bit storage arrays 210 correspond to one flag bit storage array 220, that is, one flag bit storage array 220 is used to store flag information corresponding to data information of a plurality of data bit storage arrays 210. For example, 16 data bit storage arrays 210 may correspond to one flag bit storage array 220, and accordingly, 16 data bit reading units 111 may correspond to one flag bit reading unit 112.

[0062] In one embodiment, the data transmission circuit further includes an enable control module 600, which is connected to the redundant read module 113 and the multiple data bit read units 111 respectively. The enable control module 600 is used to generate a redundant read enable signal Read Repair and multiple data bit read enable signals Read killn, wherein n is the same as the number of the data bit storage array, the data bit read enable signal Read killn corresponds to the data bit read unit 111 one by one, and the redundant read enable signal Read Repair corresponds to the redundant read module 113. The enable control module 600 is also used to send the redundant read enable signal Read Repair and the data bit read enable signal Read killn to the data bit read unit 111 or the redundant read module 113 one by one. When the redundant read enable signal Read Repair is valid, one of the multiple data bit read enable signals Readkilln is invalid; when the redundant read enable signal Read Repair is invalid, the multiple data bit read enable signals Readkilln are all valid.

[0063] For ease of explanation, in the embodiment of the present application, the data bit read enable signal is named Read killn, and the redundant read enable signal Read Repair is named Read Repair. Since the data bit read enable signal Read killn corresponds to the data bit read unit 111 one by one, the number of the data bit read enable signal Read killn is the same as the number of the data bit read unit 111. For example, if the number of the data bit read unit 111 is 16, the number of the data bit read enable signal Read killn is also 16, and the 16 data bit read enable signals Read killn can be named Read kill0 to Readkill15 respectively.

[0064] Furthermore, the enable control module 600 is also connected to the flag reading unit 112 , and the enable control module 600 is also used to generate a flag read enable signal Read killcc, so as to control the flag reading unit 112 .

[0065] Before the memory is shipped out of the factory, each data bit storage array 210 of the memory is tested to determine the damaged data bit storage array 210, and then each data bit storage array 210 is marked according to the test results, and a query table for storing the mark of each data bit storage array 210 is generated. Therefore, the mark determines the data bit read enable signal Read killn of the corresponding data bit storage array 210. For example, when the data bit storage array 210 is damaged, the mark is 0, and the corresponding generated data bit read enable signal Read killn is invalid; when the data bit storage array 210 is not damaged, the mark is 1, and the corresponding generated data bit read enable signal Read killn is valid.

[0066] Furthermore, it takes about 2 ns for the data bit reading unit 111 and the redundant reading module 113 to read data from the corresponding storage array. During this time period, the enable control module 600 synchronously reads the above-mentioned query table to obtain information on whether each data bit storage array 210 is damaged, thereby generating a redundant read enable signal ReadRepair and multiple data bit read enable signals Read killn based on the queried information.

[0067] Figure 2 is a structural diagram of a data transmission circuit according to another embodiment, Figure 2 It should be noted that the memory includes multiple data bit storage arrays 210, for example, 8, 16 or 32, etc., but in order to simplify the drawings, Figure 2Only two data bit storage arrays 210 and their corresponding data transmission structures are shown. Similarly, the drawings of other embodiments of the present application are also simplified and will not be described in detail in other drawings.

[0068] refer to Figure 2 In this embodiment, the data transmission circuit further includes a plurality of logic operation units 131, one input end of the logic operation unit 131 is connected to one of the data bit reading unit 111, the flag bit reading unit 112 and the redundant reading module 113, the other input end of the logic operation unit 131 is connected to the enable signal, the output end of the logic operation unit 131 is connected to the error detection operation module 300, and the logic operation unit 131 is used to perform a preset operation on the data input from the two input ends, and send the operation result to the error detection operation module 300. In this embodiment, the logic operation unit 131 performs preliminary processing on the received data according to the enable signal, and then sends the processed data to the error detection operation module 300, thereby simplifying the operation complexity of the error detection operation module 300 and improving the operation speed of the error detection operation module 300.

[0069] In one embodiment, the logic operation unit 131 is a logic AND unit, one input end of the logic AND unit is connected to one of the data bit reading unit 111, the flag bit reading unit 112 and the redundant reading module 113, the other input end of the logic AND unit is connected to the enable signal, and the output end of the logic AND unit is connected to the error detection operation module 300. The logic operation unit 131 is used to perform a logic AND operation on the data input from the two input ends, and send the operation result to the error detection operation module 300.

[0070] Specifically, taking the first data bit reading unit 111 and the data bit read enable signal Read kill0 as an example, a logic AND operation is performed on the data output by the first data bit reading unit 111 and the data bit read enable signal Read kill0.

[0071] When the data bit read enable signal Read kill0 is 0, it indicates that the corresponding data bit storage array 210 is damaged, and the data output by the data bit reading unit 111 is logically ANDed with 0, and the data output by the logical AND unit is all 0. For example, if it is 8-bit data, the logical AND unit corresponding to the data bit reading unit 111 outputs 00000000. At the same time, under the control of the flag bit read enable signal Read killcc, the logical AND unit corresponding to the flag bit reading unit 112 also outputs 0. Based on the above operation processing of the logical AND unit, the data information can be matched with the flag information, and the detection result of the error detection operation module 300 is that there is no error. Therefore, it is not necessary to further obtain the information of the error data bit through the error detection operation module 300, thereby simplifying the operation steps and complexity of the error detection operation module 300.

[0072] When the data bit read enable signal Read kill0 is 1, it indicates that the corresponding data bit storage array 210 is not damaged, and the data output by the data bit reading unit 111 is logically ANDed with 1, and the data output by the logical AND unit is the data output by the data bit reading unit 111. Therefore, the logic operation unit 131 of this embodiment does not affect the data transmission and error detection functions of the undamaged data bit storage array 210, and can reduce the difficulty of data transmission and error detection of the damaged data bit storage array 210, thereby realizing a data transmission circuit with a faster running speed.

[0073] It should be clear that the logic operation unit 131 is not limited to the AND unit provided in the above embodiment, and can also be a NAND unit, etc. The logic operation unit 131 only needs to meet the following conditions: when the data bit read enable signal Read killn is effective, the data read by the data bit reading unit 111 is output; when the data bit read enable signal Read killn is invalid, the preset data is output. The preset data output by the logic operation unit 131 corresponding to the data bit reading unit 111 can also be, for example, 11111111, 01010101, etc., and the preset data output by the logic operation unit 131 corresponding to the flag bit reading unit 112 can be, for example, 0.

[0074] In one embodiment, the error detection operation module 300 is used to output a plurality of error detection information, and the error detection information corresponds to the data bit reading unit 111 one by one. The data transmission circuit further includes a normal error correction unit 151, a redundant data bus 400 and a plurality of first multiplexers 141. The error detection information includes whether the read data information is the same as the written data information. When the two are different, the error detection information further includes a specific error data bit. For example, if the written data information is 10000000 and the read data information is 11000000, the error data bit is the second bit.

[0075] The normal error correction unit 151 is connected to the data bit reading unit 111 in a one-to-one correspondence, and is also connected to the error detection operation module 300. The normal error correction unit 151 is used to receive error detection information and update the data information output by the corresponding data bit reading unit 111 according to the error detection information. Since the data in the memory is stored in binary, when there is an error in reading the data, error correction can be performed directly according to the error detection information. For example, if the data information output by the data bit reading unit 111 is 11000000, and the error detection information indicates that the second bit is an erroneous data bit, the written data information must be 10000000, and the normal error correction unit 151 can update the data information to complete the error correction.

[0076] The redundant data bus 400 is connected to the redundant read module 113 and is used to receive data output by the redundant read module 113. Specifically, after the redundant read module 113 reads data from the redundant storage array 230, it transmits the read data to the redundant data bus 400, so that the first multiplexer 141 corresponding to the damaged data bit storage array 210 can obtain the read data from the redundant data bus 400.

[0077] The first multiplexer 141 corresponds one-to-one to the normal error correction unit 151, one input end of the first multiplexer 141 is connected to the corresponding normal error correction unit 151, and the other input end of the first multiplexer is connected to the redundant data bus 400. The first multiplexer 141 is used to receive the data bit read enable signal Read killn, and select to output the data input from any input end under the control of the data bit read enable signal Read killn. Specifically, taking the first data bit read unit 111 and the data bit read enable signal Read kill0 as an example, when the data bit read enable signal Read kill0 is 0, it indicates that the corresponding data bit storage array 210 is damaged, and the first multiplexer 141 selects to output data from the redundant data bus 400, that is, the redundant storage array 230 replaces the data bit storage array 210; when the data bit read enable signal Readkill0 is 1, it indicates that the corresponding data bit storage array 210 is not damaged, and the first multiplexer 141 selects to output data from the normal error correction unit 151, that is, the data read by the data bit read unit 111 is output normally.

[0078] In one embodiment, the normal error correction unit 151 is used to send the data information output by the data bit reading unit 111 directly to the first multiplexer 141 when the error detection information is invalid. The invalid error detection information means that the read data information is the same as the written data information, and there is no need to perform error correction on the read data information.

[0079] In one embodiment, the normal error correction unit 151 is used to correct the data information output by the data bit reading unit 111 according to the error detection information when the error detection information is valid, so as to update the data information, and send the updated data information to the first multiplexer 141. The error detection information is valid, that is, the read data information is different from the written data information, and the read data information needs to be corrected according to the error detection information, so as to achieve the correct output of the data information.

[0080] In one embodiment, the normal error correction unit 151 is further used to send updated data information to the corresponding data bit storage array 210 when the error detection information is valid, so as to update the data information stored in the normal storage array 200. When the read data information is different from the written data information, the data information stored in the corresponding data bit storage array 210 also has the risk of error. Therefore, this embodiment can improve the accuracy of the stored data information by updating the data information stored in the data bit storage array 210, thereby reducing the error correction amount of the normal error correction unit 151 and improving the operating speed of the data transmission circuit.

[0081] In one embodiment, the redundant read module 113 is used to send the data read by the redundant read module 113 to the redundant data bus 400 when the redundant read enable signal Read Repair is valid; the first multiplexer 141 is used to select and output the data on the redundant data bus 400 when the data bit read enable signal Read kill0 is invalid. Through the above reading method, the redundant storage array 230 can replace the damaged data storage array.

[0082] In one embodiment, the error detection operation module 300 is also used to output error detection information corresponding to the redundant reading module 113, and the data transmission circuit further includes: a redundant error correction unit 152, which is respectively connected to the redundant reading module 113, the error detection operation module 300 and the redundant data bus 400, and the redundant error correction unit 152 is used to update the data output by the redundant reading module 113 according to the error detection information when the error detection information is valid and the redundant read enable signal Read Repair is valid, and send the updated data to the redundant data bus 400. In this embodiment, the redundant error correction unit 152 is used to correct the data read by the redundant reading module 113, so as to achieve the reading accuracy of the redundant reading module 113.

[0083] Figure 3 is a structural diagram of a data transmission circuit of yet another embodiment, Figure 3 The multiple modules and units related to the data writing process are shown in FIG. Figure 3 In the present embodiment, in one of the embodiments, the data transmission circuit further includes a flag bit writing unit 122 , a redundant writing module 123 and a plurality of data bit writing units 121 .

[0084] The plurality of data bit writing units 121 are connected to the plurality of data bit storage arrays 210 in one-to-one correspondence, and are also connected to the redundant data bus 400, and are used to send data information to the data bit storage array 210 or the redundant data bus 400;

[0085] The flag bit writing unit 122 is connected to the flag bit storage array 220 and the redundant data bus 400 respectively, and is used to send flag information to the flag bit storage array 220 or the redundant data bus 400;

[0086] The redundant writing module 123 is connected to the redundant storage array 230 and the redundant data bus 400 , respectively, and is used to write the data on the redundant data bus 400 into the redundant storage array 230 .

[0087] The data bit write enable signal Write killn matches the aforementioned data bit read enable signal Read killn, that is, if the data bit storage array 210 is damaged, its read and write functions are replaced by the redundant storage array 230 .

[0088] Specifically, taking the first data bit reading unit 111 and the data bit write enable signal Write kill0 as an example, when the data bit write enable signal Write kill0 is 0, it means that the corresponding data bit storage array 210 is damaged, then the data bit writing unit 121 sends the received data information to the redundant data bus 400, and sends the preset data to the flag encoding module 500 through the write operation unit 161 to reduce the encoding complexity of the flag encoding module 500, and the redundant writing module 123 obtains the data information from the redundant data bus 400 and writes it to the redundant storage array 230. When the data bit write enable signal Write kill0 is 1, it means that the corresponding data bit storage array 210 is not damaged, then the data bit writing unit 121 sends the received data information to the corresponding data bit storage array 210, thereby realizing the normal storage of the data information.

[0089] In one embodiment, the data transmission circuit further includes: a flag encoding module 500, which is connected to the data bit writing unit 121 and the flag writing unit 122, respectively, and is used to receive the data information output by the data bit writing unit 121, encode the data to generate flag information, and send the flag information to the flag writing unit 122. The flag encoding module 500 encodes the written data information according to a preset rule to generate unique flag information, and sends the generated flag information to the flag writing unit 122, so as to store the flag information for error detection when the data information is read.

[0090] Figure 4 is a structural diagram of a data transmission circuit of yet another embodiment, Figure 4 The multiple modules and units related to the data writing and reading process are shown in FIG. Figure 4In this embodiment, the data transmission circuit further includes a second multiplexer 171, the two input ends of the second multiplexer 171 are respectively connected to the data bit reading unit 111 and the data bit writing unit 121, and the second multiplexer 171 is used to conduct the data transmission path between any input end and the output end in a time-sharing manner under the control of the read / write enable signal Wr / Rd, so as to realize the time-sharing writing and reading functions of the data. Figure 4 In the embodiment, the error detection operation module 300 and the flag encoding module 500 are integrated to improve the integration of the memory. In other embodiments, the error detection operation module 300 and the flag encoding module 500 can also be set separately.

[0091] Specifically, the first data bit reading unit 111 and the data bit read enable signal Read kill0 are taken as examples for specific description. When writing data, the data bit writing unit 121 obtains the data information to be written from the data pin area 240. When the data bit storage array 210 is not damaged, the corresponding data bit write enable signal Write kill0 is 1, and the data bit writing unit 121 sends the data information to the data bit storage array 210 and the flag encoding module 500 respectively to store and encode the data information.

[0092] When the data bit storage array 210 is damaged, the corresponding data bit write enable signal Write kill0 is 0, so that the data transmission path between the data bit write unit 121 and the redundant data bus 400 is turned on, so the data bit write unit 121 will also send the data information to the redundant data bus 400. The flag encoding module 500 is used to encode the received data information according to the preset encoding rule to generate flag information, and send the flag information to the flag writing unit 122 for storage. When there is a data bit write enable signal Write kill0 that is 0, the redundant write enable signal Write Repair is 1, the data transmission path between the redundant data bus 400 and the redundant write module 123 is turned on, and the redundant write module 123 obtains the data information to be written from the redundant data bus 400 and stores it.

[0093] During data reading, when the data bit storage array 210 is not damaged, the corresponding data bit read enable signal Readkill0 is 1, the data bit reading unit 111 reads data information from the corresponding data bit storage array 210, and sends the read data information to the normal error correction unit 151, the flag encoding module 500 and the error detection operation module 300, and at the same time, the logic operation unit 131 sends the preset data to the second multiplexer 171 under the control of the redundant read enable signal Read Repair. The flag encoding module 500 encodes according to the received data information to generate the flag information corresponding to the read data information, the error detection operation module 300 receives the flag information corresponding to the read data information, and obtains the flag information corresponding to the written data information from the flag bit reading unit 112, the error detection operation module 300 compares the two flag information to generate error detection information, and the normal error correction unit 151 corrects the read data information according to the error detection information and outputs it to the data pin area 240.

[0094] When the data bit storage array 210 is damaged, the corresponding data bit read enable signal Read kill0 is 0, and the redundant read enable signal Read Repair is 1. The redundant read module 113 sends the read data to the redundant error correction unit 152, the flag encoding unit and the error detection operation module 300 to perform error detection and correction steps. At the same time, the logic operation module corresponding to the damaged data bit storage array 210 sends the preset data value to the error detection operation module 300, thereby simplifying the operation complexity of the error detection operation module 300. After the redundant error correction unit 152 processes the received data information, it sends the data information to the redundant data bus 400. The data bit read enable signal Read kill0 enables the data transmission path between the first multiplexer 141 corresponding to the damaged data bit storage array 210 and the redundant data bus 400 to be turned on. The first multiplexer 141 corresponding to the damaged data bit storage array 210 obtains the data information from the redundant data bus 400 and sends the data information to the data pin area 240 under the control of the data bit read enable signal Read kill0.

[0095] The embodiment of the present application also provides a memory, including: a plurality of normal memory arrays 200; a redundant memory array 230; a plurality of data pin areas 240, the data pin areas 240 corresponding to the normal memory arrays 200 one by one; and a data transmission circuit as described above, the data transmission circuit is respectively connected to the redundant memory array 230, the normal memory array 200 and the data pin area 240. The memory of this embodiment does not need to perform the step of querying the address of the damaged normal memory array 200 first, regardless of whether the normal memory array 200 is damaged, which simplifies the serial steps of data reading, thereby realizing a memory with a faster reading speed.

[0096] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A data transmission circuit, characterized in that: The data transmission circuit comprises: A normal reading module is connected to a normal storage array; A redundant read module connected to a redundant storage array; wherein the normal read module and the redundant read module are used to synchronously read and output data from the normal storage array and the redundant storage array respectively; an error detection operation module, connected to the normal reading module and the redundant reading module respectively; wherein the error detection operation module is used to synchronously receive the read data output by the normal reading module and the redundant reading module, and perform an error detection operation on the read data; The normal storage array includes a flag bit storage array and a plurality of data bit storage arrays, and the normal reading module includes: A plurality of data bit reading units, each of which is connected to the data bit storage array in a one-to-one correspondence and is used to read data information from the corresponding data bit storage array; A flag reading unit, connected to the flag storage array, and used for reading flag information from the flag storage array; The flag information is uniquely generated according to the data information and is used to reversely judge whether the data information is wrong.

2. The data transmission circuit according to claim 1, characterized in that: Also includes: A plurality of logic operation units, one input end of some of the logic operation units is connected to the data bit reading unit, one input end of some of the logic operation units is connected to the flag bit reading unit, one input end of some of the logic operation units is connected to the redundant reading module, another input end of each of the logic operation units is connected to an enable signal, an output end of each of the logic operation units is connected to the error detection operation module, and each of the logic operation units is used to perform a preset operation on the data input from the two input ends, and send the operation result to the error detection operation module.

3. The data transmission circuit according to claim 2, characterized in that: The logic operation unit is a logic AND unit, one input end of the logic AND unit is connected to one of the data bit reading unit, the flag bit reading unit and the redundant reading module, the other input end of the logic AND unit is connected to the enable signal, the output end of the logic AND unit is connected to the error detection operation module, and the logic operation unit is used to perform a logic AND operation on the data input from the two input ends, and send the operation result to the error detection operation module.

4. The data transmission circuit according to claim 3, characterized in that: Also includes: An enable control module is connected to the plurality of logic AND units respectively, the enable control module is used to generate a redundant read enable signal and a plurality of data bit read enable signals, the data bit read enable signal corresponds to the data bit read unit one-to-one, the redundant read enable signal corresponds to the redundant read module, and the enable control module is further used to send the redundant read enable signal and the data bit read enable signal to the logic AND unit one-to-one; When the redundant read enable signal is valid, one of the multiple data bit read enable signals is invalid; when the redundant read enable signal is invalid, all of the multiple data bit read enable signals are valid.

5. The data transmission circuit according to claim 4, characterized in that: The error detection operation module is used to output a plurality of error detection information, wherein the error detection information corresponds to the data bit reading unit one by one, and the data transmission circuit further includes: A normal error correction unit, connected to the data bit reading unit in a one-to-one correspondence, and also connected to the error detection operation module, the normal error correction unit is used to receive the error detection information, and update the corresponding data information output by the data bit reading unit according to the error detection information; A redundant data bus connected to the redundant reading module and used for receiving data output by the redundant reading module; A plurality of first multiplexers, wherein the first multiplexers correspond one-to-one to the normal error correction units, one input end of the first multiplexer is connected to the corresponding normal error correction unit, another input end of the first multiplexer is connected to the redundant data bus, and the first multiplexer is used to receive a data bit read enable signal and select to output data input from any of the input ends under the control of the data bit read enable signal.

6. The data transmission circuit according to claim 5, characterized in that: The normal error correction unit is used for sending the data information output by the data bit reading unit to the first multiplexer when the error detection information is invalid.

7. The data transmission circuit according to claim 5, characterized in that: The normal error correction unit is used for correcting the data information output by the data bit reading unit according to the error detection information when the error detection information is valid, so as to update the data information, and send the updated data information to the first multiplexer.

8. The data transmission circuit according to claim 7, characterized in that: The normal error correction unit is further configured to send the updated data information to the corresponding data bit storage array when the error detection information is valid, so as to update the data information stored in the normal storage array.

9. The data transmission circuit according to claim 5, characterized in that: The redundant read module is used for sending the data read by the redundant read module to the redundant data bus when the redundant read enable signal is valid; The first multiplexer is used for selecting and outputting data on a redundant data bus when the data bit read enable signal is invalid.

10. The data transmission circuit according to claim 5, characterized in that: The error detection operation module is also used to output error detection information corresponding to the redundant reading module, and the data transmission circuit also includes: A redundant error correction unit, wherein the redundant error correction unit is respectively connected to the redundant read module, the error detection operation module and the redundant data bus, and the redundant error correction unit is used to update the data output by the redundant read module according to the error detection information when the error detection information is valid and the redundant read enable signal is valid, and send the updated data to the redundant data bus.

11. The data transmission circuit according to claim 5, characterized in that: Also includes: A plurality of data bit writing units are connected to the plurality of data bit storage arrays in a one-to-one correspondence and are also connected to the redundant data bus, and are used to send data information to the data bit storage array or the redundant data bus; a flag bit writing unit, connected to the flag bit storage array and the redundant data bus respectively, and used for sending flag information to the flag bit storage array or the redundant data bus; The redundant writing module is connected to the redundant storage array and the redundant data bus respectively, and is used for writing the data on the redundant data bus into the redundant storage array.

12. The data transmission circuit according to claim 11, characterized in that: Also includes: The flag encoding module is connected to the data bit writing unit and the flag writing unit respectively, and is used to receive the data information output by the data bit writing unit, encode the data to generate the flag information, and send the flag information to the flag writing unit.

13. A memory, characterized in that: include: Multiple normal storage arrays; Redundant storage arrays; A plurality of data pin areas, wherein the data pin areas correspond one to one with the normal storage array; The data transmission circuit according to any one of claims 1 to 12, wherein the data transmission circuit is connected to the redundant memory array, the normal memory array and the data pin area respectively.

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