Chip and electronic device with built-in reconfigurable coprocessor

Abstract

The embodiment of the present application discloses a chip and electronic device with a built-in reconfigurable coprocessor, which relates to the field of control. The chip with a built-in reconfigurable coprocessor includes: a main processor and a coprocessor including multiple algorithm modules. The main processor can select the required algorithm module from multiple algorithm modules according to actual needs to reconstruct the control loop, and use the control loop to execute the calculation process, thereby solving the problem of excessive processor overhead caused by the main processor using its own processor core to execute the calculation process in the related technology. The present application makes full use of the computing power of each algorithm module in the coprocessor, and hardly consumes the computing power of the main processor, so there is no need to increase the size of the processor. In addition, directly using modular algorithm modules to reconstruct the control loop can reduce the difficulty of developing control algorithms and improve development efficiency.

Description

Technical Field

[0001] The invention relates to the field of control, and in particular to a chip and electronic equipment with a built-in reconfigurable coprocessor. Background Art

[0002] With the continuous improvement of industrial intelligence, the functions required of industrial products are becoming more diversified and complex, and the corresponding performance requirements for the main control chips in industrial products are also getting higher and higher. In order to improve the processing performance of the main control chip, the efficiency of program execution (especially algorithms) is generally improved by increasing the main frequency of the main control chip. Therefore, many main control chips in the industrial control field are developing in the direction of high main frequency. At the same time, in order to meet the needs of users for multiple algorithms, the chip memory size is continuously expanded, resulting in an increase in the size of the chip. Summary of the invention

[0003] The embodiment of the present application provides a chip and an electronic device with a built-in reconfigurable coprocessor, which can solve the problem of large processor size caused by increasing the processing performance by increasing the main frequency of the chip in the related art. The technical solution is as follows:

[0004] In a first aspect, an embodiment of the present application provides a chip with a built-in reconfigurable coprocessor, including:

[0005] Main processor and coprocessor;

[0006] The main processor is connected to the coprocessor via a bus, the coprocessor includes N algorithm modules, N is an integer greater than 1, and each algorithm module is implemented in hardware form;

[0007] The main processor is used to select at least one algorithm module from the N algorithm modules, and use the selected algorithm module to form a control loop, start the control loop to perform calculation, and read the calculation result of the control loop.

[0008] In a second aspect, the present application provides an electronic device, comprising: a chip including any one of the above-mentioned built-in reconfigurable coprocessors.

[0009] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:

[0010] Based on the dual-core architecture that combines a reconfigurable coprocessor with a main controller, multiple algorithm modules are integrated into one coprocessor. At the same time, multiple access methods to the coprocessor are used to ensure user flexibility, ultimately allowing low-frequency chips to achieve the performance of high-frequency chips. At the same time, users do not need to write algorithm programs in the control field, which saves development and design difficulty, reduces the storage space required for the chip, and reduces chip costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0012] Figure 1 is a structural diagram of a chip with a built-in reconfigurable coprocessor provided by an embodiment of the present invention;

[0013] Figure 2 is another structural diagram of a chip with a built-in reconfigurable coprocessor provided by an embodiment of the present invention;

[0014] Figure 3 is another structural diagram of a chip with a built-in reconfigurable coprocessor provided by an embodiment of the present invention;

[0015] Figure 4 is another structural diagram of a chip with a built-in reconfigurable coprocessor provided by an embodiment of the present invention;

[0016] Figure 5 is another structural diagram of a chip with a built-in reconfigurable coprocessor provided by an embodiment of the present invention;

[0017] Figure 6 4 is another structural diagram of a chip with a built-in reconfigurable coprocessor provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] See also Figure 1 to Figure 6 The present invention provides a schematic structural diagram of a chip with a built-in reconfigurable coprocessor according to an embodiment. The chip with a built-in reconfigurable coprocessor includes: a main processor, a coprocessor and a memory.

[0020] The main processor and the coprocessor are connected via an off-chip bus, which can provide a high-speed signal transmission channel between the main processor and the coprocessor. The coprocessor includes N algorithm modules, where N is an integer greater than 1. Each algorithm module is a hardware-implemented module, for example, the algorithm module can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). For example, the algorithm module may be: FFT (Fast Fourier Transform) module, DFT (Discrete Fourier Transform) module, IIR (Infinite Impulse Response) module, FIR (Finite Impulse Response) module, SIN (sine) module, COS (cosine) module, ARCTAN (inverse tangent) module, MATRIX (matrix operation) module, SINH (hyperbolic sine function) module, COSH (hyperbolic cosine function) module, DIV (integer division) module, HCC module, RMS (root mean square) module or ECU module, wherein the number of algorithm modules of the same type may be multiple, for example, the coprocessor includes 2 FFT modules.

[0021] Among them, the main processor calls the program code stored in the memory to select at least one algorithm module from N algorithm modules, forms a control loop with the selected algorithm modules, starts the control loop for calculation, and the control loop uses a given input signal for calculation. The input signal can be from inside the main processor or from outside the main processor, and this application does not limit it. The main processor reads the calculation result after detecting that the control loop has completed the calculation process. In the control loop, the output of one algorithm module may be the input of another algorithm module. The topological structure of the control loop can be determined according to actual needs, and this application does not limit it.

[0022] The hardware architecture of the embodiment of the present application adopts a dual-core architecture of a reconfigurable coprocessor + main processor; a variety of connection relationships between the main processor and the coprocessor: connection relationship 1, the main processor can access the resources of the coprocessor through the bus, saving the time occupied by a large number of algorithm operation units of the main processor, and improving the processing task capability and algorithm operation efficiency. Connection relationship 2, through the event management unit module of the main processor, the algorithm module of the coprocessor and the module of the main controller are reconstructed and managed to achieve the effect of multi-core simultaneous operation. These two connection methods can meet the user's demand for the use of algorithm modules, and can also meet the user's demand for the use of multiple modules in series and parallel. They are widely applicable to scenarios and highly flexible, and are very suitable for engineers in the field of industrial control to debug and control the control from multiple angles and directions. In addition, in order to improve the efficiency of the coprocessor in performing algorithm operations, a separate data storage space is allocated for each algorithm module to avoid affecting the data throughput speed in the algorithm module due to bus congestion.

[0023] In one or more possible embodiments, the main processor reads the calculation result in the following manner: the control loop initiates an interrupt request after completing the calculation process, temporarily stores the calculation result, and the main processor reads the calculation result after detecting the interrupt request; or the control loop temporarily stores the calculation result after completing the calculation process, and then sets the status flag of the register to 1. After starting the control loop, the main processor periodically polls the value of the status flag, and reads the calculation result of the control loop when the value of the status flag is 1.

[0024] In one or more possible embodiments, the memory is a non-volatile memory, and each algorithm module is configured with a fixed storage space in the memory to store the intermediate results of each algorithm module respectively.

[0025] See also Figure 2As shown, another structural schematic diagram of a chip with a built-in reconfigurable coprocessor provided in an embodiment of the present application, in an embodiment of the present application, the main processor includes a processor core, the number of which can be one or more, and the processor core is the core of the processor, which is used to process all instructions and data. The processor core is connected to N algorithm modules through a bus. The processor core is used to select at least one algorithm module from the N algorithm modules, and to form a control loop using the selected algorithm module, start the control loop for calculation, and read the calculation result of the control loop. When the number of processor cores is multiple, the processor core with the lightest load can be selected to communicate with the coprocessor according to the load of each processor core. The method for the processor core to read the calculation result can be an interrupt mode or a state indication bit mode. The embodiment of the present application does not need to change the hardware structure of the main processor, and directly uses the processor core to realize the reconstruction of the control loop and the reading of the calculation result, and only consumes a small amount of processing power of the processor core to flexibly realize the control algorithm with different requirements.

[0026] In one or more possible embodiments, the event management module configures the topology of the control loop through registers. There are multiple registers, and the registers store flags. According to the values ​​of the flags, the algorithm module is selected (at least one algorithm module is selected from N algorithm modules), the topology is determined (the previous node and the next node of the current algorithm module are determined), the input signal is selected (one or more input signals can be selected from an external signal source or an internal signal source), and the reading method of the calculation result is determined (interrupt mode or status flag), etc.

[0027] For example, the registers configured in the event management module are shown in Table 1.

[0028] name Offset Size (x32) illustrate CH_ENA 0x00 1 Channel enable control. CH_INT_ENA 0x04 1 Channel interrupt enable control. CPU_KST 0x08 1 CPU channel startup control. CH_PND_CLR 0x10 1 Clear control of channel Pending. CH_CPU_PND 0x14 1 CPU pending flag of the channel CH_HW_PND 0x18 1 The hardware pending flag of the channel. CH_MODE0 0x1C 1 Channel mode selection control. SRC_CH_CON0 0x20-0x5C 1 Source channel trigger signal selection control. SRC_CH_CON1 0x60-0x9C 1 Source channel trigger signal selection control. DST_CH_CON0 0xA0-0xDC 1 Destination channel enable control.

[0029] Table 1

[0030] For example, see Figure 3 As shown, the processor core selects the FFT module in the coprocessor to form a control loop. The input signal is an analog signal. The AD module 1 in the main processor converts the input signal into a digital signal, and inputs the digital signal into the FFT module. The FFT module calculates the input digital signal to obtain a calculation result. The processor core reads the calculation result and then outputs the calculation result to an external device, such as a motor, a digital power supply or an inverter, through a PWM module or a communication interface.

[0031] See also Figure 4, is another structural schematic diagram of a chip with a built-in reconfigurable coprocessor provided in an embodiment of the present application. In the embodiment of the present application, the main processor includes an event management module and a processor core. The event management module is implemented in hardware. The number of processor cores is one or more, and the event management module is connected to each processor core. The event management module is connected to each algorithm module through an off-chip bus. The event management module is used to select at least one algorithm module from N algorithm modules, and to form a control loop using the selected algorithm module, to start the control loop for calculation, and to read the calculation result of the control loop, and to send the calculation result to the processor core. The method for the event management module to read the calculation result can be an interrupt mode or a status indication bit mode. In the embodiment of the present application, an event management module is added to the main processor, and the event management module directly realizes the reconstruction of the control loop and the reading of the calculation result, and the control algorithm with different requirements can be flexibly realized without consuming the processing power of the processor core.

[0032] For example, see Figure 5 As shown, the processor core selects the DFT module, ARCTAN module, SIN module, MATRIX module 1, IIR module 1, FFT module, HCC module, MATRIX module 2, IIR module 2 and addition module (marked by X in the figure) in the coprocessor. The above algorithm modules form a control loop. The topological connection relationship of each algorithm module in the control loop is referenced. Figure 5 As shown, no further description is given here. The AD1 module 1 performs analog-to-digital conversion on the external input signal to obtain digital signal 1, and inputs digital signal 1 into the DFT module. The AD2 module performs analog-to-digital conversion on the external input signal to obtain digital signal 2, and inputs digital signal 2 into the FFT module. The AD3 module performs analog-to-digital conversion on the external input signal to obtain digital signal 3, and inputs digital signal 3 into the addition module. The control loop calculates the above three digital signals to obtain calculation results, and the event management module reads the calculation results and outputs them through the PWM module.

[0033] In one or more possible embodiments, the processor cores and control loops are enabled in parallel, which can improve processing efficiency.

[0034] For example: See Figure 6 As shown, the processor core selects the DFT module, ARCTAN module, SIN module, MATRIX module 1, IIR module 1, FFT module, HCC module, MATRIX module 2, IIR module 2 and addition module (marked by X in the figure) in the coprocessor. The above algorithm modules form a control loop. The topological connection relationship of each algorithm module in the control loop is referenced. Figure 5As shown, no further description is given here. The control loop processes the digital signals input from AD modules 1 to 3 and then outputs them through the PWM module. The processor core processes the digital signals input from the AD module and then outputs them through the communication interface. The processor core and the control loop operate independently of each other, which can improve the chip processing efficiency of the built-in reconfigurable coprocessor.

[0035] The electronic device provided in the embodiment of the present application may further include, in addition to the above-mentioned chip with a built-in reconfigurable coprocessor, a housing for accommodating various components.

[0036] The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.

Claims

1. A chip with a built-in reconfigurable coprocessor, characterized in that: include: Main processor and coprocessor; The main processor is connected to the coprocessor via a bus, the coprocessor includes N algorithm modules, N is an integer greater than 1, and each algorithm module is implemented in hardware form; The main processor includes: an event management module and a processor core; the event management module is connected to the N algorithm modules via a bus; The event management module is used to select at least one algorithm module from the N algorithm modules, and use the selected algorithm module to form a control loop, start the control loop to perform calculations, and read the calculation results of the control loop; the processor core and the control loop run in parallel; The event management module is configured with registers; the registers are used to select an algorithm module, determine a topological structure, select an input signal, and determine a method for reading a calculation result.

2. The chip according to claim 1, characterized in that: Also includes: Memory; Each algorithm module is allocated a fixed storage space in the memory.

3. The chip according to claim 2, characterized in that: Reading the calculation result of the control loop by interruption; or The calculation result of the control loop is read through the status flag bit.

4. The chip according to claim 3, characterized in that: The algorithm module is a digital signal processing module.

5. The chip according to claim 1, characterized in that: The main processor also includes: an AD module, a clock circuit, a communication interface and a PWM module; Wherein, the clock circuit is used to provide clock signals for the main processor and the coprocessor; The AD module is used to convert analog signals into digital signals; The communication interface is used to communicate with external devices; The PWM module is used to generate a PWM signal according to the calculation result.

6. An electronic device, characterized in that: A chip comprising any one of claims 1-5 having a built-in reconfigurable coprocessor.

Images