Trench MOSFET Devices

Abstract

The present invention provides a trench MOSFET device, comprising: a first epitaxial layer of a first doping type located on a substrate; a first conductive layer of a second doping type, the first conductive layer of the second doping type is located in the first epitaxial layer of the first doping type, and the second doping type is opposite to the first doping type; a second epitaxial layer of the first doping type, the second epitaxial layer of the first doping type is located on the surface of the first epitaxial layer of the first doping type and the surface of the first conductive layer of the second doping type; a body region; a second conductive layer located in the second epitaxial layer of the first doping type, the second conductive layer connects the first conductive layer of the second doping type and the body region. Based on the trench MOSFET device of the present invention, the withstand voltage BV of the trench MOSFET device is improved, Crss / Ciss is reduced, and the reliability of the trench MOSFET device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more specifically, to a trench MOSFET device. Background Art

[0002] Power MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) is a multi-subconducting device with a wide variety of types and rapid changes. This is the current status of power MOSFET application. Power MOSFET is mainly trench power MOSFET. Trench MOSFET is a device with a vertical conductive channel. When the trench MOSFET is in the on state, the current will flow vertically from the drain end to the source end. Trench MOSFET has the advantages of low on-resistance, small gate leakage current, and high switching rate. These advantages make it widely used in industrial control, aerospace, communication, automobile, computer and portable appliances, home appliances, office supplies and other fields, especially in the application of switching power supply. It has achieved rapid development and greatly improved the efficiency of electronic systems. Traditional trench MOSFET has a broad market in the field of medium and low voltage devices with a withstand voltage of 20V to 200V due to its mature manufacturing process and low unit price.

[0003] like Figure 1 As shown, it is a schematic diagram of the structure of the existing trench MOSFET, Ciss and Crss are the input capacitance and feedback capacitance of the MOS tube respectively. By observing the inter-electrode capacitance and parasitic gate charge Qg of the trench MOSFET tube, it can be seen that the inter-electrode capacitance of the MOS tube is determined by its conductive channel structure and process. In order to reduce Qg and Crss / Ciss, the existing trench MOSFET preparation method injects impurities into the epitaxial layer 102 on the substrate 101 after the trench 103 is etched, and the substrate 101 is subjected to a high-temperature process to form a floating region 104 in the drift region at the bottom of the trench 103. The floating region 104 prepared according to the existing preparation method is a floating potential.

[0004] During the process of forming the body region 205, the potential suspended 104 is affected by factors such as hot carriers and plasma injection, resulting in unstable and uncontrollable Qg and Crss / Ciss, which has an adverse effect on reducing Qg and Crss / Ciss, and affects the reliability of the device. Under the premise of not affecting the withstand voltage, Qg and Crss / Ciss are reduced, and the performance of trench MOSFET is continuously improved and enhanced, so that trench MOSFET applications can gain a larger market. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a trench MOSFET device.

[0006] To achieve the above-mentioned object, the first aspect of the present invention provides a trench MOSFET device, characterized in that it comprises: a substrate; a first epitaxial layer of a first doping type located on the substrate; a first trench located in the first epitaxial layer of the first doping type, the first trench extending longitudinally from the top of the first epitaxial layer of the first doping type to the bottom of the substrate and terminating in the first epitaxial layer of the first doping type, and the first trench having a first trench width horizontal to the substrate surface direction and a first trench height perpendicular to the substrate surface direction; a first conductive layer of a second doping type, the first conductive layer of the second doping type being located at the bottom of the first trench, the second doping type being opposite to the first doping type; the first conductive layer of the second doping type having a first conductive layer height perpendicular to the substrate surface direction and a first conductive layer width horizontal to the substrate surface direction, the first conductive layer The height of the conductive layer is less than or equal to the height of the first trench; the second epitaxial layer of the first doping type, the second epitaxial layer of the first doping type is located on the surface of the first epitaxial layer of the first doping type and the surface of the first conductive layer of the second doping type; the second trench, the second trench is located in the second epitaxial layer of the first doping type above the first conductive layer of the second doping type, and the bottom surface of the second trench is higher than the surface of the first conductive layer of the second doping type, and the second trench has a second trench width horizontal to the substrate surface direction; the body region, the body region is located in the second epitaxial layer of the first doping type and is adjacent to the second trench, and part of the body region is located above the first conductive layer of the second doping type; the third trench, the third trench is located in the second epitaxial layer of the first doping type, the third trench penetrates the body region and exposes part of the surface of the first conductive layer of the second doping type. The second conductive layer, the second conductive layer fills the third trench, and the second conductive layer connects the first conductive layer of the second doping type and the body region.

[0007] Preferably, the width of the first conductive layer is 80% to 100% of the width of the second groove.

[0008] Preferably, the bottom surface of the second trench is 0.1 um to 0.5 um higher than the surface of the first conductive layer of the second doping type.

[0009] Preferably, the first conductive layer has a height of 0.2 um to 0.8 um.

[0010] Preferably, the resistance of the second conductive layer is lower than the resistance of the first conductive layer of the second doping type.

[0011] Preferably, the resistivity of the first epitaxial layer of the first doping type is lower than the resistivity of the first conductive layer of the second doping type; the resistivity of the second epitaxial layer of the first doping type is lower than the resistivity of the first conductive layer of the second doping type.

[0012] Preferably, the resistivity of the first epitaxial layer of the first doping type is 1 to 5 times lower than the resistivity of the first conductive layer of the second doping type; the resistivity of the second epitaxial layer of the first doping type is 1 to 5 times lower than the resistivity of the first conductive layer of the second doping type.

[0013] Preferably, the material of the first conductive layer of the second doping type and / or the material of the second conductive layer are semiconductor materials.

[0014] Preferably, the material of the second conductive layer includes metal material.

[0015] Preferably, the material of the first conductive layer of the second doping type is the same as the material of the second conductive layer.

[0016] Preferably, it also includes: a first trench located in the first epitaxial layer of the first doping type, the first trench longitudinally extending from the top of the first epitaxial layer of the first doping type to the bottom of the substrate and terminating in the first epitaxial layer of the first doping type, and the first trench has a first trench width horizontal to the substrate surface direction and a first trench height perpendicular to the substrate surface direction; the first conductive layer of the second doping type is located at the bottom of the first trench, and the height of the first conductive layer is less than or equal to the first trench height.

[0017] Preferably, the height of the first conductive layer is smaller than the height of the first trench, and the second epitaxial layer of the first doping type fills the first trench.

[0018] Preferably, it also includes: a source region located in the body region; the third trench penetrates the body region and the source region, and the second conductive layer connects the source region, the body region and the first conductive layer of the second doping type.

[0019] A second aspect of the present invention provides a method for preparing a trench MOSFET device, comprising: step S01, providing a substrate, and forming a first epitaxial layer of a first doping type on the surface of the substrate; step S02, forming a first trench in the first epitaxial layer of the first doping type; step S03, forming a first conductive layer of a second doping type in the first trench; step S04, forming a second epitaxial layer of the first doping type on the surface of the first epitaxial layer of the first doping type and the surface of the first conductive layer of the second doping type; step S05, forming a second trench in the second epitaxial layer of the first doping type above the first conductive layer of the second doping type; step S06: depositing a gate dielectric layer on the inner wall and bottom of the second trench; step S07: forming a gate electrode layer filling the second trench on the gate dielectric layer; step S08, forming a body region in the second epitaxial layer of the first doping type; step S09, forming a third trench penetrating the body region in the second epitaxial layer of the first doping type; step S10, forming a second conductive layer in the third trench.

[0020] Preferably, the first trench extends longitudinally from the top of the first epitaxial layer of the first doping type to the bottom of the substrate and terminates in the first epitaxial layer of the first doping type, and the first trench has a first trench width horizontal to the substrate surface direction and a first trench height perpendicular to the substrate surface direction; the first conductive layer of the second doping type has a first conductive layer height perpendicular to the substrate surface direction and a first conductive layer width horizontal to the substrate surface direction, and the first conductive layer height is less than or equal to the first trench height.

[0021] Preferably, the height of the first conductive layer is smaller than the height of the first trench, and the second epitaxial layer of the first doping type further fills the first trench.

[0022] Preferably, the formation of the second doping type first conductive layer comprises one or more combinations of flowing chemical vapor deposition (FCVD), spin coating, high density plasma (HDP) chemical vapor deposition (CVD), and ion implantation processes.

[0023] Preferably, the formation of the second conductive layer comprises one or more combinations of flowing chemical vapor deposition (FCVD), spin coating, high density plasma (HDP) chemical vapor deposition (CVD), and ion implantation processes.

[0024] Preferably, it also includes: doping the body region to form a source region in the body region; the third trench also penetrates the source region, and the second conductive layer connects the source region, the body region and the first conductive layer of the second doping type.

[0025] In the trench MOSFET device prepared based on the method of the present invention, the second conductive layer connects the first conductive layer of the second doping type located in the first epitaxial layer of the first doping type and the body region, so that the equipotential of the first conductive layer of the second doping type and the body region is achieved, and the drift region located at the bottom of the second trench is depleted laterally and vertically, thereby improving the withstand voltage BV of the trench MOSFET device, reducing Qg and controlling the hot carrier injection introduced in the process, reducing Crss / Ciss, and thus improving the reliability of the trench MOSFET device; at the same time, by adjusting the height and width of the first conductive layer, the current loss is reduced, the heat generation of the device is reduced, compatibility with the existing MOSFET device process technology, and the stability of the device is improved, which has significant significance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A schematic diagram of the structure of an existing trench MOSFET

[0028] Figure 2 A flowchart showing the preparation of a trench MOSFET according to an embodiment of the present invention is shown.

[0029] Figures 3 to 6 A schematic cross-sectional diagram of stages of preparation of a trench MOSFET according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0030] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0031] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly above the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0032] If it is to describe the situation of being directly located on another layer or another region, the expression "A is directly on B" or "A is on B and adjacent to it" will be used herein. In the present invention, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0033] Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques and technologies of the semiconductor device, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0034] Unless otherwise specified below, the various layers or regions of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si and Ge. The gate conductor and electrode layer may be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of the various conductive materials. The gate dielectric may be composed of SiO2 or a material having a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, and titanates. Furthermore, the gate dielectric may be formed not only of materials known to those skilled in the art, but also of materials developed in the future for the gate dielectric.

[0035] In the present invention, the term "semiconductor structure" refers to the entire semiconductor structure formed in various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "lateral extension" refers to extension in a direction substantially perpendicular to the depth direction of the trench.

[0036] The present invention provides a trench MOSFET structure, comprising: a substrate; a first epitaxial layer of a first doping type located on the substrate; a first trench located in the first epitaxial layer of the first doping type, the first trench longitudinally extending from the top of the first epitaxial layer of the first doping type to the bottom of the substrate and terminating in the first epitaxial layer of the first doping type, and the first trench having a first trench width horizontal to the substrate surface direction and a first trench height vertical to the substrate surface direction; a first conductive layer of a second doping type, the first conductive layer of the second doping type being located at the bottom of the first trench, the second doping type being opposite to the first doping type; the first conductive layer of the second doping type having a first conductive layer height vertical to the substrate surface direction and a first conductive layer width horizontal to the substrate surface direction, the first conductive layer height being less than or equal to The height of the first trench; the second epitaxial layer of the first doping type, the second epitaxial layer of the first doping type is located on the surface of the first epitaxial layer of the first doping type and the surface of the first conductive layer of the second doping type; the second trench, the second trench is located in the second epitaxial layer of the first doping type above the first conductive layer of the second doping type, and the bottom surface of the second trench is higher than the surface of the first conductive layer of the second doping type, and the second trench has a second trench width horizontal to the substrate surface direction; the body region, the body region is located in the second epitaxial layer of the first doping type and is adjacent to the second trench, and part of the body region is located above the first conductive layer of the second doping type; the third trench, the third trench is located in the second epitaxial layer of the first doping type, the third trench penetrates the body region and exposes part of the surface of the first conductive layer of the second doping type. The second conductive layer, the second conductive layer fills the third trench, and the second conductive layer connects the first conductive layer of the second doping type and the body region.

[0037] The present invention may be embodied in various forms, some examples of which will be described below.

[0038] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples. Figure 2 FIG. 1 is a flow chart showing the preparation of a trench MOSFET according to an embodiment of the present invention. Figures 3 to 6 A schematic cross-sectional diagram of stages of preparation of a trench MOSFET according to an embodiment of the present invention is shown.

[0039] See also Figure 2 , Figure 2 A total of 10 steps are shown below. Figure 2 See also Figure 3-Figure 6 :

[0040] Step S01 : providing a substrate 201 , and forming a first epitaxial layer 212 of a first doping type on a surface of the substrate 201 .

[0041] Step S02 , forming a first trench (not shown) in the first epitaxial layer 212 of the first doping type.

[0042] Step S03: forming a first conductive layer 203 of a second doping type in the first trench.

[0043] Step S04 , forming a second epitaxial layer 222 of the first doping type on a surface of the first epitaxial layer 212 of the first doping type and a surface of the first conductive layer 203 of the second doping type.

[0044] See also Figure 3 , Figure 3 It is a schematic cross-sectional diagram of the stages from step S01 to step S04. In the present embodiment, the substrate 201 is a silicon substrate, but the present invention does not impose any restrictions on the material of the substrate 201. In other embodiments, materials such as germanium or silicon germanium can also be used as the substrate 201. The substrate 201 also includes other conductor layers between the substrate 201 and the first epitaxial layer 212 of the first doping type. In order to reduce the instability of the interface between the substrate 201 and the first epitaxial layer 212 of the first doping type due to defects in the substrate 201, the doping type of the conductor layer is the same as that of the epitaxial layer 102.

[0045] The first epitaxial layer 212 of the first doping type can be formed as an initial first epitaxial layer by chemical vapor deposition. The thickness of the initial first epitaxial layer is set according to the specific situation. During the deposition process of the initial first epitaxial layer, the first epitaxial layer 212 of the first doping type is formed by doping. Specifically, the initial first epitaxial layer is a silicon epitaxial layer. After N-doping or P-doping, an N-type first epitaxial layer 212 of the first doping type or a P-type first epitaxial layer 212 of the first doping type is formed. After the deposition process of the first epitaxial layer 212 of the first doping type is completed, the surface of the first epitaxial layer 212 of the first doping type is processed and flattened by chemical mechanical polishing, and the substrate 201 is used as the drain of the trench MOSFET. The first epitaxial layer 212 of the first doping type can also be implanted with an N-type dopant (e.g., P, As) on the surface of the substrate 201; in order to form a P-type first epitaxial layer 212 of the first doping type, a P-type dopant (e.g., B) can be implanted on the surface of the substrate 201.

[0046] The formation of the first conductive layer 203 of the second doping type includes: forming a first trench (not shown) in the first epitaxial layer 212 of the first doping type, the first trench extending longitudinally from the top of the first epitaxial layer 212 of the first doping type to the bottom of the substrate 201 and terminating in the first epitaxial layer 212 of the first doping type, and the first trench having a first trench width horizontal to the direction of the substrate 201 and a first trench height vertical to the direction of the substrate 201; forming a first conductive layer 203 of the second doping type at the bottom of the first trench, the first conductive layer 203 of the second doping type having a second doping type, and the second doping type is opposite to the first doping type, and in the present invention, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

[0047] The first conductive layer 203 of the second doping type has a first conductive layer height perpendicular to the surface direction of the substrate 201 and a first conductive layer width horizontal to the surface direction of the substrate 201, and the first conductive layer height is less than or equal to the first trench height. The material of the first conductive layer 203 of the second doping type is a semiconductor material, the resistivity of the first epitaxial layer 212 of the first doping type is lower than the resistivity of the first conductive layer 203 of the second doping type, the first conductive layer width is equal to the first trench width, and the first conductive layer height is less than or equal to the first trench height; the first conductive layer height is 0.2um to 0.8um. ​​In this embodiment, the resistivity of the first epitaxial layer 212 of the first doping type is 1 to 5 times lower than the resistivity of the first conductive layer of the second doping type. In this embodiment, the first conductive layer height is less than the first trench height, and the second epitaxial layer 222 of the first doping type also fills the first trench. The formation of the first conductive layer 203 of the second doping type includes an ion implantation process. In another embodiment, a mask is formed on the surface of the first epitaxial layer 212 of the first doping type. After the first conductive layer 203 of the second doping type is formed inside the first epitaxial layer 212 of the first doping type by the ion implantation process, a second epitaxial layer 222 of the first doping type is formed on the first epitaxial layer 212 of the first doping type. The second epitaxial layer 222 of the first doping type covers the surface of the first epitaxial layer 212 of the first doping type and the surface of the first conductive layer 203 of the second doping type. The preparation of the second epitaxial layer 222 of the first doping type is the same as that of the first epitaxial layer 212 of the first doping type. The material of the second epitaxial layer 222 of the first doping type is the same as that of the first epitaxial layer 212 of the first doping type, and no further description is given on this basis.

[0048] Step S05 , forming a second trench 204 in the second epitaxial layer 222 of the first doping type above the first conductive layer 203 of the second doping type.

[0049] See also Figure 4 ,like Figure 4 As shown, in this embodiment, a second trench 204 is formed in the second epitaxial layer 222 of the first doping type by photolithography and etching technology, and the second trench 204 extends longitudinally from the top of the second epitaxial layer 222 of the first doping type to the bottom of the substrate 201 and terminates in the second epitaxial layer 222 of the first doping type, and the bottom surface of the second trench 204 is 0.1um to 0.5um higher than the surface of the first conductive layer 203 of the second doping type. The etching technology includes one of dry etching or wet etching, and the width of the first conductive layer is 80% to 100% of the width of the second trench. By adjusting the width of the first conductive layer of the second doping type, the performance of the trench MOSFET device can be controlled, the current loss can be reduced, and the heat generation of the device can be reduced. In this embodiment, the pattern of the second trench 204 is first defined by photolithography, and then the second trench 204 with a high aspect ratio is obtained by silicon etching. The silicon etching process here may be a typical deep silicon etching process (Bosch process), which includes a silicon etching process step and a sidewall passivation process step, and the second trench 204 with a relatively flat sidewall is obtained by continuously repeating the two process steps. Next, the etched second trench 204 is wet cleaned, generally using a conventional cleaning solution, such as a mixed cleaning solution of HCl / H2O2 / H2O or NH4OH / H2O2 / H2O.

[0050] Step S06: depositing a gate dielectric layer 213 on the inner wall and bottom of the second trench 204;

[0051] Step S07: forming a gate electrode layer 223 filling the second trench 204 on the gate dielectric layer 213;

[0052] See also Figure 5 , Figure 5 The schematic diagram of the combination of S05 and S06 is shown. A gate dielectric layer 113 is deposited on the inner wall and bottom of the trench 103 using thermal oxidation technology. Thermal oxidation technology is generally a process in which silicon reacts with a gas containing an oxidizing substance, such as water vapor and oxygen, at high temperature to produce a dense silicon dioxide (SiO2) film on the surface of the silicon wafer, which is an important process in silicon planar technology. Further, polysilicon is filled in the trench 103 covered with the gate dielectric layer 113 by low-pressure chemical vapor deposition to form a gate electrode layer 123, and then back etching or chemical mechanical planarization is used to make the gate electrode layer 123 flush with the trench 103.

[0053] Step S08, forming a body region 205 in the second epitaxial layer 222 of the first doping type;

[0054] Step S09, forming a third trench (not shown) penetrating the body region 205 in the second epitaxial layer 222 of the first doping type;

[0055] Step S10, forming a second conductive layer 203 in the third trench.

[0056] Figure 6 It is a schematic cross-sectional diagram of the stages from step S08 to step S10. The formation of the body region 205 includes ion implantation and annealing processes. In this embodiment, a third trench (not shown) is formed in the second epitaxial layer 222 of the first doping type. The third trench penetrates the body region 205 and extends vertically to the upper surface of the first conductive layer 203 of the second doping type; a second conductive layer 206 is formed in the third trench; the second conductive layer 206 connects the body region 205 and the first conductive layer 203 of the second doping type to achieve the equipotential between the first conductive layer 203 of the second doping type and the body region 205. The formation of the third trench includes defining the third trench by a photolithography process, and then using a silicon etching process to obtain a third trench with a high aspect ratio. Since the process is known in the art, the details are not repeated here. The formation of the second conductive layer 206 includes one or more combinations of flowing chemical vapor deposition (FCVD), spin coating, high density plasma (HDP) chemical vapor deposition (CVD), and ion implantation processes. In one embodiment, the second conductive layer 206 is formed by an ion implantation process. After the body region 205 is formed, a mask is formed on the body region 205. The mask defines the position of the third trench. The third trench penetrating the body region 205 and the second conductive layer 206 located in the third trench are formed in the body region 205 by the ion implantation process. In another embodiment, the body region 205 is doped, and a source region (not shown) is further formed in the body region 205; the third trench also penetrates the source region, and the second conductive layer 206 connects the source region, the body region 205 and the first conductive layer 203 of the second doping type, so as to achieve the equipotential between the first conductive layer 203 of the second doping type located at the bottom of the trench, the source region and the body region 205. The resistance of the second conductive layer 206 is lower than the resistance of the first conductive layer 203 of the second doping type. The materials of the first conductive layer 203 of the second doping type and the second conductive layer 206 are both semiconductor materials. The material of the second conductive layer 206 includes a metal material. In one embodiment, the second conductive layer 206 is formed by filling the third trench with a metal material.

[0057] In the trench MOSFET device prepared by the method of the present invention, the second conductive layer connects the first conductive layer of the second doping type located in the first epitaxial layer of the first doping type and the body region, so as to achieve equipotential between the first conductive layer of the second doping type and the body region, and the drift region located at the bottom of the trench is depleted laterally and vertically, so as to improve the withstand voltage BV of the trench MOSFET device, reduce Qg and control the hot carrier injection introduced in the process, reduce Crss / Ciss, and thus improve the reliability of the trench MOSFET device; at the same time, by adjusting the height and width of the first conductive layer, it is compatible with the existing MOSFET device process technology, and the stability of the device is improved, which has significant significance.

[0058] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for preparing a trench MOSFET device, characterized in that: include: Step S01, providing a substrate, and forming a first epitaxial layer of a first doping type on a surface of the substrate; Step S02, forming a first trench in the first epitaxial layer of the first doping type; wherein the first trench longitudinally extends from the top of the first epitaxial layer of the first doping type to the bottom of the substrate and terminates in the first epitaxial layer of the first doping type, and the first trench has a first trench width horizontal to the substrate surface direction and a first trench height perpendicular to the substrate surface direction; Step S03, forming a first conductive layer of a second doping type in the first trench; the height of the first conductive layer is less than the height of the first trench, and by adjusting the height and width of the first conductive layer, current loss is reduced and device heating is reduced; wherein the first conductive layer of the second doping type has a first conductive layer height perpendicular to the substrate surface direction and a first conductive layer width horizontal to the substrate surface direction; Step S04, forming a second epitaxial layer of the first doping type on a surface of the first epitaxial layer of the first doping type and a surface of the first conductive layer of the second doping type; the second epitaxial layer of the first doping type also fills the first trench; Step S05, forming a second trench in the second epitaxial layer of the first doping type above the first conductive layer of the second doping type; Step S06: depositing a gate dielectric layer on the inner wall and bottom of the second trench; Step S07: forming a gate electrode layer filling the second trench on the gate dielectric layer; Step S08, forming a body region in the second epitaxial layer of the first doping type; doping the body region, and forming a source region in the body region; Step S09, forming a third trench penetrating the body region and the source region in the second epitaxial layer of the first doping type; Step S10, forming a second conductive layer in the third trench, wherein the second conductive layer is connected to the source region, the body region and the first conductive layer of the second doping type.

2. The method for preparing a trench MOSFET device according to claim 1, wherein: The formation of the second doping type first conductive layer includes one or more combinations of flowing chemical vapor deposition (FCVD), spin coating, high density plasma (HDP) chemical vapor deposition (CVD), and ion implantation processes.

3. The method for preparing a trench MOSFET device according to claim 1, wherein: The formation of the second conductive layer includes one or more combinations of flowing chemical vapor deposition (FCVD), spin coating, high density plasma (HDP) chemical vapor deposition (CVD), and ion implantation processes.

4. A trench MOSFET device, implemented by the method for preparing a trench MOSFET device according to any one of claims 1 to 3, characterized in that: include: substrate; a first epitaxial layer of a first doping type located on the substrate; a first trench located in the first epitaxial layer of the first doping type, the first trench longitudinally extending from the top of the first epitaxial layer of the first doping type to the bottom of the substrate and terminating in the first epitaxial layer of the first doping type, and the first trench having a first trench width horizontal to a surface direction of the substrate and a first trench height perpendicular to the surface direction of the substrate; a first conductive layer of a second doping type, the first conductive layer of the second doping type being located at the bottom of the first trench, the second doping type being opposite to the first doping type; the first conductive layer of the second doping type having a first conductive layer height perpendicular to the substrate surface direction and a first conductive layer width horizontal to the substrate surface direction, the first conductive layer height being less than the first trench height; A second epitaxial layer of a first doping type, wherein the second epitaxial layer of the first doping type is located on a surface of the first epitaxial layer of the first doping type and a surface of the first conductive layer of the second doping type, and the second epitaxial layer of the first doping type further fills the first trench; a second trench, wherein the second trench is located in the second epitaxial layer of the first doping type above the first conductive layer of the second doping type, and the bottom surface of the second trench is higher than the surface of the first conductive layer of the second doping type, and the second trench has a second trench width parallel to the substrate surface direction; a gate dielectric layer located on the inner wall and bottom of the second trench, and a gate electrode layer located on the gate dielectric layer, wherein the gate electrode layer fills the second trench; a body region, wherein the body region is located in the second epitaxial layer of the first doping type and is adjacent to the second trench, and a portion of the body region is located above the first conductive layer of the second doping type; a source region, located in the body region; a third trench, the third trench being located in the second epitaxial layer of the first doping type, the third trench penetrating the body region and the source region and exposing a portion of the surface of the first conductive layer of the second doping type; A second conductive layer fills the third trench, and the second conductive layer connects the first conductive layer of the second doping type, the body region, and the source region.

5. The trench MOSFET device according to claim 4, characterized in that: The width of the first conductive layer is greater than the width of the second trench.

6. The trench MOSFET device according to claim 4, characterized in that: The bottom surface of the second trench is 0.1 μm to 0.5 μm higher than the surface of the first conductive layer of the second doping type.

7. The trench MOSFET device according to claim 4, characterized in that: The first conductive layer has a height of 0.2 μm to 0.8 μm.

8. The trench MOSFET device according to claim 4, characterized in that: The resistance of the second conductive layer is lower than the resistance of the second doping type first conductive layer.

9. The trench MOSFET device according to claim 4, characterized in that: The resistivity of the first epitaxial layer of the first doping type is lower than the resistivity of the first conductive layer of the second doping type; the resistivity of the second epitaxial layer of the first doping type is lower than the resistivity of the first conductive layer of the second doping type.

10. The trench MOSFET device according to claim 4, characterized in that: The material of the first conductive layer of the second doping type and / or the material of the second conductive layer is a semiconductor material.

11. The trench MOSFET device according to claim 4, characterized in that: The material of the second conductive layer includes metal material.

12. The trench MOSFET device according to claim 4, characterized in that: The material of the first conductive layer of the second doping type is the same as the material of the second conductive layer.

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