Semiconductor structure and method for manufacturing the same

Abstract

The present invention provides a semiconductor structure and a preparation method thereof. After removing the exposed Ti metal seed layer by a first wet etching, a first pretreatment is performed on a dielectric layer to form a first groove in the dielectric layer to expose the residual Ti metal seed layer in the dielectric layer, and the residual Ti metal seed layer is removed by a second wet etching, and the dielectric layer is pretreated by a second pretreatment to form a second groove with a depth greater than that of the residual Ti metal seed layer, so that the residual Ti metal seed layer in the dielectric layer can be effectively removed, so that a depth difference exists between the bottom of the second groove and the residual Ti metal seed layer, thereby avoiding a short circuit caused by the residual Ti metal seed layer and improving device reliability.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor manufacturing and relates to a semiconductor structure and a preparation method thereof. Background Art

[0002] As integrated circuits become more powerful, with higher performance and integration, and as new integrated circuits emerge, packaging technology plays an increasingly important role in integrated circuit products, accounting for an increasing proportion of the value of the entire electronic system. At the same time, as the feature size of integrated circuits reaches the nanometer level, transistors develop towards higher density and higher clock frequency, and packaging also develops towards higher density.

[0003] Wafer-level packaging (WLP) uses wafers as processing objects, packages and tests the entire wafer, and then cuts the wafer into individual chips. Due to its advantages of miniaturization, low cost, high integration, better performance and higher energy efficiency, WLP has become an important packaging method for electronic devices such as high-demand mobile / wireless networks, and is one of the most promising packaging technologies.

[0004] RDL can re-layout the soldering area positions of the chip's pads so that the new soldering areas meet the minimum depth difference requirements for the solder balls and are arranged in an array. For high I / O chip packaging structures, multiple layers of RDL metal lines are required. Under limited shape and package size, the smaller the line width and line depth difference of the RDL metal lines, the more power supply tracks can be obtained. However, the manufacture of RDL requires more processes and complex procedures. When forming the Ti metal seed layer, a small amount of Ti will enter the middle layer of the dielectric layer. When the Ti metal seed layer is subsequently removed by wet etching, the Ti metal seed layer remaining in the dielectric layer cannot be cleaned up, so the remaining Ti metal seed layer has the risk of causing a short circuit, which will reduce the reliability of the device.

[0005] Therefore, it is necessary to provide a semiconductor structure and a method for preparing the same. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor structure and a preparation method thereof, which is used to solve the problem in the prior art that the Ti metal seed layer remaining in the dielectric layer cannot be cleaned up, so that the residual Ti metal seed layer causes a short circuit and reduces reliability.

[0007] To achieve the above object and other related objects, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0008] Providing a supporting substrate, and forming a separation layer on the supporting substrate;

[0009] forming a dielectric layer on the separation layer;

[0010] forming a Ti metal seed layer on the dielectric layer;

[0011] forming a Cu metal seed layer on the Ti metal seed layer;

[0012] forming a photoresist layer on the Cu metal seed layer, and patterning the photoresist layer;

[0013] forming a metal layer in contact with the Cu metal seed layer;

[0014] removing the photoresist layer to expose the Cu metal seed layer;

[0015] removing the Cu metal seed layer to expose the Ti metal seed layer;

[0016] Using a first wet etching method to remove the Ti metal seed layer to expose the dielectric layer;

[0017] Performing a first pretreatment on the dielectric layer to form a first groove in the dielectric layer to expose a residual Ti metal seed layer in the dielectric layer;

[0018] Using a second wet etching method to remove the residual Ti metal seed layer;

[0019] The dielectric layer is subjected to a second pretreatment to form a second groove having a depth greater than that of the residual Ti metal seed layer.

[0020] Optionally, the first pretreatment includes plasma treatment of the dielectric layer using one of O2, CF4, and Ar; the second pretreatment includes plasma treatment of the dielectric layer using one of O2, CF4, and Ar.

[0021] Optionally, the depth of the first groove ranges from 0.2 μm to 0.4 μm; and the depth of the second groove ranges from 0.3 μm to 1.2 μm.

[0022] Optionally, the temperature range of the first wet etching to remove the exposed Ti metal seed layer includes 30℃~50℃, and the processing time includes 120s~150s; the temperature range of the second wet etching to remove the residual Ti metal seed layer includes 30℃~50℃, and the processing time includes 40s~80s.

[0023] Optionally, the material of the dielectric layer includes one of PI, epoxy resin, silica gel, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass.

[0024] Optionally, the method for forming the Ti metal seed layer includes one of sputtering and chemical plating; the method for forming the Cu metal seed layer includes one of sputtering, chemical plating and electroplating; the method for forming the metal layer includes one of sputtering, chemical plating and electroplating.

[0025] The present invention also provides a semiconductor structure, comprising:

[0026] Support substrate;

[0027] a separation layer, the separation layer being located on the supporting substrate;

[0028] A dielectric layer, the dielectric layer is located on the separation layer, and the dielectric layer has a first groove and a second groove that are connected to each other;

[0029] A Ti metal seed layer, wherein the Ti metal seed layer is located on the dielectric layer, wherein the dielectric layer in contact with the Ti metal seed layer has a residual Ti metal seed layer, and the depth of the second groove is greater than the depth of the residual Ti metal seed layer;

[0030] A Cu metal seed layer, wherein the Cu metal seed layer is located on the Ti metal seed layer;

[0031] A metal layer is located on the Cu metal seed layer.

[0032] Optionally, the depth of the first groove ranges from 0.2 μm to 0.4 μm; and the depth of the second groove ranges from 0.3 μm to 1.2 μm.

[0033] Optionally, the depth of the first groove is equal to the depth of the residual Ti metal seed layer or the depth of the first groove is less than the depth of the residual Ti metal seed layer.

[0034] Optionally, the dielectric layer includes one of a PI layer, an epoxy resin layer, a silicone layer, a PBO layer, a BCB layer, a silicon oxide layer, a phosphosilicate glass layer and a fluorine-containing glass layer.

[0035] As described above, the semiconductor structure and preparation method thereof of the present invention, after the exposed Ti metal seed layer is removed by the first wet etching, a first groove is formed in the dielectric layer by performing a first pretreatment on the dielectric layer to expose the residual Ti metal seed layer located in the dielectric layer, and the residual Ti metal seed layer is removed by the second wet etching, and the dielectric layer is subjected to a second pretreatment to form a second groove having a depth greater than that of the residual Ti metal seed layer, thereby effectively removing the residual Ti metal seed layer located in the dielectric layer, so that there is a depth difference between the bottom of the second groove and the residual Ti metal seed layer, thereby avoiding a short circuit caused by the residual Ti metal seed layer and improving device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram of the process flow of preparing the semiconductor structure in the embodiment.

[0037] Figure 2 It is a schematic diagram of the structure after forming a separation layer in the embodiment.

[0038] Figure 3 It is a schematic diagram of the structure after the dielectric layer is formed in the embodiment.

[0039] Figure 4 It is a schematic diagram of the structure after forming a Ti / Cu metal seed layer in the embodiment.

[0040] Figure 5 It is a schematic diagram of the structure after forming a patterned photoresist layer in the embodiment.

[0041] Figure 6 It is a schematic diagram of the structure after the metal layer is formed in the embodiment.

[0042] Figure 7 It is a schematic diagram of the structure after removing the photoresist layer in the embodiment.

[0043] Figure 8 It is a schematic diagram of the structure after removing the Cu metal seed layer in the embodiment.

[0044] Fig. 9 It is a schematic diagram of the structure after removing the Ti metal seed layer in the embodiment.

[0045] Figure 10 to Figure 13 Display as Fig. 9 Schematic diagram of the enlarged structure of the A area during the process of forming the first groove and the second groove.

[0046] Fig.14 Shown is a schematic diagram of the structure after cleaning and drying in the embodiment.

[0047] Component number description

[0048] 100 Support substrate

[0049] 200 Separation Layer

[0050] 300 Dielectric Layer

[0051] 310 Residual Ti metal seed layer

[0052] 301 First Groove

[0053] 302 Second groove

[0054] 400 Ti metal seed layer

[0055] 500 Cu metal seed layer

[0056] 600 Photoresist layer

[0057] 700 Metal Layer

[0058] T1, T2, ΔT depth

[0059] A Region DETAILED DESCRIPTION

[0060] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] See also Figure 1 to Figure 14 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0062] See also Figure 1 The present embodiment provides a method for preparing a semiconductor structure, wherein after the exposed Ti metal seed layer is removed by a first wet etching, a first pretreatment is performed on the dielectric layer to form a first groove in the dielectric layer to expose the residual Ti metal seed layer in the dielectric layer, and the residual Ti metal seed layer is removed by a second wet etching, and the dielectric layer is subjected to a second pretreatment to form a second groove having a depth greater than that of the residual Ti metal seed layer, thereby effectively removing the residual Ti metal seed layer in the dielectric layer, so that a depth difference exists between the bottom of the second groove and the residual Ti metal seed layer, thereby avoiding a short circuit caused by the residual Ti metal seed layer and improving device reliability.

[0063] See also Figure 2 to Figure 14 , showing a structural schematic diagram of each step of preparing the semiconductor structure.

[0064] First, see Figure 2 , providing a supporting substrate 100 , and forming a separation layer 200 on the supporting substrate 100 .

[0065] Specifically, the supporting substrate 100 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate. The separation layer 200 includes one of a tape and a polymer, so that the subsequent process of removing the supporting substrate 100 is simplified through the separation layer 200, reducing damage to the components. Among them, the separation layer 200 can be cured and formed by a UV curing or a thermal curing process. In this embodiment, a polymer is used as the separation layer 200, and the method for forming the polymer layer includes using a spin coating process to coat the polymer on the surface of the supporting substrate 100, and then using a UV curing or a thermal curing process to cure it. In the subsequent peeling process, heating can also be used, which is not described here.

[0066] Next, see Figure 3 , a dielectric layer 300 is formed on the separation layer 200 .

[0067] Specifically, the dielectric layer 300 may be formed on the separation layer 200 by chemical vapor deposition or physical vapor deposition. The material of the dielectric layer 200 includes one of PI, epoxy resin, silica gel, PBO, BCB, silicon oxide, phosphorus silicon glass and fluorine-containing glass. In this embodiment, the material of the dielectric layer 200 is PI, but it is not limited thereto.

[0068] Next, see Figure 4 , a Ti metal seed layer 400 and a Cu metal seed layer 500 are sequentially formed on the dielectric layer.

[0069] Specifically, the method for forming the Ti metal seed layer 400 includes one of sputtering and chemical plating; the method for forming the Cu metal seed layer 500 includes one of sputtering, chemical plating and electroplating. In the present embodiment, the Ti metal seed layer 400 and the Cu metal seed layer 500 are both formed by sputtering, but are not limited thereto. When forming the Ti metal seed layer 400, since the dielectric layer 300 inevitably has a certain degree of roughness, part of the Ti metal seed layer 400 will penetrate into the preset depth of the surface of the dielectric layer 300 to form a residual Ti metal seed layer 310, such as Fig.10 The residual Ti metal seed layer 310 has a depth ranging from 0.1 μm to 0.4 μm, such as 0.2 μm, 0.3 μm, 0.4 μm, etc.

[0070] Next, see Figure 5 , forming a photoresist layer 600 on the Cu metal seed layer 500 , and patterning the photoresist layer 600 .

[0071] Specifically, the material of the photoresist layer includes one of a positive photoresist, a negative photoresist or a hard mask, and the specific material is not limited here. The patterned photoresist layer 600 can be obtained by coating, exposure, and development, and the subsequent process can be performed by using the photoresist layer 600 as a mask. The thickness of the photoresist layer 600 is preferably 50 μm to 200 μm, such as 100 μm, 150 μm, etc., and can be selected according to the thickness of the metal layer 700 to be formed subsequently. The morphology of the photoresist layer 600 is not limited here.

[0072] Next, see Figure 6 , forming a metal layer 700 in contact with the Cu metal seed layer 500 .

[0073] Specifically, the material of the metal layer 700 includes one of copper, aluminum, silver, chromium, titanium, tantalum, molybdenum and neodymium, and the method of forming the metal layer 700 may include one of sputtering, chemical plating and electroplating. In this embodiment, in order to reduce the complexity of the process and improve the bonding performance, the metal layer 700 is made of copper metal and is prepared by electroplating, but it is not limited thereto.

[0074] Next, see Figure 7 , remove the photoresist layer 600 to expose the Cu metal seed layer 500 .

[0075] Next, see Figure 8 , remove the Cu metal seed layer 500 to expose the Ti metal seed layer 400. The method of removing the Cu metal seed layer 500 includes wet etching, and the specific process is not limited here.

[0076] Next, see Fig. 9 , a first wet etching is performed to remove the Ti metal seed layer 400 to expose the dielectric layer 300 .

[0077] Specifically, the temperature range of the first wet etching to remove the exposed Ti metal seed layer 400 includes 30° C. to 50° C., and the processing time includes 120s to 150s; if the temperature is 35° C., 38° C., 40° C., etc., the processing time includes 125s, 136s, 138s, 140s, 145s, 150s, etc. In this embodiment, the temperature of the first wet etching is 38° C. and the time is 138s to effectively remove the Ti metal seed layer 400.

[0078] See also Fig.10 Display as Fig. 9 The enlarged structural diagram of the A area in the middle Fig.10 It can be seen that after removing the Ti metal seed layer 400, the surface of the dielectric layer 300 has the residual Ti metal seed layer 310. Fig.10It can be seen that the presence of the residual Ti metal seed layer 310 may cause a risk of short circuit, thus reducing the reliability of the device.

[0079] Next, see Fig.11 , performing a first pretreatment on the dielectric layer 300 to form a first groove 301 in the dielectric layer 300 to expose the residual Ti metal seed layer 310 located in the dielectric layer 300 .

[0080] Specifically, the first pretreatment includes using one of O2, CF4, and Ar to perform plasma treatment on the dielectric layer 300. In this embodiment, the first pretreatment uses O2 for plasma treatment, and the plasma treatment time is 60s to form the first groove 301 with a depth T1, and the value of T1 is preferably equal to the depth of the residual Ti metal seed layer 310, so that the residual Ti metal seed layer 310 can be completely exposed through the first pretreatment, so that the residual Ti metal seed layer 310 can be completely removed by the subsequent second wet etching to avoid the risk of short circuit and improve the reliability of the device, but it is not limited to this. The value of the depth T1 can also be less than the depth of the residual Ti metal seed layer 310, that is, after the subsequent second wet etching, a small amount of the residual Ti metal seed layer 310 can also be removed by the second pretreatment, that is, through the second groove 302 with a depth greater than the depth T2 of the residual Ti metal seed layer 310, the residual Ti metal seed layer 310 can also be completely removed to avoid the risk of short circuit and improve the reliability of the device.

[0081] See also Fig.12 , a second wet etching is performed to remove the residual Ti metal seed layer 310 .

[0082] Specifically, the temperature range of the second wet etching to remove the residual Ti metal seed layer 310 includes 30° C. to 50° C., and the processing time includes 40s to 80s, such as the temperature is 35° C., 38° C., 40° C., etc., and the processing time includes 50s, 60s, 70s, etc. In this embodiment, the temperature of the second wet etching is 38° C. and the time is 60s to effectively remove the residual Ti metal seed layer 310.

[0083] Next, see Fig.13 , performing a second pretreatment on the dielectric layer 300 to form a second groove 302 having a depth greater than that of the residual Ti metal seed layer 310 .

[0084] Specifically, the second pretreatment includes using one of O2, CF4, and Ar to perform plasma treatment on the dielectric layer 300. In this embodiment, the first pretreatment and the second pretreatment are both performed with O2 plasma treatment, and the plasma treatment time is 60s to form the first groove 301 with the depth T1 and the second groove 302 with the depth T2, and the value of T1 is preferably equal to the depth of the residual Ti metal seed layer 310, and preferably T2=2T1, so that there is a depth difference △T between the bottom of the residual Ti metal seed layer 310 and the bottom of the second groove 302, so as to facilitate subsequent process manufacturing and provide reliability, but it is not limited to this, the first pretreatment and the second pretreatment can also use different processes as needed to form the first groove 301 and the second groove 302 with different depths. Among them, when the value of the depth T1 is preferably equal to the depth of the residual Ti metal seed layer 310, the residual Ti metal seed layer 310 can be completely exposed through the first pretreatment, so that the residual Ti metal seed layer 310 can be completely removed through the second wet etching to avoid the risk of short circuit and improve the reliability of the device, but it is not limited to this. For example, the value of the depth T1 can also be less than the depth of the residual Ti metal seed layer 310, that is, after the second wet etching, the residual Ti metal seed layer 310 can also be removed through the second pretreatment, that is, the residual Ti metal seed layer 310 can be completely removed through the second groove 302 whose depth is greater than the depth T2 of the residual Ti metal seed layer 310 to avoid the risk of short circuit and improve the reliability of the device.

[0085] Furthermore, since the value of T2 is greater than the depth of the residual Ti metal seed layer 310, a depth difference ΔT may be formed between the residual Ti metal seed layer 310 and the bottom of the second groove 302, thereby further avoiding the risk of short circuit after removing the residual Ti metal seed layer 310 and improving the reliability of the device.

[0086] Finally, if Fig.14 , and may also include washing and drying steps.

[0087] Specifically, the cleaning step can be performed with cheap and pollution-free deionized water to effectively remove impurities, but the selection of the cleaning solution is not limited thereto. The drying step can be performed by physical drying, or / and by using one or a combination of nitrogen and inert gas to improve efficiency while ensuring the drying effect. The specific cleaning and drying processes are not overly limited here.

[0088] See also Fig.13 and Fig.14 , this embodiment also provides a semiconductor structure, which includes a supporting substrate 100, a separation layer 200, a dielectric layer 300, a Ti metal seed layer 400, a Cu metal seed layer 500 and a metal layer 700. The separation layer 200 is located on the supporting substrate 100; the dielectric layer 300 is located on the separation layer 200, and the dielectric layer 300 has a first groove 301 and a second groove 302 connected to each other; the Ti metal seed layer 400 is located on the dielectric layer 300, wherein the dielectric layer 300 in contact with the Ti metal seed layer 400 has a residual Ti metal seed layer 310, and the depth of the second groove 302 is greater than the depth of the residual Ti metal seed layer 310; the Cu metal seed layer 500 is located on the Ti metal seed layer 400; and the metal layer 700 is located on the Cu metal seed layer 500.

[0089] The semiconductor structure in this embodiment can be manufactured by the above-mentioned manufacturing method, but is not limited thereto.

[0090] The semiconductor structure of this embodiment can effectively remove the residual Ti metal seed layer 310 located in the dielectric layer 300 through the first groove 301 and the second groove 302, and there is a depth difference ΔT between the bottom of the second groove 302 and the residual Ti metal seed layer 310, thereby avoiding the short circuit caused by the residual Ti metal seed layer 310 and improving the reliability of the device.

[0091] As an example, the depth T1 of the first groove 301 ranges from 0.2 μm to 0.4 μm; the depth T2 of the second groove 302 ranges from 0.3 μm to 1.2 μm.

[0092] As an example, the relationship between the depth T2 of the second groove 302 and the depth T1 of the first groove 301 includes T2=2T1.

[0093] As an example, the depth T1 of the first groove 301 is equal to the depth of the residual Ti metal seed layer 310 or the depth T1 of the first groove 301 is less than the depth of the residual Ti metal seed layer 310 .

[0094] As an example, the dielectric layer 300 includes one of a PI layer, an epoxy resin layer, a silicone layer, a PBO layer, a BCB layer, a silicon oxide layer, a phosphosilicate glass layer and a fluorine-containing glass layer.

[0095] As an example, the metal layer 700 includes one of a copper layer, an aluminum layer, a silver layer, a chromium layer, a titanium layer, a tantalum layer, a molybdenum layer and a neodymium layer.

[0096] As an example, the support substrate 100 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate.

[0097] As an example, the support substrate 100 includes a wafer-level support substrate.

[0098] As an example, the separation layer 200 includes one of an adhesive tape and a polymer layer.

[0099] In summary, the semiconductor structure and preparation method thereof of the present invention, after the exposed Ti metal seed layer is removed by the first wet etching, a first groove is formed in the dielectric layer by performing a first pretreatment on the dielectric layer to expose the residual Ti metal seed layer located in the dielectric layer, and the residual Ti metal seed layer is removed by the second wet etching, and the dielectric layer is subjected to a second pretreatment to form a second groove having a depth greater than that of the residual Ti metal seed layer, thereby effectively removing the residual Ti metal seed layer located in the dielectric layer, so that there is a depth difference between the bottom of the second groove and the residual Ti metal seed layer, thereby avoiding a short circuit caused by the residual Ti metal seed layer and improving device reliability.

[0100] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The following steps are involved: Providing a supporting substrate, and forming a separation layer on the supporting substrate; forming a dielectric layer on the separation layer; forming a Ti metal seed layer on the dielectric layer; forming a Cu metal seed layer on the Ti metal seed layer; forming a photoresist layer on the Cu metal seed layer, and patterning the photoresist layer; forming a metal layer in contact with the Cu metal seed layer; removing the photoresist layer to expose the Cu metal seed layer; removing the Cu metal seed layer to expose the Ti metal seed layer; Using a first wet etching method to remove the Ti metal seed layer to expose the dielectric layer; Performing a first pretreatment on the dielectric layer to form a first groove in the dielectric layer to expose a residual Ti metal seed layer in the dielectric layer; Using a second wet etching method to remove the residual Ti metal seed layer; The dielectric layer is subjected to a second pretreatment to form a second groove having a depth greater than that of the residual Ti metal seed layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first pretreatment includes plasma treatment of the dielectric layer using one of O2, CF4, and Ar; the second pretreatment includes plasma treatment of the dielectric layer using one of O2, CF4, and Ar.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The depth of the first groove ranges from 0.2 μm to 0.4 μm; the depth of the second groove ranges from 0.3 μm to 1.2 μm.

4. The method for preparing a semiconductor structure according to claim 1, wherein: The temperature range of the first wet etching to remove the exposed Ti metal seed layer is 30°C to 50°C, and the processing time is 120s to 150s; the temperature range of the second wet etching to remove the residual Ti metal seed layer is 30°C to 50°C, and the processing time is 40s to 80s.

5. The method for preparing a semiconductor structure according to claim 1, wherein: The material of the dielectric layer includes one of PI, epoxy resin, silica gel, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass.

6. The method for preparing a semiconductor structure according to claim 1, wherein: The method for forming the Ti metal seed layer includes one of sputtering and chemical plating; the method for forming the Cu metal seed layer includes one of sputtering, chemical plating and electroplating; the method for forming the metal layer includes one of sputtering, chemical plating and electroplating.

7. A semiconductor structure, characterized in that: The semiconductor structure comprises: Support substrate; a separation layer, the separation layer being located on the supporting substrate; a dielectric layer, the dielectric layer being located on the separation layer and comprising a first groove and a second groove; A Ti metal seed layer, the Ti metal seed layer is located on the dielectric layer, wherein the dielectric layer in contact with the Ti metal seed layer has a residual Ti metal seed layer, the first groove exposes the residual Ti metal seed layer in the dielectric layer, the depth of the second groove is greater than the depth of the residual Ti metal seed layer, and the first groove and the second groove are connected; A Cu metal seed layer is located on the Ti metal seed layer. A metal layer, the metal layer is located on the Cu metal seed layer; Wherein, the supporting substrate comprises a wafer-level supporting substrate, and the separating layer comprises one of an adhesive tape and a polymer layer.

8. The semiconductor structure according to claim 7, characterized in that: The depth of the first groove ranges from 0.2 μm to 0.4 μm; the depth of the second groove ranges from 0.3 μm to 1.2 μm.

9. The semiconductor structure according to claim 7, characterized in that: The depth of the first groove is equal to the depth of the residual Ti metal seed layer or the depth of the first groove is less than the depth of the residual Ti metal seed layer.

10. The semiconductor structure according to claim 7, wherein: The dielectric layer includes one of a PI layer, an epoxy resin layer, a silica gel layer, a PBO layer, a BCB layer, a silicon oxide layer, a phosphosilicate glass layer and a fluorine-containing glass layer.

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