Semiconductor structure and method for manufacturing the same

Abstract

The present invention provides a semiconductor structure and a preparation method thereof. After planarization, a Si substrate is dry-etched so that the Si substrate and an insulating layer have a first height difference. Through wet processing, residual Cu metal near the edge of a Cu column can be effectively removed, and the Cu column and the insulating layer have a second height difference, and the first height difference is greater than the second height difference, so that connection between the Cu metal inside and outside the insulating layer can be avoided, so as to effectively avoid affecting the electrical properties of the device; further, the Si substrate can be effectively covered by a passivation layer, so as to avoid the Si substrate from forming a conductive channel in a subsequent process, so as to achieve a good insulation effect, so as to further avoid affecting the electrical properties of the device.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor manufacturing and relates to a semiconductor structure and a preparation method thereof. Background Art

[0002] As integrated circuits become more powerful, more performant and more integrated, packaging technology plays an increasingly important role in integrated circuit products, and accounts for an increasing proportion of the value of the entire electronic system. Wafer-level packaging (WLP) technology has become an important packaging method for electronic devices such as high-demand mobile / wireless networks, and is currently one of the most promising packaging technologies, due to its advantages of miniaturization, low cost, high integration, better performance and higher energy efficiency.

[0003] The redistribution layer (RDL) can re-layout the soldering area positions of the chip's solder pads and arrange the new soldering areas in an array. Therefore, RDL is widely used in the WLP process. With the development of packaging technology, high-density, small-pitch RDL metal lines are urgently needed.

[0004] In the prior art, Cu metal is widely used as a conductive material in the WLP process. However, due to the forgeability of Cu metal, Cu metal is easily left after the planarization process, and the residual Cu metal will affect the electrical performance of the prepared high-density, small-pitch devices.

[0005] Therefore, it is necessary to provide a semiconductor structure and a method for preparing the same to improve the electrical performance of the device. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor structure and a method for preparing the same, so as to solve the problem in the prior art that residual Cu metal after the planarization process reduces the electrical performance of the device.

[0007] To achieve the above object and other related objects, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0008] Providing a Si substrate;

[0009] Patterning the Si substrate to form a groove;

[0010] forming an insulating layer in the trench to cover the bottom and sidewalls of the trench;

[0011] forming a Cu column to fill the trench;

[0012] Performing planarization to expose the Si substrate, the insulating layer and the Cu pillar;

[0013] dry-etching the Si substrate so that there is a first height difference between the Si substrate and the insulating layer;

[0014] Performing wet processing to remove Cu metal residues and part of the Cu column, so that the Cu column and the insulating layer have a second height difference, and the first height difference is greater than the second height difference;

[0015] A passivation layer is formed to cover the Si substrate, the insulating layer and the Cu pillar.

[0016] Optionally, the treatment solution used in the wet treatment includes an acidic solution that chemically reacts with Cu metal, and the acidic solution includes one or a mixed solution of H2O2, H3PO4 and H2SO4.

[0017] Optionally, the first height difference ranges from 2 μm to 5 μm, and the second height difference ranges from 0.1 μm to 0.5 μm.

[0018] Optionally, the planarization includes one or a combination of mechanical polishing and chemical mechanical polishing.

[0019] Optionally, after forming the insulating layer and before forming the Cu column, the method further includes forming a metal seed layer.

[0020] The present invention also provides a semiconductor structure, comprising a Si substrate, an insulating layer, a Cu column and a passivation layer, wherein the Cu column is located in the Si substrate, the insulating layer covers the side wall and the bottom of the Cu column and is in contact with the Si substrate, the passivation layer covers the Si substrate, the insulating layer and the Cu column, and the Si substrate and the insulating layer have a first height difference, the Cu column and the insulating layer have a second height difference, and the first height difference is greater than the second height difference.

[0021] Optionally, the first height difference ranges from 2 μm to 5 μm.

[0022] Optionally, the second height difference ranges from 0.1 μm to 0.5 μm.

[0023] Optionally, a metal seed layer is further included between the insulating layer and the Cu column, and the metal seed layer and the Cu column have the same height.

[0024] Optionally, the insulating layer includes one or a combination of a SiO2 layer and a Si3N4 layer; the passivation layer includes one or a combination of a SiO2 layer and a Si3N4 layer.

[0025] As described above, the semiconductor structure and preparation method thereof of the present invention, after planarization, is dry-etched on the Si substrate so that the Si substrate and the insulating layer have a first height difference, and the residual Cu metal near the edge of the Cu column can be effectively removed by wet treatment, and the Cu column and the insulating layer have a second height difference, and the first height difference is greater than the second height difference, thereby avoiding the connection of the Cu metal inside and outside the insulating layer, so as to effectively avoid affecting the electrical properties of the device; further, the Si substrate can be effectively covered by the passivation layer, so as to avoid the Si substrate from forming a conductive channel in the subsequent process, so as to have a good insulation effect, thereby further avoiding affecting the electrical properties of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the process flow of preparing a semiconductor structure in an embodiment.

[0027] Figure 2 It is a schematic diagram of the structure after flattening in the embodiment.

[0028] Figure 3 It is a schematic diagram of the structure after dry etching in the embodiment.

[0029] Figure 4 Shown is a schematic diagram of the structure after wet processing in the embodiment.

[0030] Figure 5 It is a schematic diagram of the structure after the passivation layer is formed in the embodiment.

[0031] Component number description

[0032] 100 Si substrate

[0033] 200 Insulation

[0034] 300 Cu column

[0035] 400 Cu metal residue

[0036] 500 Passivation layer

[0037] D1 First height difference

[0038] D2 Second height difference DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0041] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. As used herein, "between..." means including the end point values.

[0042] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0043] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0044] See also Figure 1 to Figure 5 This embodiment provides a method for preparing a semiconductor structure, comprising the following steps:

[0045] Providing a Si substrate 100;

[0046] Patterning the Si substrate 100 to form a groove (not shown);

[0047] forming an insulating layer 200 in the trench to cover the bottom and sidewalls of the trench;

[0048] forming a Cu column 300 to fill the trench;

[0049] Planarization is performed to expose the Si substrate 100, the insulating layer 200 and the Cu pillar 300;

[0050] Dry-etching the Si substrate 100 so that a first height difference D1 exists between the Si substrate 100 and the insulating layer 200;

[0051] Performing wet processing to remove the Cu metal residue 400 and a portion of the Cu column 300 , so that the Cu column 300 and the insulating layer 200 have a second height difference D2 , and the first height difference D1 is greater than the second height difference D2 ;

[0052] A passivation layer 500 is formed to cover the Si substrate 100 , the insulating layer 200 and the Cu pillar 300 .

[0053] In the method for preparing the semiconductor structure of this embodiment, after the planarization, a portion of the Si substrate 100 is removed by the dry etching, so that the Si substrate 100 and the insulating layer 200 have the first height difference D1, and the Cu metal residue 400 can be removed by the wet treatment, and the Cu column 300 and the insulating layer 200 have the second height difference D2, and the first height difference D1 is greater than the second height difference D2, thereby avoiding the connection between the Cu metal inside and outside the insulating layer 200, so as to effectively avoid affecting the electrical properties of the device; further, the passivation layer 500 can effectively cover the Si substrate 100, so as to avoid the Si substrate 100 from forming a conductive channel in the subsequent process, so as to achieve a good insulation effect, thereby further avoiding affecting the electrical properties of the device.

[0054] See also Figure 1 First, a Si substrate 100 is provided, and the Si substrate 100 is patterned to form a groove (not shown).

[0055] Specifically, the method for patterning the Si substrate 100 may adopt a conventional photolithography method, such as patterning using a mask, the mask may include photoresist, but is not limited thereto. The depth, width and distribution of the grooves may be selected as required, and are not excessively limited here.

[0056] Next, an insulating layer 200 is formed in the trench to cover the bottom and sidewalls of the trench.

[0057] As an example, the insulating layer 200 includes one or a combination of a SiO2 layer and a Si3N4 layer. By covering the bottom and sidewalls of the groove, the insulating layer 200 can effectively prevent the formation of a conductive channel between the subsequently formed Cu column 300 and the Si substrate 100, thereby achieving a good insulation effect. The specific formation method, thickness, and material of the insulating layer 200 can be selected as needed, and no excessive restrictions are made here. In this embodiment, the insulating layer 200 adopts a SiO2 layer, but it is not limited to this. The insulating layer 200 can also adopt a Si3N4 layer or a stack of a SiO2 layer and a Si3N4 layer.

[0058] As an example, after forming the insulating layer 200 and before forming the Cu pillar 300 , a step of forming a metal seed layer (not shown) is further included.

[0059] Specifically, the metal seed layer can be formed on the surface of the insulating layer 200 by PVD method, and the metal seed layer can include a Ti / Cu metal seed layer or a Cu metal seed layer, but is not limited thereto, and can be selected according to needs. Among them, it is preferred that the metal seed layer adopts a Cu metal seed layer, so that when the second height difference D2 is formed later, the metal seed layer and the Cu column 300 can have the same etching rate, so that the metal seed layer and the Cu column 300 have the same height, and the metal seed layer is prevented from connecting with the Cu metal outside the insulating layer 200.

[0060] Next, the Cu pillar 300 is formed to fill the trench.

[0061] Specifically, when the metal seed layer is present in the groove, the Cu column 300 may be formed by electroplating, but is not limited thereto. For example, the Cu column 300 may also be prepared by a patterned mask and a deposition method, which is not excessively limited here.

[0062] Next, planarization is performed to expose the Si substrate 100 , the insulating layer 200 and the Cu pillar 300 .

[0063] As an example, the planarization includes one or a combination of mechanical polishing and chemical mechanical polishing.

[0064] Specifically, in this embodiment, mechanical grinding is first performed, and then fine chemical mechanical grinding is performed, so that a relatively flat surface can be obtained, but the planarization process is not limited to this. For example, only mechanical grinding or only chemical mechanical grinding can be used as needed, and no excessive restrictions are made here. However, since Cu metal has good forgeability, during the planarization process, Cu metal residue 400 will be formed near the edge of the Cu column 300, and this part of the residual Cu metal will affect the electrical performance of the high-density, small-pitch devices prepared subsequently, so it is necessary to completely remove the Cu metal residue 400, see Figure 2 .

[0065] Next, see Figure 3 , dry-etching the Si substrate 100 so that the Si substrate 100 and the insulating layer 200 have a first height difference D1.

[0066] Specifically, through the dry etching, the Si substrate 100 and the insulating layer 200 can have the first height difference D1 to effectively expose the Cu metal residue 400, so that in the subsequent process, the Cu metal residue 400 can be effectively removed to avoid the connection of Cu metal, so as to effectively avoid affecting the electrical performance of the device.

[0067] As an example, the first height difference D1 ranges from 2 μm to 5 μm.

[0068] Specifically, the larger the value of the first height difference D1 is, the more conducive it is to avoiding contact between the Cu metal residue 400 and the Cu column 300. However, if the first height difference D1 is too large, it will cause defects such as cracks in the insulating layer 200 during the subsequent grinding process, which will in turn cause the hidden danger of electrical conduction between the Cu column 300 and the Si substrate 100. Therefore, in this embodiment, the first height difference D1 is preferably 3μm, but is not limited to this, and 2μm, 4μm, etc. may also be used.

[0069] Next, see Figure 4 , wet treatment is performed to remove the Cu metal residue 400 and part of the Cu column 300, 1 and to make the Cu column 300 and the insulating layer 200 have a second height difference D2, and the first height difference D1 is greater than the second height difference D2.

[0070] As an example, the processing solution used in the wet processing includes an acidic solution that chemically reacts with Cu metal, and the acidic solution includes one or a mixed solution of H2O2, H3PO4 and H2SO4.

[0071] Specifically, through the wet treatment of the acidic solution, the Cu metal residue 400 located at the edge of the Cu column 300 can be effectively removed, and further, the acidic solution can also remove part of the Cu column 300, so that the Cu column 300 and the insulating layer 200 have the second height difference D2, and the first height difference D1 is greater than the second height difference D2, thereby completely avoiding the contact between the Cu metal residue 400 and the Cu column 300, so as to improve the electrical performance of the subsequently prepared device.

[0072] As an example, the second height difference D2 ranges from 0.1 μm to 0.5 μm.

[0073] Specifically, the larger the value of the second height difference D2 is, the more conducive it is to avoiding contact between the Cu metal residue 400 and the Cu column 300. However, if the second height difference D2 is too large, it will cause defects such as cracks in the insulating layer 200 during the subsequent grinding process, which will in turn cause the hidden danger of electrical conduction between the Cu column 300 and the Si substrate 100. Therefore, in this embodiment, the second height difference D2 is preferably 0.3μm, but is not limited to this, and may also be 0.2μm, 0.4μm, etc.

[0074] Next, see Figure 5 , a passivation layer 500 is formed to cover the Si substrate 100 , the insulating layer 200 and the Cu pillar 300 .

[0075] As an example, the passivation layer 500 includes one or a combination of a SiO 2 layer and a Si 3 N 4 layer.

[0076] Specifically, the passivation layer 500 can effectively cover the Si substrate 100, avoiding the formation of a conductive channel between the metal and the Si substrate 100 in the subsequent process, thereby achieving a good insulation effect. The specific formation method, thickness, and material of the passivation layer 500 can be selected as needed, and no excessive restrictions are made here. In this embodiment, the passivation layer 500 adopts a SiO2 layer, but it is not limited to this. The passivation layer 500 can also adopt a Si3N4 layer or a stack of a SiO2 layer and a Si3N4 layer.

[0077] See also Figure 5 This embodiment also provides a semiconductor structure. The semiconductor structure of this embodiment can be prepared by the above method, but is not limited thereto.

[0078] Specifically, the semiconductor structure includes a Si substrate 100, an insulating layer 200, a Cu column 300 and a passivation layer 500, wherein the Cu column 300 is located in the Si substrate 100, the insulating layer 200 covers the side wall and the bottom of the Cu column 300 and is in contact with the Si substrate 100, the passivation layer 500 covers the Si substrate 100, the insulating layer 200 and the Cu column 300, and the Si substrate 100 and the insulating layer 200 have a first height difference D1, the Cu column 300 and the insulating layer 200 have a second height difference D2, and the first height difference D1 is greater than the second height difference D2.

[0079] The semiconductor structure of this embodiment, since the Si substrate 100 and the insulating layer 200 have the first height difference D1, the Cu column 300 and the insulating layer 200 have the second height difference D2, and the first height difference D1 is greater than the second height difference D2, can effectively avoid affecting the electrical properties of the device, avoid the connection of the Cu metal inside and outside the insulating layer 200, so as to effectively avoid affecting the electrical properties of the device, and further, the passivation layer 500 can effectively cover the Si substrate 100, so as to further avoid the Si substrate 100 from forming a conductive channel in the subsequent process, so as to have a good insulation effect, so as to further avoid affecting the electrical properties of the device.

[0080] As an example, the first height difference D1 ranges from 2 μm to 5 μm.

[0081] Specifically, the larger the value of the first height difference D1 is, the more conducive it is to avoiding contact between Cu metal residues and the Cu column 300. However, if the first height difference D1 is too large, defects such as cracks may be generated in the insulating layer 200 during the subsequent grinding process, which may in turn cause the hidden danger of electrical conduction between the Cu column 300 and the Si substrate 100. Therefore, in this embodiment, the first height difference D1 is preferably 3μm, but is not limited to this, and 2μm, 4μm, etc. may also be used.

[0082] As an example, the second height difference D2 ranges from 0.1 μm to 0.5 μm.

[0083] Specifically, the larger the value of the second height difference D2 is, the more conducive it is to avoiding the contact between the Cu metal residue and the Cu column 300. However, if the second height difference D2 is too large, it will cause defects such as cracks in the insulating layer 200 during the subsequent grinding process, which will in turn cause the hidden danger of electrical conduction between the Cu column 300 and the Si substrate 100. Therefore, in this embodiment, the second height difference D2 is preferably 0.3μm, but is not limited to this, and may also be 0.2μm, 0.4μm, etc.

[0084] As an example, a metal seed layer (not shown) is further included between the insulating layer 200 and the Cu pillar 300 , and the metal seed layer and the Cu pillar 300 have the same height.

[0085] Specifically, the metal seed layer may include a Ti / Cu metal seed layer or a Cu metal seed layer, but is not limited thereto and may be selected as required. Preferably, the metal seed layer is a Cu metal seed layer and the metal seed layer and the Cu column 300 have the same height to avoid the metal seed layer from being connected to the Cu metal outside the insulating layer 200.

[0086] As an example, the insulating layer 200 includes one or a combination of a SiO 2 layer and a Si 3 N 4 layer.

[0087] Specifically, the insulating layer 200 can effectively prevent the formation of a conductive channel between the Cu column 300 and the Si substrate 100, thereby achieving a good insulating effect. The specific formation method, thickness, and material of the insulating layer 200 can be selected as needed, and no excessive restrictions are made here. In this embodiment, the insulating layer 200 is a SiO2 layer, but it is not limited to this. The insulating layer 200 can also be a Si3N4 layer or a stack of a SiO2 layer and a Si3N4 layer.

[0088] As an example, the passivation layer 500 includes one or a combination of a SiO 2 layer and a Si 3 N 4 layer.

[0089] Specifically, the passivation layer 500 can effectively cover the Si substrate 100 to prevent the Si substrate 100 from forming a conductive channel in the subsequent process, thereby achieving a good insulation effect. The specific formation method, thickness, and material of the passivation layer 500 can be selected as needed, and no excessive restrictions are made here. In this embodiment, the passivation layer 500 adopts a SiO2 layer, but is not limited to this. The passivation layer 500 can also adopt a Si3N4 layer or a stack of a SiO2 layer and a Si3N4 layer.

[0090] In summary, the semiconductor structure and preparation method thereof of the present invention, after planarization, is dry-etched on the Si substrate so that the Si substrate and the insulating layer have a first height difference, and the residual Cu metal near the edge of the Cu column can be effectively removed by wet treatment, and the Cu column and the insulating layer have a second height difference, and the first height difference is greater than the second height difference, thereby avoiding the connection between the Cu metal inside and outside the insulating layer, so as to effectively avoid affecting the electrical properties of the device; further, the Si substrate can be effectively covered by the passivation layer, so as to avoid the Si substrate from forming a conductive channel in the subsequent process, so as to have a good insulation effect, thereby further avoiding affecting the electrical properties of the device.

[0091] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The following steps are involved: Providing a Si substrate; Patterning the Si substrate to form a groove; forming an insulating layer in the trench to cover the bottom and sidewalls of the trench; forming a Cu column to fill the trench; Performing planarization to expose the Si substrate, the insulating layer and the Cu pillar; dry-etching the Si substrate so that there is a first height difference between the Si substrate and the insulating layer; Performing wet processing to remove Cu metal residues and part of the Cu column, so that the Cu column and the insulating layer have a second height difference, and the first height difference is greater than the second height difference, the first height difference ranges from 2 μm to 5 μm, and the second height difference ranges from 0.1 μm to 0.5 μm; A passivation layer is formed to cover the Si substrate, the insulating layer and the Cu pillar.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The treatment solution used in the wet treatment includes an acidic solution that chemically reacts with Cu metal, and the acidic solution includes one or a mixed solution of H2O2, H3PO4 and H2SO4.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The planarization includes one or a combination of mechanical polishing and chemical mechanical polishing.

4. The method for preparing a semiconductor structure according to claim 1, wherein: After forming the insulating layer and before forming the Cu column, the method further includes forming a metal seed layer.

5. A semiconductor structure, characterized in that: The semiconductor structure includes: a Si substrate, an insulating layer, a Cu column and a passivation layer, wherein the Cu column is located in the Si substrate, the insulating layer covers the side wall and the bottom of the Cu column and is in contact with the Si substrate, the passivation layer covers the Si substrate, the insulating layer and the Cu column, and the Si substrate and the insulating layer have a first height difference, the Cu column and the insulating layer have a second height difference, and the first height difference is greater than the second height difference, the first height difference ranges from 2μm to 5μm, and the second height difference ranges from 0.1μm to 0.5μm.

6. The semiconductor structure according to claim 5, characterized in that: A metal seed layer is further included between the insulating layer and the Cu column, and the metal seed layer and the Cu column have the same height.

7. The semiconductor structure according to claim 5, characterized in that: The insulating layer includes one or a combination of a SiO2 layer and a Si3N4 layer; the passivation layer includes one or a combination of a SiO2 layer and a Si3N4 layer.

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