Intelligent timing synchronization control panel and control method for subway vehicles

Abstract

This invention relates to the field of urban rail transit control technology, and discloses an intelligent timing synchronization control board and control method for metro vehicles. The intelligent timing synchronization control board for metro vehicles includes: a main control module, in which a main control chip reads information and data, and an AC contactor receives instructions to correct and control the AC power of several vehicles to be connected in parallel after phase synchronization; an auxiliary control module, in which an auxiliary control chip controls semiconductor devices to chop DC power; a clock module, including a crystal oscillator, which provides a clock signal to the main control chip; a DC power supply module, which supplies power to the main control module, the auxiliary control module, and the clock module; and a backup module, in which a backup battery continues to supply power to the main control chip and the auxiliary control chip when the DC power supply module is powered off, ensuring that the clock chip provides a clock signal to the main control chip in place of the crystal oscillator. This invention can accurately correct the power phase of metro vehicles to ensure safe parallel connection of two vehicles, with a high degree of intelligence and high control precision.

Description

Technical Field

[0001] The invention relates to an intelligent timing synchronization control panel and a control method for a subway vehicle, belonging to the technical field of urban rail subway control. Background Art

[0002] When subway vehicles are coupled for rescue, it is necessary to couple a rescue subway vehicle with another rescued subway vehicle, and the AC380V AC power inverter generated by the two coupled subway vehicles also needs to be connected in parallel.

[0003] However, the AC380V AC power of subway vehicles is generated by the DC power inverter of the subway power supply contact network (or contact rail). Because the AC power supply of subway vehicles has its own characteristics, the phases of the AC power inverted by different subway vehicles are often different. If the AC power supplies of subway vehicles with different phases are connected in parallel, it will cause serious faults in the electrical system, such as burning load equipment. Therefore, when two subway vehicles are connected in parallel, the phases of the AC380V AC power supplies of the two subway vehicles must be adjusted first to synchronize the phases before the AC380V power supplies of the two subway vehicles can be connected in parallel.

[0004] In order to ensure that the AC power supplies of two subway cars can be safely connected in parallel when two subway cars are connected, it is necessary to accurately control the phase synchronization of the AC power supply of the subway cars and accurately time the parallel connection. However, the traditional timing controller cannot quickly capture the phase difference of the AC power supply of the subway car and cannot quickly adjust the AC phase of the subway car. In addition, the traditional timing controller has insufficient timing accuracy, low intelligence, and large size, and cannot meet the current control requirements. Therefore, it is necessary to design an intelligent timing synchronization control board that can quickly capture and correct the AC phase of the subway vehicle, has a high degree of intelligence, and can accurately time the parallel connection of the subway vehicle, so as to control the parallel connection of the two subway vehicles when the AC power supply phase is synchronized. Summary of the invention

[0005] In view of the above-mentioned defects in the prior art, the present invention proposes an intelligent timing synchronization control panel and a control method for a subway vehicle.

[0006] The intelligent timing synchronization control board for subway vehicles described in the present invention comprises a main control module, an auxiliary control module, a clock module, a DC power supply module and a standby module, wherein:

[0007] The main control module includes a main control chip and an AC contactor KM. The main control chip reads the data of the clock module, collects the voltage information of several vehicles, and communicates with the inverters of several vehicles respectively. The AC contactor KM corrects and controls the AC power of several vehicles to be connected in parallel after phase synchronization.

[0008] An auxiliary control module, including an auxiliary control chip, a semiconductor device, and a heating and cooling device. The auxiliary control chip outputs a PWM signal to control the semiconductor device to chop the direct current, thereby controlling the working efficiency of the heating and cooling device.

[0009] The clock module includes a crystal oscillator, which provides a clock signal to the main control chip;

[0010] A DC power supply module, which supplies power to the main control module, the auxiliary control module and the clock module;

[0011] The backup module includes a clock chip and a backup battery. When the DC power module is powered off, the backup battery can continue to supply power to the main control chip and the auxiliary control chip to ensure that the clock chip replaces the crystal oscillator to provide the clock signal to the main control chip.

[0012] Preferably, the heating and cooling devices are resistance wires and tiny fans, respectively, to achieve heating and heat dissipation of the intelligent timing and synchronization control panel of the subway vehicle.

[0013] Preferably, the main control chip is also connected to an onboard relay assembly, and the onboard relay assembly receives drive instructions from the main control chip to control the opening and closing of circuits in the intelligent synchronous control board of the subway vehicle.

[0014] Preferably, the semiconductor device comprises an IGBT and a MOS tube, which chop the direct current flowing to the resistance wire and the micro fan respectively.

[0015] The control method of the subway vehicle intelligent timing synchronization control panel of the present invention comprises the following steps:

[0016] Step S1: Timing setting: write the conversion time of the voltage transformers at different phases of several vehicles into the constant array in the main control chip program, and obtain the corresponding value by querying the array when using;

[0017] Step S2: Perform calculation: The main control chip calculates the time intervals between the three-phase AC phases of several vehicles and the time interval required for delay of one of the vehicles;

[0018] Step S3: Temperature control: using an anti-integral saturation PID control algorithm to control the temperature of the intelligent timing synchronization control board of the subway vehicle to enable it to operate normally;

[0019] Step S4: Implement parallel access and coupling: The main control chip adjusts the AC power phase of several vehicles to synchronize the inverter output phases of several vehicles, and then drives the AC contactor KM to operate, so that the AC power supplies between several vehicles are connected in parallel, further realizing the coupling of several vehicles.

[0020] Preferably, the calculation formula for the time interval between the three-phase AC phases of several vehicles in step S2 is as follows:

[0021] Δt 0 =K AS ×(t AUS +t AVS+ t AWS ) / 3+K AAD ×(t AUAD +t AVAD +t AWAD ) / 3+K ACT ×t ACT -[K AS ×(t BUS +t BVS +t BWS ) / 3+K BAD ×(t BUAD +t BVAD +t BWAD ) / 3+K BCT ×t BCT +K CTR ×t CTR ];

[0022] The above formula is calculated based on the three-phase AC phase lag of car A compared to car B, where: K AS is the correction coefficient of the average time required for the synchronous contactor of car A to operate; t AUS The time required for the U-phase synchronous contactor of car A to operate; t AVS The time required for the V-phase synchronous contactor of car A to operate; t AWS K is the time required for the synchronous contactor of phase W of car A to operate; AAD It is the correction coefficient of the delay interval of the AD conversion of the analog voltage signal output by the voltage transformer of vehicle A by the main control chip; t AUAD The AD conversion delay interval of the analog voltage signal output by the main control chip to the U-phase voltage transformer of car A; t AVAD The AD conversion delay interval of the analog voltage signal output by the main control chip to the V-phase voltage transformer of vehicle A; t AWAD K is the AD conversion delay interval of the analog voltage signal output by the main control chip to the W-phase voltage transformer of car A; ACT The delay time correction coefficient when the main control chip communicates with the inverter of vehicle A; t ACT K is the delay time when the main control chip communicates with the inverter of vehicle A; BS The average time correction coefficient required for the synchronous contactor of car B to operate; t BUS The time correction coefficient for the U-phase synchronous contactor of car B to operate; t BVS The time correction coefficient for the V-phase synchronous contactor of car B to operate; t BWSK is the time correction coefficient required for the W-phase synchronous contactor of car B to operate; BAD It is the delay interval correction coefficient of the AD conversion of the analog voltage signal output by the U-phase voltage transformer of car B by the main control chip; t BUAD The AD conversion delay interval of the analog voltage signal output by the main control chip to the U-phase voltage transformer of car B; t BVAD The AD conversion delay interval of the analog voltage signal output by the main control chip to the V-phase voltage transformer of car B; t BWAD K is the AD conversion delay interval of the analog voltage signal output by the main control chip to the W-phase voltage transformer of the B car; BCT The delay time correction coefficient when the main control chip communicates with the inverter of vehicle B; t BCT K is the delay time when the main control chip communicates with the inverter of vehicle B; CTR The delay time interval correction coefficient when the main control chip drives the AC contactor KM; t CTR It is the delay time interval when the main control chip drives the AC contactor KM.

[0023] Preferably, the calculation formula for the delay time interval required for one of the vehicles in step S2 is as follows:

[0024]

[0025] The above formula is calculated based on car B, where: △t 0 K is the time interval between the phase difference of the three-phase AC power of car A and car B, t is the time correction coefficient constant.

[0026] Preferably, the calculation formula of the PID control algorithm in step S3 is as follows:

[0027]

[0028] Where: kp is the proportional coefficient, T is the integral time constant, and TD is the differential time constant.

[0029] Preferably, the PID control algorithm includes the following correction steps:

[0030] (1) Proportional link: proportional response temperature control system temperature deviation signal;

[0031] (2) Integral link: eliminate temperature static difference and improve the system's error-free degree;

[0032] (3) Differential link: reflects the changing trend of the temperature deviation signal and reduces the temperature adjustment time.

[0033] The subway vehicle intelligent timing synchronization control panel and control method described in the present invention have the following beneficial effects:

[0034] (1) Introducing FPGA chips and ARM chips to achieve dual-core control and high timing control accuracy;

[0035] (2) Introducing resistance wire and tiny fans to realize heating control of the intelligent timing and synchronization control board of subway vehicles, so that the temperature range of the intelligent timing and synchronization control board of subway vehicles is relatively constant, which can avoid the timing inaccuracy caused by large temperature drift of the chip on the intelligent timing and synchronization control board of subway vehicles;

[0036] (3) The optimized phase timing difference algorithm is introduced into the control method, which can accurately realize the timing control of the parallel connection of the AC power of two subway cars. The control accuracy is very high, ensuring the phase synchronization of the two cars and avoiding the occurrence of electrical failures. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the connection structure of the intelligent timing and synchronization control panel of the subway vehicle.

[0038] Figure 2 It is a flow chart of a control method of an intelligent timing synchronization control panel for a subway vehicle. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] Embodiment 1:

[0041] like Figure 1 As shown, the subway vehicle intelligent timing synchronization control board of the present invention includes a main control module, an auxiliary control module, a clock module, a DC power supply module and a standby module, wherein:

[0042] The main control module includes a main control chip and an AC contactor KM. The main control chip uses an FPGA chip, which has the advantages of convenient and flexible programming, high integration, fast processing speed, low power consumption, and high cost performance. The FPGA chip reads the data of the clock module, collects the voltage information of several vehicles, and communicates with the inverters of several vehicles respectively. Through the AC contactor KM, the AC power of the unconnected vehicles is corrected and controlled to be connected in parallel after phase synchronization. The FPGA chip is set on the intelligent timing and synchronization control board of the subway vehicle, collects information from other modules and subway vehicles, and sends control instructions to other modules. This embodiment takes two subway vehicles, A and B, as examples. The AC output circuit of A is connected in parallel to the three voltage transformers of A. The analog signals output by the three voltage transformers of A are indirectly input to the AD input pins of the FPGA chip through filtering circuits, etc. The AC of B is connected to the three voltage transformers of B. The analog voltage signals output by the three voltage transformers of B are indirectly input to the AD input pins of the FPGA chip; the output pins of the FPGA chip indirectly drive the AC contactor KM, and the AC power of A and B is corrected and controlled to be connected in parallel after the phases are synchronized. The FPGA chip is also connected to the inverters of A and B. According to the detected AC phase output by the inverter of B, the AC phase output by the inverter of A is adjusted, so that the output phases of the inverters of A and B are synchronized, and then the AC contactor KM is driven to act, so that the AC power sources of the two are connected in parallel, and the coupling of the two vehicles is further controlled.

[0043] The auxiliary control module includes an auxiliary control chip, semiconductor devices, and heating and cooling devices. The auxiliary control chip uses an ARM chip, which has the advantages of high performance, low power consumption, and low price. The ARM chip outputs a PWM signal to control the semiconductor device to chop the DC power, thereby controlling the working efficiency of the heating and cooling devices. Semiconductor devices include IGBT and MOS tubes, and the heating and cooling devices are resistance wires and tiny fans. Since semiconductor devices are easily affected by temperature and drift, commonly known as "temperature drift", it is necessary to ensure that the chip on the intelligent timing and synchronization control board of the subway vehicle works within the normal range, thereby ensuring the normal operation of the intelligent timing and synchronization control board of the subway vehicle.

[0044] The resistance wire heats the crystal oscillator and other components, and the ARM chip outputs a PWM signal to control the IGBT to chop the DC power output by the DC power module, so as to indirectly control the average supply voltage of the resistance wire, and then control the heating power of the resistance wire, and indirectly control the output heat of the resistance wire to the chip on the intelligent timing and synchronization control board of the subway vehicle, and automatically adjust the working environment temperature of the FPGA chip in a closed loop within a time limit; at the same time, the ARM chip outputs a PWM signal to control the MOS tube, chop the DC power output by the DC power module, and then control the average input voltage of the micro fan, indirectly control the air volume of the micro fan, and then control the heat dissipation efficiency, and cooperate with the resistance wire to realize the closed-loop temperature automatic adjustment of the ambient temperature of the FPGA chip.

[0045] The clock module includes a crystal oscillator, which provides a clock signal to the FPGA chip, that is, provides a clock signal for the program running inside the FPGA chip to accumulate timing.

[0046] The DC power supply module supplies power to the main control module, auxiliary control module and clock module, that is, it supplies power to the FPGA chip, IGBT, MOS tube and ARM chip to ensure the normal operation of the intelligent timing and synchronization control board of the subway vehicle.

[0047] The backup module includes a clock chip and a backup battery. The clock chip uses a DS1302 chip, which has the advantages of wide operating voltage and high precision. When the DC power module is powered off, the backup battery can continue to supply power to the FPGA chip and the FPGA chip, ensuring that the DS1302 chip replaces the crystal oscillator to provide a clock signal to the FPGA chip. The backup battery uses a button battery, which is inexpensive and easy to obtain, reducing the manufacturing cost of the intelligent timing and synchronization control board for subway vehicles.

[0048] The FPGA chip is also connected to the onboard relay combination, which receives the drive instructions of the FPGA chip. When the AC power phases of the two subway vehicles are synchronized, the onboard relay is controlled to close, and then indirectly controls the AC contactor KM to close, controlling the AC power of several vehicles to be connected in parallel after phase synchronization, thereby enhancing the safety of synchronous parallel connection of the AC power of the two subway vehicles.

[0049] Embodiment 2:

[0050] like Figure 2 As shown, the control method of the subway vehicle intelligent timing synchronization control panel of the present invention comprises the following steps:

[0051] Step S1: Timing setting: write the conversion time of the voltage transformers at different phases of several vehicles into the main control chip, that is, the constant array in the FPGA chip program, and obtain the corresponding value by querying the array when using it.

[0052] Step S2: Perform calculation: The main control chip (FPGA chip) calculates the time intervals between the three-phase AC phases of several vehicles and the time interval required for delay of one of the vehicles;

[0053] The calculation formula for the time interval between the three-phase AC phases of several vehicles is as follows:

[0054] Δt 0 =K AS ×(t AUS +t AVS+ t AWS ) / 3+K AAD ×(t AUAD +t AVAD +t AWAD ) / 3+K ACT ×t ACT -[K AS ×(t BUS +t BVS +t BWS ) / 3+K BAD ×(t BUAD +t BVAD +t BWAD ) / 3+K BCT ×t BCT +K CTR ×t CTR ];

[0055] The above formula is calculated based on the three-phase AC phase lag of car A compared to car B, where: K AS is the average time correction coefficient required for the synchronous contactor of car A to operate; t AUS The time required for the U-phase synchronous contactor of car A to operate; t AVS The time required for the V-phase synchronous contactor of car A to operate; t AWS K is the time required for the synchronous contactor of phase W of car A to operate; AAD is the AD conversion delay interval correction coefficient of the FPGA chip for the analog voltage signal output by the voltage transformer of vehicle A; t AUAD t is the AD conversion delay interval of the analog voltage signal output by the FPGA chip to the U-phase voltage transformer of car A; AVAD t is the AD conversion delay interval of the analog voltage signal output by the FPGA chip to the V-phase voltage transformer of vehicle A; AWAD K is the AD conversion delay interval of the analog voltage signal output by the FPGA chip to the W-phase voltage transformer of car A; ACT is the delay time correction coefficient when the FPGA chip communicates with the inverter of vehicle A; t ACT K is the delay time when the FPGA chip communicates with the inverter of vehicle A; BS The average time correction coefficient required for the synchronous contactor of car B to operate; tBUS The time correction coefficient for the U-phase synchronous contactor of car B to operate; t BVS The time correction coefficient for the V-phase synchronous contactor of car B to operate; t BWS K is the time correction coefficient required for the W-phase synchronous contactor of car B to operate; BAD is the AD conversion delay interval correction coefficient of the analog voltage signal output by the FPGA chip to the U-phase voltage transformer of car B; t BUAD t is the AD conversion delay interval of the analog voltage signal output by the FPGA chip to the U-phase voltage transformer of car B; BVAD t is the AD conversion delay interval of the analog voltage signal output by the FPGA chip to the V-phase voltage transformer of car B; BWAD K is the AD conversion delay interval of the analog voltage signal output by the FPGA chip to the W-phase voltage transformer of the B car; BCT is the delay time correction coefficient when the FPGA chip communicates with the inverter of vehicle B; t BCT K is the delay time when the FPGA chip communicates with the inverter of vehicle B; CTR The delay time interval correction coefficient when the main control chip drives the AC contactor KM; t CTR It is the delay time interval when the FPGA chip drives the AC contactor KM.

[0056] When t AUS , t AVS , t AWS When the sum of the absolute values ​​of the pairwise errors is ≥ 2.3us, the coefficient K AS The value is 1.018; when t AUS , t AVS , t AWS When the sum of the absolute values ​​of the pairwise errors is less than 2.3us, the coefficient K AS The value is 0.9956;

[0057] When t AUAD , t AVAD , t AWAD When the sum of the absolute values ​​of the pairwise errors is ≥50ns, the coefficient K AAD The value is 1.009; when t AUAD , t AVAD , t AWAD When the sum of the absolute values ​​of the pairwise errors is less than 50ns, the coefficient K AS The value is 0.9963;

[0058] When t ACT ≥17ns, coefficient K ACT The value is 1.063; when t ACT <17ns, coefficient K ACT The value is 0.9976;

[0059] Coefficient K AS The value is 1.003;

[0060] When t BUAD , t BVAD , t BWAD When the sum of the absolute values ​​of the pairwise errors is ≥32ns, the coefficient K BAD The value is 1.009; when t BUAD , t BVAD , t BWAD When the sum of the absolute values ​​of the pairwise errors is less than 32ns, the coefficient K BAD The value is 0.9981.

[0061] When t BCT ≥13ns, coefficient K BCT The value is 1.026; when t BCT <13ns, coefficient K BCT The value is 0.9983;

[0062] When t CTR ≥0.2ns, coefficient K CTR The value is 1.005; when 0.1ns <t BCT <0.2ns, coefficient K BCT The value is 1.003; when t BCT ≤0.1ns, K BCT The value is 0.998.

[0063] The calculation formula for the delay time interval required for one vehicle is as follows:

[0064]

[0065] The above formula is calculated based on car B, where: △t 0 K is the time interval between the phase difference of the three-phase AC power of car A and car B, t is the time correction coefficient constant.

[0066] Step S3: Temperature control: using an anti-integral saturation PID control algorithm to control the temperature of the intelligent timing synchronization control board of the subway vehicle to enable it to operate normally;

[0067] The calculation formula of the PID control algorithm is as follows:

[0068]

[0069] Where: kp is the proportional coefficient, T is the integral time constant, TD is the differential time constant, error(t) is the control deviation between the given value of the PID controller and the actual output, and the calculation formula of error(t) is as follows:

[0070]

[0071] Among them: yd(t) is the given temperature value; y(t) is the actual output temperature value.

[0072] Step S4: Implement parallel access and coupling: The FPGA chip adjusts the AC power phase of several vehicles to synchronize the inverter output phases of several vehicles, and then drives the AC contactor KM to operate, so that the AC power supplies between several vehicles are connected in parallel, further realizing the coupling of several vehicles.

[0073] The PID control algorithm includes the following correction steps:

[0074] (1) Proportional link: Proportional response to the temperature deviation signal of the temperature control system; once the temperature deviation signal is generated, the controller immediately takes control action to reduce the temperature deviation.

[0075] (2) Integral link: eliminate temperature static difference and improve the system's zero difference; the strength of the integral effect depends on the integral time constant TI. The larger the TI, the weaker the integral effect, and vice versa.

[0076] (3) Differentiation link: reflects the changing trend of the temperature deviation signal and can introduce an effective early temperature correction signal into the system before the temperature deviation signal becomes too large, thereby speeding up the system's action speed and reducing the temperature adjustment time.

[0077] The so-called integral saturation phenomenon refers to the deviation in one direction of the system. The output of the PID control algorithm increases due to the continuous accumulation of the integral action, causing the actuator to reach the limit position. If the output u(k) is controlled to continue to increase, the output Xmax of the actuator cannot continue to increase. At this time, it is called that the computer output control quantity exceeds the normal range and enters the saturation zone. Once the system has a reverse deviation, the controller output u(k) will exit the saturation zone. The deeper it enters the saturation zone, the longer it takes to exit the saturation zone. During this period of time, the actuator still stays at the limit position and cannot make corresponding changes immediately with the deviation in the opposite direction. At this time, the system is like losing control, causing the control system to deteriorate. This phenomenon is called integral saturation or integral loss of control.

[0078] One of the methods to prevent integral saturation is the anti-integral saturation algorithm. The idea of ​​this method is to first determine whether the control amount u(k-1) at the previous moment exceeds the limit range when calculating u(k). If u(k-1)>umax, only negative deviations are accumulated. If u(k-1)<umax, only positive deviations are accumulated. This algorithm can prevent the control amount from staying in the saturation zone for a long time.

[0079] The beneficial effects of the present invention are as follows: the intelligent timing and synchronization control board for subway vehicles described in the present invention can accurately correct the phase of subway vehicles and realize safe parallel connection and coupling of vehicles. At the same time, the intelligent timing and synchronization control board for subway vehicles described in the present invention has a small size, a high degree of intelligence and a high control accuracy.

[0080] The present invention can be widely used in urban rail and subway control situations.

[0081] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0082] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An intelligent timing synchronization control panel for subway vehicles, characterized in that: It includes a main control module, an auxiliary control module, a clock module, a DC power supply module and a backup module, among which: The main control module includes a main control chip and an AC contactor KM. The main control chip reads the data of the clock module, collects the voltage information of several vehicles, and communicates with the inverters of several vehicles respectively. The AC contactor KM corrects and controls the AC power of several vehicles to be connected in parallel after phase synchronization. An auxiliary control module, including an auxiliary control chip, a semiconductor device, and a heating and cooling device. The auxiliary control chip outputs a PWM signal to control the semiconductor device to chop the direct current, thereby controlling the working efficiency of the heating and cooling device. The clock module includes a crystal oscillator, which provides a clock signal to the main control chip; A DC power supply module, which supplies power to the main control module, the auxiliary control module and the clock module; The backup module includes a clock chip and a backup battery. When the DC power module is powered off, the backup battery continues to supply power to the main control chip and the auxiliary control chip, ensuring that the clock chip replaces the crystal oscillator to provide a clock signal to the main control chip. The heating and cooling devices are resistance wire and micro fan, respectively, which realize heating and cooling of the intelligent timing synchronization control panel of the subway vehicle; The semiconductor device comprises an IGBT and a MOS tube, which respectively chop the direct current flowing to the resistance wire and the micro fan.

2. The intelligent timing synchronization control panel for subway vehicles according to claim 1 is characterized in that: The main control chip is also connected to an onboard relay assembly, and the onboard relay assembly receives a drive instruction from the main control chip to control the opening and closing of a circuit in the intelligent synchronous control board of a subway vehicle.

3. A control method for the intelligent timing synchronization control panel of a subway vehicle based on any one of claims 1 to 2, characterized in that: The following steps are involved: Step S1: Timing setting: write the conversion time of the voltage transformers at different phases of several vehicles into the constant array in the main control chip program, and obtain the corresponding value by querying the array when using; Step S2: Perform calculation: The main control chip calculates the time intervals between the three-phase AC phases of several vehicles and the time interval required for delay of one of the vehicles; Step S3: Temperature control: using an anti-integral saturation PID control algorithm to control the temperature of the intelligent timing synchronization control board of the subway vehicle to enable it to operate normally; Step S4: Implement parallel access and coupling: The main control chip adjusts the AC power phase of several vehicles to synchronize the inverter output phases of several vehicles, and then drives the AC contactor KM to operate, so that the AC power supplies between several vehicles are connected in parallel to achieve coupling of several vehicles.

4. The control method of the subway vehicle intelligent timing synchronization control panel according to claim 3 is characterized in that: The calculation formula of the time interval between the three-phase AC phases of several vehicles in step S2 is as follows: Δt0=K AS ×(t AUS +t AVS+ t AWS ) / 3+K AAD ×(t AUAD +t AVAD +t AWAD ) / 3+K ACT ×t ACT -[K AS ×(t BUS +t BVS +t BWS ) / 3+K BAD ×(t BUAD +t BVAD +t BWAD ) / 3+K BCT ×t BCT +K CTR ×t CTR ]; The above formula is calculated based on the three-phase AC phase lag of car A compared to car B, where: K AS is the correction coefficient of the average time required for the synchronous contactor of car A to operate; t AUS The time required for the U-phase synchronous contactor of car A to operate; t AVS The time required for the V-phase synchronous contactor of car A to operate; t AWS K is the time required for the synchronous contactor of phase W of car A to operate; AAD It is the correction coefficient of the delay interval of the AD conversion of the analog voltage signal output by the voltage transformer of vehicle A by the main control chip; t AUAD The AD conversion delay interval of the analog voltage signal output by the main control chip to the U-phase voltage transformer of car A; t AVAD The AD conversion delay interval of the analog voltage signal output by the main control chip to the V-phase voltage transformer of vehicle A; t AWAD K is the AD conversion delay interval of the analog voltage signal output by the main control chip to the W-phase voltage transformer of car A; ACT The delay time correction coefficient when the main control chip communicates with the inverter of vehicle A; t ACT K is the delay time when the main control chip communicates with the inverter of vehicle A; BS The average time correction coefficient required for the synchronous contactor of car B to operate; t BUS The time correction coefficient for the U-phase synchronous contactor of car B to operate; t BVS The time correction coefficient for the V-phase synchronous contactor of car B to operate; t BWS K is the time correction coefficient required for the W-phase synchronous contactor of car B to operate; BAD It is the delay interval correction coefficient of the AD conversion of the analog voltage signal output by the U-phase voltage transformer of car B by the main control chip; t BUAD The AD conversion delay interval of the analog voltage signal output by the main control chip to the U-phase voltage transformer of car B; t BVAD The AD conversion delay interval of the analog voltage signal output by the main control chip to the V-phase voltage transformer of car B; t BWAD K is the AD conversion delay interval of the analog voltage signal output by the main control chip to the W-phase voltage transformer of the B car; BCT The delay time correction coefficient when the main control chip communicates with the inverter of vehicle B; t BCT K is the delay time when the main control chip communicates with the inverter of vehicle B; CTR The delay time interval correction coefficient when the main control chip drives the AC contactor KM; t CTR It is the delay time interval when the main control chip drives the AC contactor KM.

5. The control method of the subway vehicle intelligent timing synchronization control panel according to claim 3 is characterized in that: The calculation formula for the delay time interval required for one of the vehicles in step S2 is as follows: The above formula is calculated based on car B, where: △t0 is the time interval between the phase of the three-phase AC power of car A and that of car B, K t is the time correction coefficient constant.

6. The control method of the subway vehicle intelligent timing synchronization control panel according to claim 3 is characterized in that: The calculation formula of the PID control algorithm in step S3 is as follows: Where: kp is the proportional coefficient, T is the integral time constant, and TD is the differential time constant.

7. The control method of the subway vehicle intelligent timing synchronization control panel according to claim 6 is characterized in that: The PID control algorithm includes the following correction steps: (1) Proportional link: proportional response to the temperature deviation signal of the temperature control system; (2) Integral link: eliminate temperature static difference and improve the system's error-free degree; (3) Differential link: reflects the changing trend of the temperature deviation signal and reduces the temperature adjustment time.

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