Voltage control circuit

Abstract

The voltage control circuit includes a tracking circuit, an operational amplifier, a transistor, a feedback circuit, and a sample-and-hold circuit. The tracking circuit generates an update enable voltage based on an enable voltage, a sampling enable voltage, and a sampling reference voltage. The operational amplifier includes a first input terminal for receiving an input voltage, a second input terminal for receiving a feedback voltage, and an output terminal for outputting a control voltage. The transistor includes a control terminal for receiving a control voltage, a first terminal for receiving a reference voltage, and a second terminal for outputting a regulated voltage. The feedback circuit is coupled between the second terminal of the transistor and the second input terminal of the operational amplifier to generate a feedback voltage based on the regulated voltage. The sample-and-hold circuit samples the input voltage to generate a sampling enable voltage and samples the feedback voltage to generate a sampling reference voltage.

Description

Technical Field

[0001] The present invention relates to an electronic circuit, in particular to a voltage control circuit of a power amplifier. Background Art

[0002] In communications devices, power amplifiers amplify signals for radio frequency (RF) transmission. The power of RF signals must meet communications standards to ensure transmission within a predetermined range while minimizing signal interference between devices. Since communications devices are typically powered by batteries, their power level gradually decreases over time. When the battery voltage is too low, the power supplied to the power amplifier is insufficient, causing the RF signal to fail to meet communications standards, increasing signal interference between devices, and reducing device performance. Summary of the Invention

[0003] An embodiment of the present invention provides a voltage control circuit comprising a tracking circuit, an operational amplifier, a reference terminal, a transistor, a feedback circuit, and a sample-and-hold circuit. The tracking circuit is configured to generate an updated enable voltage that is updated according to the enable voltage, a sampled enable voltage, and a sampled reference voltage. The operational amplifier comprises a first input terminal coupled to the tracking circuit for receiving an input voltage, a second input terminal for receiving a feedback voltage, and an output terminal for outputting a control voltage. The reference terminal is configured to provide a reference voltage. The transistor comprises a control terminal coupled to the output terminal of the operational amplifier for receiving the control voltage, a first terminal for receiving a reference voltage, and a second terminal for outputting a regulated voltage. The feedback circuit is coupled between the second terminal of the transistor and the second input terminal of the operational amplifier for generating a feedback voltage according to the regulated voltage. The sample-and-hold circuit is coupled to the tracking circuit, the operational amplifier, and the feedback circuit for sampling and holding the input voltage to generate a sampled enable voltage, and for sampling the feedback voltage to generate a sampled reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 Schematic diagram of a voltage control circuit in an embodiment of the present invention.

[0005] Figure 2 To display Figure 1 The waveform of the regulation voltage in .

[0006] Figure 3 for Figure 1 Schematic diagram of the sample and hold circuit in .

[0007] Figure 4 for Figure 1 Timing diagram of the voltage control circuit in .

[0008] Explanation of symbols

[0009] 1: Voltage control circuit

[0010] 10: Tracking Circuit

[0011] 12: Operational Amplifier

[0012] 14: Sample and hold circuit

[0013] 140,142: Transmission Gate

[0014] 15,16: Reference end

[0015] 17: Feedback circuit

[0016] 18: Power Amplifier

[0017] 20,22: Waveform

[0018] M1, M140 to M143: transistors

[0019] R1, R2, R140, R142: resistors

[0020] C140, C142: capacitors

[0021] Sin: AC signal

[0022] Sout: amplified AC signal

[0023] SW1 and SW2: switches

[0024] t0 to t4: time

[0025] V1: input voltage

[0026] V2: Feedback voltage

[0027] VBAT: reference voltage

[0028] Vc: control signal

[0029] Vc_bar: inverting control signal

[0030] Vclamp: sampling reference voltage

[0031] Vmask: shield

[0032] Vset: Enable voltage

[0033] V'set: Update enable voltage

[0034] Vset_max: sampling enable voltage

[0035] Vr0 to Vr3: voltage level

[0036] Vrd: sampling control voltage

[0037] Vrd_bar: inverted sampling control voltage

[0038] Vreg: regulated voltage DETAILED DESCRIPTION

[0039] Figure 1 Schematic diagram of a voltage control circuit 1 according to an embodiment of the present invention. The voltage control circuit 1 can function as a low dropout regulator (LDO regulator), powered by a reference voltage VBAT to generate a regulated voltage Vreg, and supplying the regulated voltage Vreg as power to a power amplifier (PA) 18. The voltage control circuit 1 can adjust the regulated voltage Vreg so that when the reference voltage VBAT is greater than or very close to the regulated voltage Vreg, the regulated voltage Vreg can still be maintained at a substantially stable predetermined level. The reference voltage VBAT is a variable voltage generated by a battery or battery pack that can gradually decrease over time. When the reference voltage VBAT drops to an excessively low level, the voltage control circuit 1 cannot maintain the regulated voltage Vreg at the predetermined level and will decrease along with the reference voltage VBAT.

[0040] The voltage control circuit 1 may include a tracking circuit 10, an operational amplifier 12, a sample and hold circuit 14, a reference terminal 16, a feedback circuit 17, and a transistor M1. Reference terminal 16 may provide a reference voltage VBAT. The operational amplifier 12 includes a first input terminal coupled to the tracking circuit 10, a second input terminal coupled to the feedback circuit 17, and an output terminal coupled to the transistor M1. The transistor M1 includes a control terminal coupled to the output terminal of the operational amplifier 12, a first terminal coupled to the reference terminal 16, and a second terminal coupled to the power amplifier 18. The feedback circuit 17 is coupled to the second terminal of the transistor M1 and the second input terminal of the operational amplifier 12 to generate a feedback voltage V2 based on the regulation voltage Vreg. The feedback voltage V2 may be positively correlated with the regulation voltage Vreg. The power amplifier 18 includes a power terminal for receiving the regulation voltage Vreg, an input terminal for inputting an AC signal Sin, and an output terminal for outputting an amplified AC signal Sout. The AC signal Sin and the amplified AC signal Sout may be radio frequency signals.

[0041] The first input terminal of the operational amplifier 12 can be an inverting input terminal, and the second input terminal of the operational amplifier 12 can be a non-inverting input terminal. The first input terminal of the operational amplifier 12 can receive an input voltage V1, and the second input terminal of the operational amplifier 12 can receive a feedback voltage V2. The output terminal of the operational amplifier 12 can generate a control voltage based on the difference between the feedback voltage V2 and the input voltage V1. The control terminal of the transistor M1 can receive the control voltage, and the second terminal of the transistor M1 can output a regulation voltage Vreg based on the control voltage. The transistor M1 can be a field-effect transistor (FET), such as a P-type metal-oxide-semiconductor field-effect transistor (MOSFET), and can be configured as a common-source amplifier stage. When the feedback voltage V2 is substantially equal to the input voltage V1, the control voltage is substantially equal to 0V, and the transistor M1 is turned on to generate the regulation voltage Vreg. When the feedback voltage V2 is less than the input voltage V1, the control voltage is less than 0V, and the conduction level of the transistor M1 increases, thereby increasing the regulation voltage Vreg. When the reference voltage VBAT is lower than the predetermined level of the regulation voltage Vreg, the regulation voltage Vreg outputted by the second terminal of the transistor M1 will be lower than the predetermined level. When the power amplifier 18 is turned off, the input voltage V1 must drop below the feedback voltage V2 to reduce the regulation voltage Vreg.

[0042] Figure 2The waveform diagram of the regulated voltage Vreg includes a mask Vmask defined in the communication standard, a waveform 20 of the regulated voltage Vreg that complies with the communication standard, and a waveform 22 of the regulated voltage Vreg that does not comply with the communication standard. Waveform 20 may correspond to the waveform generated by an embodiment of the present invention, while waveform 22 may correspond to a waveform generated by the prior art. When the power amplifier 18 is operating, the regulated voltage Vreg must not exceed the mask Vmask to comply with the communication standard and not cause signal interference to other devices. At time t0, the power amplifier 18 begins to turn on, and waveforms 20 and 22 begin to rise from a low level Vr0. At time t1, waveforms 20 and 22 rise to a predetermined level Vr1. The period between times t0 and t1 is referred to as the voltage ramp-up period. At time t2, the power amplifier 18 begins to turn off, and waveform 20 begins to fall from level Vr2, while waveform 22 remains at level Vr2. Level Vr2 may be lower than the predetermined level Vr1. The period between time t1 and t2 can be referred to as the power amplifier on period, during which power amplifier 18 amplifies AC signal Sin. At time t3, waveform 20 drops to level Vr3, and waveform 22 begins to drop from level Vr2. At time t4, both waveforms 20 and 22 drop to low level Vr0. The period between time t2 and t4 can be referred to as the ramp-down period. The period from time t4 to the next time power amplifier 18 is turned on, time t0, can be referred to as the power amplifier off period, during which power amplifier 18 is inoperable. Because waveform 22 begins to drop from level Vr2 at time t3, it exceeds mask Vmask at time t3, failing to comply with communication specifications and potentially causing signal interference to other devices. Furthermore, because waveform 22 abruptly drops from level Vr2 to low level Vr0 between time t3 and t4, it can generate transient noise, potentially interfering with signals in other internal circuits. In contrast, the waveform 20 decreases slowly during the voltage drop period and does not exceed the mask voltage Vmask, thus complying with communication standards and not likely to cause signal interference to other devices or internal circuits.

[0043] The voltage control circuit 1 can, via a sample-and-hold circuit 14 and a tracking circuit 10, cause the input voltage V1 to change in accordance with the feedback voltage V2 after time t2. For example, after time t2, the input voltage V1 is pulled to the feedback voltage V2 to generate a waveform 20 of a regulated voltage Vreg that complies with communication standards. The sample-and-hold circuit 14 can be coupled to the tracking circuit 10, the operational amplifier 12, and the feedback circuit 17. During the voltage drop period, the sample-and-hold circuit 14 can sample and hold the input voltage V1 to generate a sampled enable voltage Vset_max, and sample and hold the feedback voltage V2 to generate a sampled reference voltage Vclamp. The tracking circuit 10 can generate an updated enable voltage V'set that is updated with the enable voltage Vset based on the enable voltage Vset, the sampled enable voltage Vset_max, and the sampled reference voltage Vclamp. The updated enable voltage V'set can be positively correlated with the sampled reference voltage Vclamp and negatively correlated with the sampled enable voltage Vset_max. Specifically, the tracking circuit 10 may divide the sampled reference voltage Vclamp by the sampled enable voltage Vset_max to generate a ratio (Vclamp / Vset_max), and multiply the ratio (Vclamp / Vset_max) by the enable voltage Vset to generate the update enable voltage V'set, as shown in Formula 1:

[0044] V'set=(Vclamp / Vset_max)*Vset Formula 1

[0045] If the reference voltage VBAT is less than the predetermined level of the regulation voltage Vreg, the feedback voltage V2 is less than the input voltage V1, and the sampled reference voltage Vclamp is less than the sampled enable voltage Vset_max, the updated enable voltage V'set can be a scaled-down value of the enable voltage Vset according to the ratio (Vclamp / Vset_max). Tracking circuit 10 can be implemented as a multiplier circuit.

[0046] In one embodiment, the voltage control circuit 1 may further include switches SW1 and SW2. Switches SW1 and SW2 can be configured to switch between an enable voltage Vset and an update enable voltage V'set. During a voltage-falling period, the input voltage V1 is generated based on the update enable voltage V'set, and during a non-voltage-falling period, the input voltage V1 is generated based on the enable voltage Vset. The non-voltage-falling period may be all times other than the voltage-falling period, including a voltage-rising period, a power amplifier on period, and a power amplifier off period. Because the update enable voltage V'set may be a scaled-down value of the enable voltage Vset multiplied by a ratio (Vclamp / Vset_max), the input voltage V1 during the voltage-falling period may be pulled to the feedback voltage V2, causing the input voltage V1 to begin falling from the feedback voltage V2, thereby generating a waveform 20 of the regulated voltage Vreg that complies with communication specifications. The conduction states of switches SW1 and SW2 may be opposite. During the non-voltage-falling period, the first control signal Vc_bar turns off switch SW1, and the second control signal Vc turns on switch SW2. During the voltage drop period, the first control signal Vc_bar turns on switch SW1 for a first predetermined time, and the second control signal Vc turns off switch SW2 for a first predetermined time. The first predetermined time may be less than the voltage drop period. The second control signal Vc and the first control signal Vc_bar may be inverted signals and may be set to a logic low or logic high level. The second control signal Vc may be an active high signal, and the first control signal Vc_bar may be an active high signal. In this embodiment, switches SW1 and SW2 may be transistors of the same type, such as both N-type transistors, for example, NMOS transistors. In other embodiments, switches SW1 and SW2 may be transistors of different types, such as one N-type transistor and the other P-type transistor, so that the second control signal Vc and the first control signal Vc_bar may be in phase. Switch SW1 includes a control terminal for receiving a first control signal Vc_bar; a first terminal coupled to tracking circuit 10 for receiving an update enable voltage V'set; and a second terminal coupled to a first input terminal of operational amplifier 12 for outputting input voltage V1. Switch SW2 includes a control terminal for receiving a second control signal Vc; a first terminal for receiving an enable voltage Vset; and a second terminal coupled to a first input terminal of operational amplifier 12 for outputting input voltage V1.

[0047] Feedback circuit 17 may include feedback resistors R1 and R2. Feedback resistor R1 includes a first terminal coupled to the second terminal of transistor M1 and a second terminal coupled to the second input terminal of operational amplifier 12 for generating feedback voltage V2. Feedback resistor R2 includes a first terminal coupled to the second terminal of feedback resistor R1 and a second terminal coupled to reference terminal 15. Reference terminal 15 may provide a ground voltage, such as 0V. The impedance values of feedback resistors R1 and R2 can adjust the value of regulated voltage Vreg. When the impedance value of feedback resistor R1 increases and / or the impedance value of feedback resistor R2 decreases, regulated voltage Vreg increases; when the impedance value of feedback resistor R1 decreases and / or the impedance value of feedback resistor R2 increases, regulated voltage Vreg decreases. In some embodiments, the impedance values of feedback resistors R1 and R2 can adjust regulated voltage Vreg to (8 / 3)V'set. In other embodiments, regulated voltage Vreg can also be adjusted to other values by changing the impedance values of feedback resistors R1 and R2.

[0048] During the voltage rise period, the enable voltage Vset can be gradually increased from a low level to a high level. During the voltage fall period, the enable voltage Vset can be gradually increased from a high level to a low level. When the power amplifier is on, the enable voltage Vset can be maintained at a high level. When the power amplifier is off, the enable voltage Vset can be maintained at a low level. The low level can be 0V, and the high level can be greater than or equal to a logic high level. The enable voltage Vset can be externally input or generated by a voltage generator.

[0049] Figure 3 1 is a schematic diagram of the sample and hold circuit 14. The sample and hold circuit 14 includes a transmission gate 140, a resistor R140, a capacitor C140, a transmission gate 142, a resistor R142, and a capacitor C142.

[0050] The transmission gate 140 can sample the input voltage V1 based on the sampling control voltage Vrd and the inverted sampling control voltage Vrd_bar to generate the sampling enable voltage Vset_max. The resistor R140 includes a first end coupled to the transmission gate 140; and a second end for outputting the sampling enable voltage Vset_max. The capacitor C140 includes a first end coupled to the second end of the resistor R140; and a second end coupled to the reference terminal 15. The transmission gate 142 can sample the feedback voltage V2 based on the sampling control voltage Vrd and the inverted sampling control voltage Vrd_bar to generate the sampling reference voltage Vclamp. The resistor R142 includes a first end coupled to the transmission gate 142; and a second end for outputting the sampling reference voltage Vclamp. The capacitor C142 includes a first end coupled to the second end of the resistor R142; and a second end coupled to the reference terminal 15.

[0051] Transmission gate 140 includes transistor M140 and transistor M141. Transistor M140 includes a control terminal for receiving the sampled control voltage Vrd, a first terminal for receiving the input voltage V1, and a second terminal coupled to the first terminal of resistor R140. Transistor M141 includes a control terminal for receiving the inverted sampled control voltage Vrd_bar, a first terminal for receiving the input voltage V1, and a second terminal coupled to the first terminal of resistor R140. Transmission gate 142 includes transistor M142 and transistor M143. Transistor M142 includes a control terminal for receiving the sampled control voltage Vrd, a first terminal for receiving the feedback voltage V2, and a second terminal coupled to the first terminal of resistor R142. Transistor M143 includes a control terminal for receiving the inverted sampled control voltage Vrd_bar, a first terminal for receiving the feedback voltage V2, and a second terminal coupled to the first terminal of resistor R142. Transistors M140 and M142 may be of a first semiconductor type, while transistors M141 and M143 may be of a second semiconductor type. The first semiconductor type and the second semiconductor type may be different. For example, transistors M140 and M142 may be N-type transistors, such as NMOS transistors. Transistors M141 and M143 may be P-type transistors, such as PMOS transistors.

[0052] The sampling control voltage Vrd and the inverted sampling control voltage Vrd_bar may be inverted and may be set to a logic low or logic high level. The sampling control voltage Vrd may be an active high signal, and the inverted sampling control voltage Vrd_bar may be an active low signal. In some embodiments, the sampling control voltage Vrd and the second control signal Vc may be inverted, and the inverted sampling control voltage Vrd_bar and the first control signal Vc_bar may be inverted. During the voltage drop period, the sampling control voltage Vrd may turn on the transmission gate 140 for a first predetermined time to sample the sampling enable voltage Vset_max from the input voltage V1 and store the sampling enable voltage Vset_max in the capacitor C140. The sampling control voltage Vrd may turn on the transmission gate 142 for a first predetermined time to sample the sampling reference voltage Vclamp from the feedback voltage V2 and store the sampling reference voltage Vclamp in the capacitor C142. The first predetermined time for sampling the control voltage Vrd may be less than the voltage falling period and may be substantially equal to the first predetermined time during which the first control signal Vc_bar turns on the switch SW1. The sampling enable voltage Vset_max may be the maximum sampled value of the input voltage V1 during the first predetermined time, and the sampling reference voltage Vclamp may be the maximum sampled value of the feedback voltage V2 during the first predetermined time.

[0053] Figure 41 is a timing diagram of the voltage control circuit 1 , including the regulation voltage Vreg, mask Vmask, enable voltage Vset, sampling control voltage Vrd, inverted sampling control voltage Vrd_bar, second control signal Vc, first control signal Vc_bar, sampling enable voltage Vset_max, sampling reference voltage Vclamp and update enable voltage V'set. At time t2, the voltage drop period begins. The sampling control voltage Vrd is pulled from a logic low level to a logic high level, and the inverted sampling control voltage Vrd_bar is pulled from a logic high level to a logic low level. The transmission gate 140 in the sample and hold circuit 14 is enabled to sample the input voltage V1 to generate the sampling enable voltage Vset_max. The transmission gate 142 in the sample and hold circuit 14 is enabled to sample the feedback voltage V2 to generate the sampling reference voltage Vclamp. The tracking circuit 10 generates the update enable voltage V'set according to formula (1). The second control signal Vc is pulled from a logic high level to a logic low level, and the first control signal Vc_bar is pulled from a logic low level to a logic high level. The switch SW1 is turned on and the switch SW2 is turned off to pull the input voltage V1 down according to the update enable voltage V'set, so that the regulation voltage Vreg begins to drop. At time t3, the sampling control voltage Vrd is pulled from a logic high level to a logic low level, and the inverted sampling control voltage Vrd_bar is pulled from a logic low level to a logic high level. Transmission gates 140 and 142 in the sample and hold circuit 14 are disabled, the second control signal Vc is pulled from a logic low level to a logic high level, and the first control signal Vc_bar is pulled from a logic high level to a logic low level. Switch SW1 is turned off, and switch SW2 is turned on, pulling the input voltage V1 lower in accordance with the enable voltage Vset. Since the input voltage V1 begins to be lower than the feedback voltage V2 at this point, the operational amplifier 12 gradually pulls the regulation voltage Vreg lower in accordance with the input voltage V1. The feedback voltage V2 also gradually decreases along with the regulation voltage Vreg. At time t4, the voltage drop period ends, the enable voltage Vset drops to a low level Vr0, and the regulation voltage Vreg also drops to a low level Vr0. The regulated voltage Vreg decreases slowly during the voltage drop period and does not exceed the mask voltage Vmask, thus complying with communication specifications and not easily causing signal interference to other devices or internal circuits.

[0054] In summary, after the voltage drop period begins, the voltage control circuit 1 of the embodiment of the present invention can change the input voltage V1 along with the feedback voltage V2 via the sample and hold circuit 14 and the tracking circuit 10, thereby producing a smoother falling waveform for the regulated voltage Vreg. This complies with communication standards, reduces transient noise, and is less likely to cause signal interference to other devices or internal circuits, thereby increasing device performance.

[0055] The above description is only a preferred embodiment of the present invention. Any equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A voltage control circuit, characterized in that: Include: a tracking circuit for generating an update enable voltage updated with the enable voltage according to an enable voltage, a sample enable voltage and a sample reference voltage; an operational amplifier comprising a first input terminal coupled to the tracking circuit for receiving a first input voltage, a second input terminal for receiving a feedback voltage, and an output terminal for outputting a control voltage; a first reference terminal for providing a reference voltage; a first transistor comprising a control terminal coupled to the output terminal of the operational amplifier for receiving the control voltage, a first terminal for receiving the reference voltage, and a second terminal for outputting a regulation voltage; a feedback circuit coupled between the second terminal of the first transistor and the second input terminal of the operational amplifier, for generating the feedback voltage according to the regulation voltage; a sample and hold circuit coupled to the tracking circuit, the operational amplifier, and the feedback circuit, for sampling the first input voltage to generate the sampling enable voltage, and sampling the feedback voltage to generate the sampling reference voltage; a first switch comprising a control terminal for receiving a first control signal, a first terminal coupled to the tracking circuit for receiving the update enable voltage, and a second terminal coupled to the first input terminal of the operational amplifier for outputting the first input voltage; and A second switch includes a control terminal for receiving a second control signal, a first terminal for receiving the enabling voltage, and a second terminal coupled to the first input terminal of the operational amplifier for outputting the first input voltage.

2. The voltage control circuit according to claim 1, wherein: The feedback circuit further comprises: a first feedback impedance comprising a first terminal coupled to the second terminal of the first transistor and a second terminal coupled to the second input terminal of the operational amplifier for generating the feedback voltage; and A second feedback impedance includes a first end coupled to the second end of the first feedback impedance and a second end coupled to a second reference end.

3. The voltage control circuit according to claim 1, wherein: The reference voltage is variable.

4. The voltage control circuit according to claim 3, wherein: The reference voltage decreases over time.

5. The voltage control circuit according to claim 1, wherein: The tracking circuit is used to generate the update enable voltage which is positively correlated with the sampling reference voltage and negatively correlated with the sampling enable voltage.

6. The voltage control circuit according to claim 1, wherein: The tracking circuit is used for dividing the sample reference voltage by the sample enable voltage to generate a ratio, and multiplying the ratio and the enable voltage to generate the update enable voltage.

7. The voltage control circuit according to claim 2, wherein: The sampling and holding circuit includes: a first transmission gate for sampling the first input voltage according to a sampling control voltage and an inverted sampling control voltage to generate the sampling enable voltage; a first resistor comprising a first terminal coupled to the first transmission gate and a second terminal for outputting the sampling enable voltage; a first capacitor comprising a first terminal coupled to the second terminal of the first resistor, and a second terminal, coupled to the second reference end; a second transmission gate for sampling the feedback voltage according to the sampling control voltage and the inverted sampling control voltage to generate the sampling reference voltage; a second resistor comprising a first terminal coupled to the second transmission gate, and a second terminal for outputting the sampled reference voltage; and a second capacitor comprising a first terminal coupled to the second terminal of the second resistor, and a second terminal, coupled to the second reference end.

8. The voltage control circuit according to claim 7, wherein: in: The sampling control voltage and the inverted sampling control voltage are in opposite phases to each other; and During a voltage drop period, the sampled control voltage turns on the first transmission gate and the second transmission gate for a first predetermined time.

9. The voltage control circuit according to claim 8, wherein: The first predetermined time is shorter than the voltage drop period.

10. The voltage control circuit according to claim 7, wherein: in: The first transmission gate comprises: a second transistor comprising a control terminal for receiving the sampled control voltage, a first terminal for receiving the first input voltage, and a second terminal coupled to the first terminal of the first resistor; and a third transistor comprising a control terminal for receiving the inverted sampling control voltage, a first terminal for receiving the first input voltage, and a second terminal coupled to the first terminal of the first resistor; and The second transmission gate comprises: a fourth transistor comprising a control terminal for receiving the sampled control voltage, a first terminal for receiving the feedback voltage, and a second terminal coupled to the first terminal of the second resistor; and A fifth transistor includes a control terminal for receiving the inverted sampling control voltage, a first terminal for receiving the feedback voltage, and a second terminal coupled to the first terminal of the second resistor.

11. The voltage control circuit according to claim 10, wherein: The second transistor and the fourth transistor are N-type transistors, and the first transistor, the third transistor and the fifth transistor are P-type transistors.

12. The voltage control circuit according to claim 1, wherein: The conduction states of the first switch and the second switch are opposite.

13. The voltage control circuit according to claim 1, wherein: in; During a non-voltage falling period, the first control signal is used to turn off the first switch, and the second control signal is used to turn on the second switch; and During a voltage drop period, the first control signal is used to turn on the first switch for a first predetermined time, and the second control signal is used to turn off the second switch for the first predetermined time.

14. The voltage control circuit according to claim 13, wherein: The first predetermined time is shorter than the voltage drop period.

15. The voltage control circuit according to claim 1, wherein: The first switch and the second switch are N-type transistors, and the first transistor is a P-type transistor.

16. The voltage control circuit according to claim 1, wherein: The first transistor is used to output the regulated voltage to a power amplifier.

17. The voltage control circuit according to claim 16, wherein: The power amplifier includes: a power supply terminal for receiving the regulated voltage; an input terminal for inputting an AC signal; and An output terminal is used to output the amplified AC signal.

18. The voltage control circuit according to claim 1, wherein: The first input terminal of the operational amplifier is an inverting input terminal, and the second input terminal of the operational amplifier is a non-inverting input terminal.

19. The voltage control circuit according to claim 1, wherein: The tracking circuit is a multiplier circuit.

Images