Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate; forming a plurality of source-drain structures, a plurality of gate structures and a first protection structure, wherein the source-drain structures are located in the substrate on both sides of the gate structure, the gate structure is located on the substrate, the gate structure comprises a gate electrode layer, and the first protection structure is located on the top surface of the gate electrode layer; forming a plurality of first conductive structures on the substrate, wherein the first conductive structure is located on the source-drain structures on at least one side of the gate structure; after forming the first conductive structure, forming a second protection structure and a first sidewall, wherein the second protection structure is located on the top surface of the first conductive structure, and the first sidewall is located between the first protection structure and the second protection structure. Thus, the reliability of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. As the most basic semiconductor device, the device is currently being widely used.

[0003] Generally, in the process of manufacturing semiconductor devices, a plug (Diffusion Contact) electrically connected to the source-drain doping layer is formed in the active region, and a plug (Gate Contact) electrically connected to the gate is formed outside the active region to achieve electrical connection between the semiconductor device and the external circuit. At the same time, the distance between the plug electrically connected to the source-drain doping layer and the plug electrically connected to the gate is increased to reduce the risk of short circuit. On this basis, a method for forming a plug electrically connected to the gate in the active region is proposed. By forming the plug electrically connected to the gate and the plug electrically connected to the source-drain doping layer in the active region, the area occupied by the semiconductor device can be reduced, so that the integration of the semiconductor device can be improved.

[0004] However, the reliability of the semiconductor structure formed by the prior art needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the reliability of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a plurality of gate structures located on the substrate, the gate structure including a gate electrode layer; a plurality of source-drain structures located in the substrate on both sides of the gate structure; a first protection structure located on the top surface of the gate electrode layer; a first conductive structure located on the substrate, the first conductive structure is also located on the source-drain structure on at least one side of the gate structure; a second protection structure located on the top surface of the first conductive structure; and a first side wall located between the first protection structure and the second protection structure.

[0007] Optionally, the first protection structure includes a first region and a second region located on the first region, and the first conductive structure is also located on a side wall surface of the first protection structure in the first region.

[0008] Optionally, a first groove is provided in the first protection structure of the second area, and the first side wall is also located in the first groove.

[0009] Optionally, an angle between a sidewall surface of the first protection structure in the second region and a normal line along the substrate surface is within 4 degrees.

[0010] Optionally, the material of the first protection structure includes silicon nitride or silicon oxide; the material of the second protection structure includes silicon nitride or silicon oxide.

[0011] Optionally, the material of the first protection structure is the same as that of the second protection structure.

[0012] Optionally, the material of the first sidewall spacer includes silicon nitride or silicon oxide.

[0013] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of source-drain structures, a plurality of gate structures and a first protective structure, wherein the source-drain structures are located in the substrate on both sides of the gate structure, the gate structure is located on the substrate, the gate structure includes a gate electrode layer, and the first protective structure is located on the top surface of the gate electrode layer; forming a plurality of first conductive structures on the substrate, wherein the first conductive structure is located on the source-drain structures on at least one side of the gate structure; after forming the first conductive structure, forming a second protective structure and a first side wall, wherein the second protective structure is located on the top surface of the first conductive structure, and the first side wall is located between the first protective structure and the second protective structure.

[0014] Optionally, the first protection structure includes a first region and a second region located on the first region, and the first conductive structure is also located on a side wall surface of the first protection structure in the first region.

[0015] Optionally, it also includes: after forming the first conductive structure and before forming the second protective structure and the first side wall, etching the side wall of the first protective structure in the second area to form a first groove in the first protective structure in the second area, and the first side wall is also located in the first groove.

[0016] Optionally, an angle between a sidewall surface of the first protection structure in the second region and a normal line along the substrate surface is within 4 degrees.

[0017] Optionally, it also includes: before forming the first conductive structure, forming a second side wall on the side wall surfaces of the gate structure and the first protective structure, the top surface of the second side wall is also located between the top surface of the gate structure and the top surface of the first protective structure, and the first side wall is also located on the top surface of the second side wall.

[0018] Optionally, the method further includes: before forming the first conductive structure, forming a first dielectric structure on the surface of the substrate, wherein the first dielectric structure is also located on the sidewall surfaces of the gate structure and the first protective structure.

[0019] Optionally, the method for forming the first conductive structure includes: forming a first mask structure on the surface of the first protective structure and the first dielectric structure, the first mask structure exposing the first dielectric structure between adjacent gate structures; using the first mask structure as a mask, etching the first dielectric structure until the substrate surface is exposed, and forming a first conductive opening in the first dielectric structure; forming a first conductive material layer in the first conductive opening; etching the first conductive material layer until a portion of the side wall surface of the first protective structure is exposed to form the first conductive structure.

[0020] Optionally, it also includes: before forming the first mask structure, forming an initial second dielectric structure on the surface of the first dielectric structure and the surface of the first protective structure; before etching the first dielectric structure, etching the initial second dielectric structure with the first mask structure until the surface of the first dielectric structure is exposed to form a first sidewall and a second dielectric structure.

[0021] Optionally, the method for forming the first sidewall and the second protection structure includes: forming a first sidewall film on the surfaces of the first conductive structure, the second dielectric structure and the first protection structure; etching the first sidewall film using an anisotropic etching process until the surface of the first conductive structure is exposed to form an initial first sidewall; forming a second protection structure material layer on the surfaces of the initial first sidewall, the first conductive structure and the second dielectric structure; and planarizing the second protection structure material layer, the initial first sidewall and the second dielectric structure until the surface of the first protection structure is exposed to form a second protection structure.

[0022] Optionally, the method for forming the first sidewall includes: forming a first sidewall film on the surfaces of the first conductive structure and the first protective structure; and etching the first sidewall film using an anisotropic etching process until the top surface of the first protective structure and the surface of the first conductive structure are exposed.

[0023] Optionally, the method for forming the second protection structure includes: forming a second protection structure material layer on the first protection structure, the first sidewall and the first conductive structure surface; and planarizing the second protection structure material layer until the surface of the first protection structure is exposed.

[0024] Optionally, in the normal direction along the surface of the first protection structure, the thickness of the first spacer film ranges from 10 angstroms to 50 angstroms.

[0025] Optionally, it also includes: after forming the first sidewall and the second protective structure, forming a second conductive opening in the second protective structure, wherein the bottom of the second conductive opening exposes at least a portion of the surface of the first conductive structure; and forming a second conductive structure in the second conductive opening.

[0026] Optionally, it also includes: after forming the first sidewall and the second protection structure, forming a third conductive opening in the first protection structure, the bottom of the third conductive opening exposes at least a portion of the gate electrode layer surface; forming a third conductive structure in the third conductive opening.

[0027] Optionally, the first protective structure and the second protective structure are made of the same material.

[0028] Optionally, the base includes a substrate and a plurality of fin structures that are separated from each other and located on the substrate, and the gate structure spans across the plurality of fin structures.

[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0030] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the first protective structure formed is located on the top surface of the gate electrode layer, the second protective structure formed is located on the top surface of the first conductive structure, and the first side wall formed is located between the first protective structure and the second protective structure. Therefore, by selecting the material of the first side wall, in the process of etching the first protective structure, the etching selectivity of the first protective structure and the first side wall is relatively large, and in the process of etching the second protective structure, the etching selectivity of the second protective structure and the first side wall is relatively large. Therefore, when etching the first protective structure and the second protective structure, the first side wall can be used to block the etching of the structure between the gate electrode layer and the first conductive structure at the bottom of the first side wall, thereby reducing the risk of exposure of the side wall surface of the gate electrode layer and the side wall surface of the first conductive structure, reducing the risk of short circuit between the gate electrode layer and the first conductive structure, and improving the reliability of the semiconductor structure.

[0031] Furthermore, since a first groove is formed in the first protection structure of the second region and the first side wall is also located in the first groove, the width of the first side wall is increased, thereby improving the blocking ability of the first side wall when etching the first protection structure and the second protection structure, thereby better reducing the risk of short circuit between the gate electrode layer and the first conductive structure, and improving the reliability of the semiconductor structure.

[0032] Furthermore, since the angle between the side wall surface of the first protection structure in the second zone and the normal along the substrate surface is within 4 degrees, the verticality of the side wall surface of the first protection structure in the second zone is ensured. Therefore, the side wall surface of the first side wall located in the first groove can be more vertical, so that the thickness of the first side wall can be more uniform. Therefore, when etching the first protection structure and the second protection structure, the blocking ability of the first side wall is further improved, so as to better reduce the risk of short circuit between the gate electrode layer and the first conductive structure, and improve the reliability of the semiconductor structure.

[0033] Furthermore, since the top surface of the second sidewall spacer is also located between the top surface of the gate structure and the top surface of the first protection structure, the margin of loss of the second sidewall spacer is increased on the basis of spacing the gate structure and the first conductive structure, thereby further reducing the risk of exposure of the sidewall surface of the gate electrode layer and the sidewall surface of the first conductive structure when etching the first protection structure and the second protection structure, reducing the risk of short circuit between the gate electrode layer and the first conductive structure, and improving the reliability of the semiconductor structure. Moreover, since the second sidewall spacer is formed before forming the first conductive structure, the first sidewall spacer and the second sidewall spacer are formed separately, thereby improving the independence of the process of forming the first sidewall spacer and the second sidewall spacer, and improving the degree of freedom in selecting the materials of the first sidewall spacer and the second sidewall spacer, and further, while reducing the risk of short circuit between the gate electrode layer and the first conductive structure through the first sidewall spacer, the material of the second sidewall spacer that has less influence on the electrical performance of the gate structure can be selected, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 to Figure 2 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure;

[0035] Figure 3 is a schematic cross-sectional structural diagram of a step in another method for forming a semiconductor structure;

[0036] Figures 4 to 18 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0037] As described in the background art, the reliability of semiconductor structures still needs to be improved. The reasons why the reliability of semiconductor structures is poor are described in detail below with reference to the accompanying drawings.

[0038] Figure 1 to Figure 2 The invention is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure.

[0039] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 includes an active area A, and a plurality of mutually separate fins (not shown) are formed on the substrate 100; a plurality of gate structures 110 spanning the fins, source-drain doped regions 101 located on both sides of the gate structure 110, a gate protection structure 111 located on the top surface of the gate structure 110, a conductive structure 120 located on the surface of the source-drain doped regions 101, an interconnection protection structure 121 located on the top surface of the conductive structure 120, an etch stop layer 130 located between the sidewalls of the gate structure 110 and the conductive structure 120, and a dielectric structure (not shown) surrounding the gate structure 110 are formed on the substrate 100.

[0040] Please refer to Figure 2, remove a portion of the gate protection structure 111 on the active area A to form a first plug opening 141, and the gate structure 110 is exposed at the bottom of the first plug opening 141; remove a portion of the interconnection protection structure 121 on the active area A to form a second plug opening (not shown), and the conductive structure 120 is exposed at the bottom of the second plug opening; form a first plug (not shown) in the first plug opening 141, and form a second plug in the second plug opening.

[0041] exist Figure 1 to Figure 2 In the illustrated embodiment, the material of the etch stop layer 130 and the material of the gate protection structure 111 are silicon nitride, and the material of the interconnect protection structure 121 is silicon oxide. Therefore, during the etching process for forming the second plug opening, the risk of exposure of the side wall of the gate structure 120 is reduced through the protection of the etch stop layer 130, thereby reducing the risk of short circuit between the second plug and the gate structure 110, that is, reducing the risk of short circuit between the gate structure 110 and the conductive structure 120.

[0042] However, since the material of the etch stop layer 130 is the same as that of the gate protection structure 111, when forming the first plug opening 141, the etch stop layer 130 on the sidewall of the gate protection structure 111 is easily removed, thereby causing the first plug opening 141 to expose the area B (such as Figure 2 The side wall of the conductive structure 120 in FIG. 1 is shown in FIG. 1 , causing a short circuit between the first plug and the conductive structure 120, that is, causing a short circuit between the gate structure 110 and the conductive structure 120, resulting in poor reliability of the semiconductor structure.

[0043] In another method for forming a semiconductor structure, by lowering the etch stop layer 131 (eg Figure 3 The top surface height of the conductive structure 120 and the top surface of the etching stop layer 131 are formed to form an interconnect protection structure 122 (as shown in FIG. Figure 3 As shown), thus, through the protection of the interconnect protection structure 122, during the etching process of forming the first plug opening (not shown), the etch stop layer 131 is not easily etched, thereby reducing the risk of exposing the side wall of the conductive structure 120, thereby reducing the risk of short circuit between the first plug and the conductive structure 120.

[0044] However, since the top surface height of the etch stop layer 131 is reduced, the spacing between the interconnect protection structure 122 and the gate structure 110 is reduced. At the same time, during the etching process for forming the second plug opening (not shown), the etchant is more likely to accumulate at the corners of the second plug opening (such as Figure 3As shown in FIG. 1 , the etching stop layer 131 at the corner of the second plug opening is easily consumed. Therefore, when the interconnect protection structure 122 is removed, the side wall surface of the gate structure 110 in the region C is easily exposed, causing a short circuit between the second plug and the gate structure 110, that is, causing a short circuit between the gate structure 110 and the conductive structure 120, resulting in poor reliability of the semiconductor structure.

[0045] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, by forming a first sidewall and locating the first sidewall between the first protection structure and the second protection structure, thereby improving the reliability of the formed semiconductor structure.

[0046] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] Figures 4 to 18 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0048] Please refer to Figure 4 , providing a substrate.

[0049] In this embodiment, the base includes a substrate 200 and a plurality of fin structures 201 that are separated from each other and located on the substrate 200 .

[0050] The material of the substrate 200 includes semiconductor material.

[0051] In this embodiment, the material of the substrate 200 is silicon.

[0052] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multinary semiconductor materials composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, multinary semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0053] Next, a plurality of source-drain structures, a gate structure and a first protection structure are formed, wherein the source-drain structures are located in the substrate on both sides of the gate structure, the gate structure is located on the substrate, the gate structure includes a gate electrode layer, and the first protection structure is located on the top surface of the gate electrode layer.

[0054] For details on the process of forming the gate structure and the first protection structure, please refer to Figure 5 to Figure 6 .

[0055] Please refer to Figure 5, forming a plurality of dummy gate structures 210 on the surface of the substrate, wherein the dummy gate structure 210 spans the fin structure 201; forming gate sidewalls (not shown) on the sidewalls of the dummy gate structure 210; after forming the gate sidewalls, forming source-drain structures 202 in the substrate on both sides of the dummy gate structure 210; after forming the source-drain structure 202, forming initial second sidewalls 230 on the surfaces of the gate sidewalls, the surfaces of the source-drain structure 202 and the substrate; after forming the initial second sidewalls 230, forming a first dielectric structure 220 on the surface of the substrate, wherein the first dielectric structure 220 is also located on the sidewalls of the dummy gate structure 210.

[0056] Specifically, in this embodiment, the source-drain structure 202 is located in the fin structure 201 on both sides of the dummy gate structure 210 .

[0057] In this embodiment, the material of the dummy gate structure 210 includes polysilicon.

[0058] In this embodiment, the method for forming the dummy gate structure 210 includes: forming a dummy gate material film (not shown) on the substrate covering the surface of the fin structure 201; patterning the dummy gate material film until the substrate surface is exposed, and forming a dummy gate structure 210 on the substrate that spans the fin structure 201, wherein the top surface of the dummy gate structure 210 is higher than the top surface of the fin structure 201.

[0059] In this embodiment, the material of the gate spacer includes a low-k dielectric material (k is less than 3.9).

[0060] In this embodiment, the method for forming the source-drain structure 202 includes: forming source-drain openings (not shown) in the fin structure 201 on both sides of the dummy gate structure 210; and forming the source-drain structure 202 in the source-drain openings using an epitaxial process.

[0061] In the process of forming the source-drain structure 202 , the gate spacer is used to define the formation position of the source-drain structure.

[0062] In this embodiment, the initial second spacer 230 provides material for subsequently forming a second spacer, and the initial second spacer 230 is also used to protect the gate spacer and the substrate to improve the oxidation problem of the gate spacer and the substrate.

[0063] In other embodiments, the initial second spacer is not formed.

[0064] In this embodiment, the first dielectric structure 220 provides support for forming a gate structure and a first protection structure.

[0065] In this embodiment, the method for forming the first dielectric structure 220 includes: forming a first dielectric structure material layer (not shown) on the surface of the dummy gate structure 210 and the substrate, wherein the surface of the first dielectric structure material layer is higher than the top surface of the dummy gate structure 210; and planarizing the first dielectric structure material layer until the top surface of the dummy gate structure 210 is exposed.

[0066] The formation process of the first dielectric structure material layer includes: a spin coating process or a deposition process, etc. The deposition process is, for example, a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD) or an atomic layer deposition process (ALD).

[0067] The process of planarizing the first dielectric structure material layer includes an etch-back process or a chemical mechanical polishing (CMP) process, etc.

[0068] In this embodiment, the method for forming the semiconductor structure further includes: before forming the dummy gate structure 210 , forming a base dielectric layer (not shown) on the surface of the substrate 200 , wherein the base dielectric layer is also located on a portion of the sidewall surface of the fin structure.

[0069] The function of the substrate dielectric layer is to electrically insulate adjacent fin structures 201 and between the semiconductor device and the substrate.

[0070] Please refer to Figure 6 After forming the first dielectric structure 220, the dummy gate structure 210 is removed, and a plurality of gate openings (not shown) are formed in the first dielectric structure 220; a gate structure 240 spanning across a plurality of fin structures 201 is formed in the gate opening, the gate structure 240 includes a gate electrode layer 241, and, in a direction perpendicular to the substrate surface, the thickness of the gate structure 240 is less than the depth of the gate opening; a first protection structure 250 is formed in the gate opening on the top surface of the gate electrode layer 241.

[0071] Specifically, in this embodiment, the first dielectric structure 220 is also located on the sidewalls of the gate structure 240 and the first protection structure 250 .

[0072] In this embodiment, the first protection structure 250 includes a first region I and a second region II located on the first region I.

[0073] In this embodiment, the gate structure 240 also includes: a gate dielectric layer (not shown) located on the sidewalls and bottom of the gate opening and a work function layer (not shown) located on the surface of the gate dielectric layer, and the gate electrode layer 241 is located on the surface of the work function layer.

[0074] The material of the gate dielectric layer includes a high dielectric constant material (dielectric constant greater than 3.9), which includes hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0075] The material of the gate electrode layer includes a metal material, for example, one or a combination of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0076] The material of the work function layer includes titanium nitride, tantalum nitride or titanium aluminum.

[0077] In this embodiment, the first protection structure 250 is also located on the top surfaces of the gate dielectric layer and the work function layer.

[0078] In this embodiment, the method for forming the gate structure 240 includes: forming a gate dielectric material layer (not shown) on the surface of the first dielectric structure 220 and in the gate opening; forming a work function material layer (not shown) on the surface of the gate dielectric material layer; forming a gate electrode material layer (not shown) on the surface of the work function material layer, and the gate electrode material layer fills the gate opening; planarizing the gate electrode material layer, the work function material layer and the gate dielectric material layer until the surface of the first dielectric structure 220 is exposed to form an initial gate structure (not shown); and etching the initial gate structure until the gate structure 240 is formed.

[0079] The process of forming the gate dielectric material layer includes an oxidation process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0080] The process of forming the work function material layer includes a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0081] The process of forming the gate electrode material layer includes a metal electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0082] The process of planarizing the gate electrode material layer, the work function material layer and the gate dielectric material layer includes an etch-back process or a chemical mechanical polishing process.

[0083] The process of etching the initial gate structure includes a dry etching process or a wet etching process.

[0084] In this embodiment, the method for forming the first protection structure 250 includes: forming a first protection structure material layer (not shown) in the gate opening on the top surface of the gate electrode layer 241 and on the surface of the first dielectric structure 220; and planarizing the first protection structure material layer until the surface of the first dielectric structure 220 is exposed.

[0085] The process of forming the first protective structure material layer includes a spin coating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0086] The process of planarizing the first protection structure material layer includes an etch-back process or a chemical mechanical polishing process.

[0087] In this embodiment, the material of the first dielectric structure 220 is silicon oxide.

[0088] In other embodiments, the material of the first dielectric structure includes at least one of SiOCH, SiOH and SiCN.

[0089] In this embodiment, the material of the first protection structure 250 is silicon nitride.

[0090] In other embodiments, the material of the first protection structure includes silicon oxide.

[0091] In this embodiment, before subsequently forming the first mask structure, an initial second dielectric structure 260 is formed on the surface of the first dielectric structure 220 and the surface of the first protection structure 250 .

[0092] The functions of the initial second dielectric structure 260 are: to provide materials for the subsequent formation of the second dielectric structure; to improve the flatness of the surface of the semiconductor structure to improve the graphic accuracy of the first mask structure formed subsequently; and to protect the top surface of the first protective structure 250 in the subsequent process of forming the first conductive opening, reduce the impact of the process of forming the first conductive opening on the first protective structure 250, and improve the performance and reliability of the semiconductor structure.

[0093] In this embodiment, the material of the initial second dielectric structure 260 is the same as the material of the first dielectric structure 220 .

[0094] In other embodiments, the material of the initial second dielectric structure is different from the material of the first dielectric structure.

[0095] In another embodiment, no initial second dielectric structure is formed.

[0096] Next, a plurality of first conductive structures are formed on the substrate. The first conductive structures are located on the source-drain structure 202 on at least one side of the gate structure 240. For details on the process of forming the first conductive structures, please refer to Figures 7 to 9 .

[0097] Please refer to Figure 7 A first mask structure 300 is formed on the surface of the first protection structure 250 and the first dielectric structure 220, and the first mask structure 300 exposes the first dielectric structure 220 between adjacent gate structures 240; the first mask structure 300 is used as a mask to etch the first dielectric structure 220 until the substrate surface is exposed, and a first conductive opening 211 is formed in the first dielectric structure 220.

[0098] The first conductive opening 211 provides space for subsequently forming a first conductive structure.

[0099] In this embodiment, before etching the first dielectric structure 220 , the initial second dielectric structure 260 is etched with the first mask structure 300 until the surface of the first dielectric structure 220 is exposed to form a second dielectric structure 261 .

[0100] It should be noted that, in this embodiment, since the initial second dielectric structure 260 is formed before forming the first mask structure 300 , the first mask structure 300 exposing the first dielectric structure 220 between adjacent gate structures 240 means that the first mask structure 300 exposes the initial second dielectric structure 260 between adjacent gate structures 240 .

[0101] In the present embodiment, during the etching process of forming the first conductive opening 211, the initial second spacer 230 is used as an etching stop layer, so the first conductive opening 211 can be formed by using the initial second spacer 230 in a self-aligned contact (SAC) process. Specifically, since the first mask structure 300 exposes the initial second dielectric structure 260 between adjacent gate structures 240, that is, the first mask structure 300 exposes the initial second dielectric structure 260 on the top of the initial second spacer 230, during the process of forming the first conductive opening 211, the initial second spacer 230 also defines the shape of the first conductive opening 211 together with the first mask structure 300.

[0102] In this embodiment, as the initial second dielectric structure 260 and the first dielectric structure 220 are etched, the initial second sidewall 230 of the second region II is exposed and removed by consumption, thereby forming a second sidewall 231 on the sidewalls of the gate structure 240 and the first protection structure 250, and the top surface of the second sidewall 231 is also located between the top surface of the gate structure 240 and the top surface of the first protection structure 250.

[0103] On the one hand, the top surface of the second sidewall 231 is lower than the top surface of the first protection structure 250, so it can provide space for the subsequent formation of the first sidewall. On the other hand, the top surface of the second sidewall 231 is higher than the top surface of the gate structure 240, so on the basis of the spacing of the gate structure 240 and the first conductive structure formed subsequently, the margin of the loss of the second sidewall 231 is increased, so that when etching the first protection structure 250 and the second protection structure formed subsequently, the risk of the sidewall surface of the gate electrode layer 241 and the sidewall surface of the first conductive structure being exposed is further reduced, the risk of the gate electrode layer 241 and the first conductive structure being short-circuited is reduced, and the reliability of the semiconductor structure is improved.

[0104] Furthermore, since the second side wall 231 is formed before the first conductive structure is subsequently formed, the first side wall and the second side wall 231 are formed separately, thereby improving the independence of the processes for forming the first side wall and the second side wall 231 and the degree of freedom in selecting the materials of the first side wall and the second side wall 231. Furthermore, while reducing the risk of short circuit between the gate electrode layer 241 and the first conductive structure through the first side wall, the material of the second side wall 231 that has less impact on the electrical properties of the gate structure 240 can be selected, thereby improving the performance of the semiconductor structure.

[0105] In this embodiment, the second spacer 231 covers the gate structure 240 and the sidewall surface of the first protection structure 250 in the first region I, and exposes the sidewall surface of the first protection structure 250 in the second region II.

[0106] In this embodiment, the process of etching the first dielectric structure 220 includes a dry etching process or a wet etching process.

[0107] In this embodiment, the process parameters for etching the first dielectric structure 220 include: a pressure range of 5 mTorr to 200 mTorr; a bias power range of 500 W to 2000 W; and a gas including C 4 F 6 , C 5 F 8 and CH 2 F 2Thus, by adjusting the process parameters, the second sidewall spacer 231 can be formed while the first conductive opening 211 is formed, that is, the second sidewall spacer 231 covers the gate structure 240 and the sidewall surface of the first protection structure 250 in the first region I, and exposes the sidewall surface of the first protection structure 250 in the second region II.

[0108] Please refer to Figure 8 , a first conductive material layer 270 is formed in the first conductive opening 211 .

[0109] The method for forming the first conductive material layer 270 includes: forming an initial first conductive material layer (not shown) in the first conductive opening 211 and on the surface of the second dielectric structure 261 ; and planarizing the initial first conductive material layer until the surface of the second dielectric structure 261 is exposed.

[0110] In this embodiment, the process of forming the initial first conductive material layer includes a metal electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0111] In this embodiment, the process of planarizing the initial first conductive material layer includes an etch-back process or a chemical mechanical polishing process.

[0112] Please refer to Fig. 9 , the first conductive material layer 270 is etched until a portion of the sidewall surface of the first protection structure 250 is exposed, and a plurality of first conductive structures 271 are formed on the substrate.

[0113] The first conductive structure 271 is located on the source-drain structure 202 on at least one side of the gate structure 240. The first conductive structure 271 is electrically connected to the source-drain structure 202.

[0114] Specifically, in this embodiment, the first conductive structure 271 is also located on the side wall surface of the first protection structure 250 in the first region I, and the first conductive structure 271 exposes the side wall surface of the first protection structure 250 in the second region II.

[0115] In this embodiment, the process of etching the first conductive material layer 270 includes at least one of a dry etching process and a wet etching process.

[0116] Please refer to Fig.10 After forming the first conductive structure 271 , the sidewall of the first protection structure 250 in the second region II is etched to form a first groove 251 in the first protection structure 250 in the second region II.

[0117] The first groove 251 provides space for subsequently forming a first sidewall, that is, the subsequently formed first sidewall is also located in the first groove 251 .

[0118] On the one hand, since the first groove 251 is formed in the first protection structure 250 of the second region II, and the first sidewall is also located in the first groove 251, the width of the first sidewall is increased, thereby improving the blocking ability of the first sidewall when etching the first protection structure 250 and the second protection structure formed subsequently, better reducing the risk of short circuit between the gate electrode layer 241 and the first conductive structure 271, and improving the reliability of the semiconductor structure. On the other hand, by etching the sidewall of the first protection structure 250 of the second region II, it is beneficial to increase the verticality of the sidewall surface of the first protection structure 250 of the second region II, thereby making the thickness of the first sidewall more uniform, so as to further improve the blocking ability of the first sidewall when etching the first protection structure 250 and the second protection structure subsequently, so as to better reduce the risk of short circuit between the gate electrode layer 241 and the first conductive structure 271, and improve the reliability of the semiconductor structure.

[0119] In this embodiment, the angle between the sidewall surface of the first protection structure 250 in the second region II and the normal line along the substrate surface is within 4 degrees.

[0120] By making the angle between the side wall surface of the first protection structure 250 in the second region II and the normal along the substrate surface within 4 degrees, the verticality of the side wall surface of the first protection structure 250 in the second region II is ensured. Therefore, the side wall surface of the first side wall located in the first groove 251 can be more vertical, so that the thickness of the first side wall can be more uniform. Therefore, when etching the first protection structure 250 and the second protection structure, the blocking ability of the first side wall is further improved, so as to better reduce the risk of short circuit between the gate electrode layer 241 and the first conductive structure 271, and improve the reliability of the semiconductor structure.

[0121] In this embodiment, the process of etching the sidewall of the first protection structure 250 in the second region II includes an anisotropic etching process, which refers to an etching process that can etch the first protection structure 250 material exposed in the horizontal direction and retain the first protection structure 250 material exposed in the vertical direction.

[0122] In this embodiment, in the process of etching the sidewall of the first protection structure 250 of the second region II, the etching selectivity ratio of the first protection structure 250 to the second dielectric structure 261 is in a range of 2:1 to 5:1.

[0123] Therefore, the second dielectric structure 261 on the top surface of the first protection structure 250 can prevent the anisotropic etching process from etching the top surface of the first protection structure 250 , and at the same time, increase the verticality of the sidewall surface of the first protection structure 250 in the exposed second region II.

[0124] The process parameters of the anisotropic etching process include: a pressure range of 50 mTorr to 500 mTorr; a source power range of 500 W to 2000 W; and the gases used include: CF 4 , CH 3 F. CHF 3 and CH 2 F 2 .

[0125] Next, after forming the first conductive structure 271, a second protective structure and a first sidewall are formed, wherein the second protective structure is located on the top surface of the first conductive structure 250, and the first sidewall is located between the first protective structure 250 and the second protective structure. For details on the process of forming the first sidewall and the second protective structure, please refer to Figures 11 to 14 .

[0126] Please refer to Fig.11 , a first spacer film 280 is formed on the surfaces of the first conductive structure 271 , the second dielectric structure 261 and the first protection structure 250 .

[0127] The first spacer film 280 provides material for forming a first spacer.

[0128] In the present embodiment, the process of forming the first spacer film 280 includes a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0129] Please refer to Fig.12 , an anisotropic etching process is used to etch the first spacer film 280 until the surface of the first conductive structure 271 is exposed to form an initial first spacer 281 .

[0130] Specifically, in this embodiment, the first spacer film 280 in the horizontal direction is removed through the anisotropic etching process, and the first spacer film 280 in the vertical direction is retained.

[0131] In the anisotropic etching process, the first protection structure 250 can be protected by the second dielectric structure 261 , thereby preventing the anisotropic etching process from damaging the first protection structure 250 .

[0132] The anisotropic etching process includes a dry etching process, such as a plasma etching process.

[0133] In this embodiment, along the normal direction of the surface of the first protection structure 250 , the thickness of the first spacer film 280 ranges from 10 angstroms to 50 angstroms.

[0134] If the first spacer film 280 is too thick, it will not only lead to material waste, but also lead to too small spacing between the sidewalls of the first spacer film 280, which is not conducive to removing the first spacer film 280 on the top surface of the first conductive structure 271 in the subsequent anisotropic etching process of forming the initial first spacer. If the first spacer film 280 is too thin, it will not only easily lead to the first spacer formed to expose the second spacer 231 and the top surface of the gate spacer, but also easily lead to the weak blocking ability of the first spacer even if the first spacer formed does not expose the second spacer 231 and the top surface of the gate spacer. When the first protection structure 250 or the second protection structure is subsequently etched, it will be quickly worn out to expose the second spacer 231 and the top surface of the gate spacer, which is not conducive to protecting the second spacer 231 and the gate spacer. Therefore, when a suitable thickness of the first sidewall film 280 is selected, that is, the thickness of the first sidewall film 280 ranges from 10 angstroms to 50 angstroms, on the one hand, material waste is reduced and the process difficulty of removing the first sidewall film 280 on the top surface of the first conductive structure 271 is reduced; on the other hand, when the first protective structure 250 or the second protective structure is subsequently etched, the second sidewall 231 and the gate sidewall can be better protected, and the etching of the structure between the gate electrode layer 241 at the bottom of the first sidewall and the first conductive structure 271 can be blocked, thereby reducing the risk of exposure of the sidewall surface of the gate electrode layer and the sidewall surface of the first conductive structure, reducing the risk of short circuit between the gate electrode layer and the first conductive structure, and improving the reliability of the semiconductor structure.

[0135] Please refer to Fig.13 A second protection structure material layer 290 is formed on the surfaces of the initial first sidewall 281 , the first conductive structure 271 and the second dielectric structure 261 .

[0136] The second protection structure material layer 290 provides material for forming a second protection structure.

[0137] In this embodiment, the material of the second protection structure material layer 290 is the same as that of the first protection structure 250 . Accordingly, the material of the second protection structure is the same as that of the first protection structure 250 .

[0138] Since the material of the second protective structure is the same as that of the first protective structure 250, the consistency of the material properties of the second protective structure and the first protective structure 250 is improved. Therefore, on the one hand, the process can be simplified, and on the other hand, the types of materials that need to be selected are reduced, making it easier to select conventional materials as the materials of the first protective structure 250 and the second protective structure, thereby improving the controllability of electrical properties.

[0139] In this embodiment, the material of the second protection structure is silicon nitride.

[0140] In other embodiments, the material of the second protection structure includes silicon oxide.

[0141] In this embodiment, the process of forming the second protection structure material layer 290 includes a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0142] In this embodiment, the first protection structure 250 and the second protection structure material layer 290 made of the same material can be separated by the second dielectric structure 261 and the initial first sidewall 281, thereby reducing the impact of the process of forming the second protection structure on the first protection structure 250 and improving the performance and reliability of the semiconductor structure.

[0143] In another embodiment, the material of the second protective structure material layer is different from the material of the first protective structure. Accordingly, the material of the second protective structure is different from the material of the first protective structure. And, the second dielectric structure is not formed. The method for forming the first sidewall comprises: forming a first sidewall film on the surface of the first conductive structure and the first protective structure; etching the first sidewall film using an anisotropic etching process to remove the first sidewall film in the horizontal direction and retain the first sidewall film in the vertical direction until the top surface of the first protective structure and the surface of the first conductive structure are exposed. The method for forming the second protective structure comprises: forming a second protective structure material layer on the surface of the first protective structure, the first sidewall and the first conductive structure; planarizing the second protective structure material layer until the surface of the first protective structure is exposed. Since the material of the second protective structure is different from the material of the first protective structure, in the process of planarizing the second protective structure material layer, the selectivity can be increased, and the influence of the planarization process on the first protective structure can be reduced without forming the second dielectric structure, thereby reducing the process steps, improving the efficiency of forming the semiconductor structure, and improving the performance and reliability of the semiconductor structure.

[0144] Please refer to Fig.14 , planarizing the second protection structure material layer 290 , the initial first sidewall 281 and the second dielectric structure 261 until the surface of the first protection structure 250 is exposed, thereby forming a first sidewall 282 and a second protection structure 291 .

[0145] The second protection structure 291 is located on the top surface of the first conductive structure 250 , and the first sidewall 282 is located between the first protection structure 250 and the second protection structure 291 .

[0146] Since the formed first protection structure 250 is located on the top surface of the gate electrode layer 241, the formed second protection structure 291 is located on the top surface of the first conductive structure 271, and the formed first sidewall 282 is located between the first protection structure 250 and the second protection structure 291, the material of the first sidewall 282 can be selected so that in the subsequent process of etching the first protection structure 250, the first protection structure 250 and the first sidewall 282 can be etched more selectively, and in the subsequent process of etching the second protection structure 291, the second protection structure 291 and the first sidewall 282 can be etched more selectively. Therefore, when etching the first protection structure 250 and the second protection structure 291, the first sidewall 282 can be used to block the etching of the structure between the gate electrode layer 241 and the first conductive structure 271 at the bottom of the first sidewall 282, thereby reducing the risk of exposing the sidewall surface of the gate electrode layer 241 and the sidewall surface of the first conductive structure 271, reducing the risk of short circuit between the gate electrode layer 241 and the first conductive structure 271, and improving the reliability of the semiconductor structure.

[0147] In this embodiment, the first sidewall spacer 282 is also located on the top surface of the second sidewall spacer 231. Therefore, the width of the first sidewall spacer 282 is increased, thereby improving the blocking ability of the first sidewall spacer 282 during the subsequent etching of the first protection structure 250 and the second protection structure 291, better reducing the risk of short circuit between the gate electrode layer 241 and the first conductive structure 271, and improving the reliability of the semiconductor structure.

[0148] In this embodiment, the material of the first sidewall 282 is different from the material of the first protection structure 250 .

[0149] In this embodiment, the material of the first spacer 282 includes silicon oxide.

[0150] In other embodiments, the material of the first spacer includes silicon nitride.

[0151] Specifically, in this embodiment, the second dielectric structure 261 is removed through the planarization process.

[0152] Please refer to Fig.15 A third dielectric material layer 310 is formed on the surfaces of the first sidewall 282 , the first protection structure 250 and the second protection structure 291 .

[0153] The third dielectric material layer 310 provides material for forming a third dielectric structure. The third dielectric structure serves as a mask for etching the first protection structure 250 and the second protection structure 291 when the first conductive opening and the second conductive opening are subsequently formed.

[0154] In this embodiment, the process of forming the third dielectric material layer 310 includes a spin coating process, an oxidation process or a deposition process. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0155] In this embodiment, the material of the third dielectric material layer 310 includes silicon oxide.

[0156] In other embodiments, the material of the third dielectric material layer includes silicon nitride.

[0157] Please refer to Fig.16 , etching the third dielectric material layer 310 to form a third dielectric structure 311, wherein the third dielectric structure 311 has a second mask opening 312 and a third mask opening 313, wherein the second mask opening 312 exposes the top surface of the first protection structure 250, and the third mask opening 313 exposes the top surface of the second protection structure 291.

[0158] In this embodiment, the method for forming the second mask opening 312 includes: forming a second patterned layer (not shown) on the surface of the third dielectric material layer 310, wherein the second patterned layer exposes a portion of the surface of the third dielectric material layer 310; using the second patterned layer as a mask, etching the third dielectric material layer 310 until the top surface of the first protective structure 250 is exposed.

[0159] In this embodiment, after the second mask opening 312 is formed, the second patterned layer is removed.

[0160] In this embodiment, the method for forming the third mask opening 313 includes: forming a third patterned layer (not shown) on the surface of the third dielectric material layer 310, wherein the third patterned layer exposes a portion of the surface of the third dielectric material layer 310; using the third patterned layer as a mask, etching the third dielectric material layer 310 until the top surface of the second protective structure 291 is exposed.

[0161] In this embodiment, after the third mask opening 313 is formed, the third patterned layer is removed.

[0162] In this embodiment, since the second mask opening 312 and the third mask opening 313 are respectively formed through two patterning layers (the second patterning layer and the third patterning layer), the number of patterns in the second patterning layer and the third patterning layer and the spacing between adjacent patterns are reduced, which is beneficial to improving defects such as pattern end connection caused by optical proximity effect and improving pattern accuracy.

[0163] In this embodiment, the second mask opening 312 exposes the first side wall 282, and the third mask opening 313 exposes the first side wall 282, thereby increasing the width of the second mask opening 312 and the third mask opening 313, increasing the process window for patterning the third dielectric material layer 310, and reducing the process difficulty of patterning the third dielectric material layer 310.

[0164] At the same time, in the subsequent etching process of forming the second conductive opening and the third conductive opening, the first conductive opening 211 can be formed by a self-aligned via (SAV) process through the first sidewall 282. Specifically, since the first sidewall 282 is located between the first protection structure 250 and the second protection structure 291, when the second conductive opening and the third conductive opening are subsequently formed, the shapes of the second conductive opening and the third conductive opening can be jointly defined by the third dielectric structure 311 and the first sidewall 282.

[0165] In other embodiments, the method for forming the second mask opening and the third mask opening includes: forming a fourth patterned layer on the surface of the third dielectric material layer, wherein the fourth patterned layer exposes a portion of the surface of the third dielectric material layer; using the fourth patterned layer as a mask, etching the third dielectric material layer until the top surface of the second protection structure and the top surface of the first protection structure are exposed. Thus, the second mask opening and the third mask opening are formed simultaneously through one patterned layer, which simplifies the process flow of forming the semiconductor structure, improves efficiency, reduces the number of patterned layers, and reduces the manufacturing cost of forming the semiconductor structure.

[0166] Please refer to Fig.17 , using the third dielectric structure 311 as a mask, the first protection structure 250 and the second protection structure 291 are etched simultaneously, a third conductive opening 321 is formed in the first protection structure 250, the bottom of the third conductive opening 321 exposes at least a portion of the surface of the gate electrode layer 341, and a second conductive opening 322 is formed in the second protection structure 391, the bottom of the second conductive opening 322 exposes at least a portion of the surface of the first conductive structure 271.

[0167] Since the first protection structure 250 and the second protection structure 291 are etched simultaneously, the efficiency of forming the semiconductor structure can be improved.

[0168] The process of etching the first protection structure 250 and the second protection structure 291 includes a dry etching process or a wet etching process.

[0169] Please refer to Fig.18 , a second conductive structure 332 is formed in the second conductive opening 322 , and a third conductive structure 331 is formed in the third conductive opening 321 .

[0170] In this embodiment, the method for forming the second conductive structure 332 and the third conductive structure 331 includes: forming an interconnect material layer (not shown) in the second conductive opening 322, in the third conductive opening 321, and on the surface of the third dielectric structure 311; and planarizing the interconnect material layer until the surface of the third conductive structure 331 is exposed.

[0171] In other embodiments, the method of forming the second conductive structure and the third conductive structure includes: planarizing the interconnect material layer until the height of the third conductive structure 331 in a direction perpendicular to the substrate surface is reduced, or until the surface of the first protection structure 250 is exposed.

[0172] During the process of planarizing the interconnect material layer, the third conductive structure 331 can also protect the unetched first protection structure 250 and the second protection structure 291, and the first side wall 231, reduce the damage of the planarization process to the first protection structure 250 and the second protection structure 291, and the first side wall 231, and improve the performance and reliability of the semiconductor structure.

[0173] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.14 , including: a substrate; a plurality of gate structures 240 located on the substrate, the gate structure 240 including a gate electrode layer 241; a plurality of source-drain structures 202 located in the substrate on both sides of the gate structure 240; a first protection structure 250 located on the top surface of the gate electrode layer 241; a first conductive structure 271 located on the substrate, the first conductive structure 271 is also located on the source-drain structure 202 on at least one side of the gate structure 240, and the first conductive structure 271 is electrically connected to the source-drain structure 202; a second protection structure 291 located on the top surface of the first conductive structure 271; and a first sidewall 282 located between the first protection structure 250 and the second protection structure 291.

[0174] In this embodiment, the base includes a substrate 200 and a plurality of fin structures 201 that are separated from each other and located on the substrate 200 .

[0175] Specifically, in this embodiment, the source-drain structure 202 is located in the fin structure 201 on both sides of the dummy gate structure 210 .

[0176] The material of the substrate 200 includes semiconductor material.

[0177] In this embodiment, the material of the substrate 200 is silicon.

[0178] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multinary semiconductor materials composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, multinary semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0179] In this embodiment, the semiconductor structure further includes: a base dielectric layer (not shown) located on the surface of the substrate 200 , and the base dielectric layer is also located on a portion of the sidewall surface of the fin structure.

[0180] In this embodiment, the gate structure 240 also includes: a gate dielectric layer (not shown) located on the sidewalls and bottom of the gate opening and a work function layer (not shown) located on the surface of the gate dielectric layer, and the gate electrode layer 241 is located on the surface of the work function layer.

[0181] The material of the gate dielectric layer includes a high dielectric constant material (dielectric constant greater than 3.9), which includes hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0182] The material of the gate electrode layer includes a metal material, for example, one or a combination of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0183] The material of the work function layer includes titanium nitride, tantalum nitride or titanium aluminum.

[0184] In this embodiment, the first protection structure 250 includes a first region I and a second region II located on the first region I.

[0185] In this embodiment, the first protection structure 250 is also located on the top surfaces of the gate dielectric layer and the work function layer.

[0186] In this embodiment, the first protection structure 250 of the second region II has a first groove 251 (eg Fig.10 As shown), and the first side wall 291 is also located in the first groove 251.

[0187] In this embodiment, the first conductive structure 271 is also located on the sidewall surface of the first protection structure 250 in the first region I.

[0188] The semiconductor structure also includes: a second side wall 231 located between the gate structure 240 and the first conductive structure 271, and between a portion of the side wall surface of the first protective structure 250 and the first conductive structure 271, the top surface of the second side wall 231 is also located between the top surface of the gate structure 240 and the top surface of the first protective structure 250, and the first side wall 291 is also located on the top surface of the second side wall 231.

[0189] In this embodiment, the angle between the sidewall surface of the first protection structure 250 in the second region II and the normal line along the substrate surface is within 4 degrees.

[0190] In this embodiment, the material of the first protection structure 250 is the same as the material of the second protection structure 291 .

[0191] In another embodiment, the material of the second protection structure is different from the material of the first protection structure.

[0192] In this embodiment, the material of the first protection structure 250 is silicon nitride.

[0193] In other embodiments, the material of the first protection structure includes silicon oxide.

[0194] In this embodiment, the material of the second protection structure 291 is silicon nitride.

[0195] In other embodiments, the material of the second protection structure includes silicon oxide.

[0196] In this embodiment, the material of the first sidewall 282 is different from the material of the first protection structure 250 .

[0197] In this embodiment, the material of the first spacer 282 includes silicon oxide.

[0198] In other embodiments, the material of the first spacer includes silicon nitride.

[0199] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A plurality of gate structures located on the substrate, wherein the gate structures include a gate electrode layer; A plurality of source-drain structures located in the substrate on both sides of the gate structure; A first protection structure located on the top surface of the gate electrode layer; a first conductive structure located on the substrate, wherein the first conductive structure is also located on a source-drain structure on at least one side of the gate structure; a second protection structure located on a top surface of the first conductive structure; a first side wall located between the first protective structure and the second protective structure; The sidewalls of the gate structure and the first protection structure also form a second sidewall, the top surface of the second sidewall is located between the top surface of the gate structure and the top surface of the first protection structure; the first sidewall is also located on the top surface of the second sidewall.

2. The semiconductor structure according to claim 1, wherein: The first protection structure includes a first region and a second region located on the first region, and the first conductive structure is also located on a sidewall surface of the first protection structure in the first region.

3. The semiconductor structure according to claim 2, wherein: The first protection structure of the second area has a first groove therein, and the first sidewall is also located in the first groove.

4. The semiconductor structure according to claim 3, characterized in that An angle between a sidewall surface of the first protection structure in the second region and a normal line along the substrate surface is within 4 degrees.

5. The semiconductor structure according to claim 1, wherein: The material of the first protection structure includes silicon nitride or silicon oxide; the material of the second protection structure includes silicon nitride or silicon oxide.

6. The semiconductor structure according to claim 1, wherein: The material of the first protection structure is the same as that of the second protection structure.

7. The semiconductor structure according to claim 1, wherein: The material of the first spacer includes silicon nitride or silicon oxide.

8. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; Forming a plurality of source-drain structures, a plurality of gate structures and a first protection structure, wherein the source-drain structures are located in the substrate on both sides of the gate structure, the gate structure is located on the substrate, the gate structure includes a gate electrode layer, and the first protection structure is located on the top surface of the gate electrode layer; forming a plurality of first conductive structures on the substrate, wherein the first conductive structures are located on the source-drain structures on at least one side of the gate structure; After forming the first conductive structure, forming a second protective structure and a first sidewall, wherein the second protective structure is located on the top surface of the first conductive structure, and the first sidewall is located between the first protective structure and the second protective structure; Before forming the first conductive structure, a second side wall is formed on the side walls of the gate structure and the first protection structure, the top surface of the second side wall is also located between the top surface of the gate structure and the top surface of the first protection structure, and the first side wall is also located on the top surface of the second side wall.

9. The method for forming a semiconductor structure according to claim 8, wherein: The first protection structure includes a first region and a second region located on the first region, and the first conductive structure is also located on a side wall surface of the first protection structure in the first region.

10. The method for forming a semiconductor structure according to claim 9, wherein: Also includes: After forming the first conductive structure and before forming the second protection structure and the first sidewall, the sidewall of the first protection structure in the second area is etched to form a first groove in the first protection structure in the second area, and the first sidewall is also located in the first groove.

11. The method for forming a semiconductor structure according to claim 10, wherein: An angle between a sidewall surface of the first protection structure in the second region and a normal line along the substrate surface is within 4 degrees.

12. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: Before forming the first conductive structure, a first dielectric structure is formed on the surface of the substrate, and the first dielectric structure is also located on the sidewall surfaces of the gate structure and the first protection structure.

13. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the first conductive structure includes: forming a first mask structure on the surface of the first protective structure and the first dielectric structure, the first mask structure exposing the first dielectric structure between adjacent gate structures; using the first mask structure as a mask, etching the first dielectric structure until the surface of the source-drain structure is exposed, and forming a first conductive opening in the first dielectric structure; forming a first conductive material layer in the first conductive opening; etching the first conductive material layer until a portion of the sidewall surface of the first protective structure is exposed, so as to form the first conductive structure.

14. The method for forming a semiconductor structure according to claim 13, wherein: Also includes: Before forming the first mask structure, an initial second dielectric structure is formed on the surface of the first dielectric structure and the surface of the first protective structure; Before etching the first dielectric structure, the initial second dielectric structure is etched with the first mask structure until the surface of the first dielectric structure is exposed to form a first sidewall and a second dielectric structure.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the first sidewall and the second protection structure includes: forming a first sidewall film on the surfaces of the first conductive structure, the second dielectric structure and the first protection structure; etching the first sidewall film using an anisotropic etching process until the surface of the first conductive structure is exposed to form an initial first sidewall; forming a second protection structure material layer on the surfaces of the initial first sidewall, the first conductive structure and the second dielectric structure; and flattening the second protection structure material layer, the initial first sidewall and the second dielectric structure until the surface of the first protection structure is exposed to form a second protection structure.

16. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the first sidewall includes: forming a first sidewall film on the surfaces of the first conductive structure and the first protective structure; etching the first sidewall film using an anisotropic etching process until the top surface of the first protective structure and the surface of the first conductive structure are exposed.

17. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the second protection structure includes: forming a second protection structure material layer on the first protection structure, the first sidewall and the first conductive structure surface; and planarizing the second protection structure material layer until the first protection structure surface is exposed.

18. The method for forming a semiconductor structure according to claim 15 or 16, wherein: In the normal direction along the surface of the first protection structure, the thickness of the first sidewall film ranges from 10 angstroms to 50 angstroms.

19. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: After forming the first sidewall and the second protection structure, forming a second conductive opening in the second protection structure, wherein the bottom of the second conductive opening exposes at least a portion of the surface of the first conductive structure; A second conductive structure is formed in the second conductive opening.

20. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: After forming the first sidewall spacer and the second protection structure, forming a third conductive opening in the first protection structure, wherein the bottom of the third conductive opening exposes at least a portion of the surface of the gate electrode layer; A third conductive structure is formed in the third conductive opening.

21. The method for forming a semiconductor structure according to claim 8, wherein: The first protection structure and the second protection structure are made of the same material.

22. The method for forming a semiconductor structure according to claim 8, wherein: The base includes a substrate and a plurality of fin structures separated from each other and located on the substrate, and the gate structure spans across the plurality of fin structures.

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