Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate; forming a plurality of source-drain structures in the substrate, and forming a plurality of gate structures, a first protection structure located on the top surface of the gate structure, a first conductive structure located between adjacent gate structures, a second protection structure located on the top surface of the first conductive structure, and an initial first sidewall located between the gate structure and the first conductive structure on the substrate, wherein the initial first sidewall is also located between the first protection structure and the second protection structure, the source-drain structure is located in the substrate on both sides of the gate structure, and the first conductive structure is located on the source-drain structure; etching the initial first sidewall to form a first sidewall and an opening, wherein the opening exposes the sidewall surface of the first protection structure, the sidewall surface of the second protection structure, and the top surface of the first sidewall; and forming a second sidewall in the opening. Thus, the reliability of the formed semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. As the most basic semiconductor device, the device is currently being widely used.

[0003] Generally, in the process of manufacturing semiconductor devices, a plug (Diffusion Contact) electrically connected to the source-drain doping layer is formed in the active region, and a plug (Gate Contact) electrically connected to the gate is formed outside the active region to achieve electrical connection between the semiconductor device and the external circuit. At the same time, the distance between the plug electrically connected to the source-drain doping layer and the plug electrically connected to the gate is increased to reduce the risk of short circuit. On this basis, a method for forming a plug electrically connected to the gate in the active region is proposed. By forming the plug electrically connected to the gate and the plug electrically connected to the source-drain doping layer in the active region, the area occupied by the semiconductor device can be reduced, so that the integration of the semiconductor device can be improved.

[0004] However, the reliability of the semiconductor structure formed by the prior art needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the reliability of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a plurality of gate structures located on the substrate; a plurality of source-drain structures located in the substrate on both sides of the gate structure; a first protection structure located on the top surface of the gate structure; a first conductive structure located between adjacent gate structures, and the first conductive structure is located on the source-drain structure; a second protection structure located on the top surface of the first conductive structure; a first side wall located between the gate structure and the first conductive structure; a second side wall located on the top surface of the first side wall, and the second side wall is also located between the first protection structure and the second protection structure.

[0007] Optionally, the width of the top of the second side wall is greater than the width of the first side wall.

[0008] Optionally, on a plane perpendicular to an extension direction of the gate structure, a projection shape of the second sidewall spacer is a trapezoid with a top width greater than a bottom width.

[0009] Optionally, on a plane perpendicular to an extension direction of the gate structure, a projection shape of the second sidewall spacer is a rectangle.

[0010] Optionally, in the trapezoid, a distance between a top edge of the first protection structure and a sidewall surface of an adjacent first sidewall spacer is 1 angstrom to 30 angstroms.

[0011] Optionally, in the trapezoid, a distance between a top edge of the second protection structure and a sidewall surface of an adjacent first sidewall spacer is 1 angstrom to 30 angstroms.

[0012] Correspondingly, the technical solution of the present invention also provides a method for forming the above-mentioned semiconductor structure, including: providing a substrate; forming a plurality of source-drain structures in the substrate, and forming a plurality of gate structures, a first protection structure located on the top surface of the gate structure, a first conductive structure located between adjacent gate structures, a second protection structure located on the top surface of the first conductive structure, and an initial first side wall located between the gate structure and the first conductive structure on the substrate, the initial first side wall is also located between the first protection structure and the second protection structure, the source-drain structure is located in the substrate on both sides of the gate structure, and the first conductive structure is located on the source-drain structure; etching the initial first side wall to form a first side wall and an opening, the opening exposing the side wall surface of the first protection structure, the side wall surface of the second protection structure and the top surface of the first side wall; forming a second side wall in the opening.

[0013] Optionally, the maximum width of the second side wall is greater than the width of the first side wall.

[0014] Optionally, the method for forming the opening further includes: etching at least one of the sidewalls of the first protection structure and the sidewalls of the second protection structure while or after etching the initial first sidewall spacer.

[0015] Optionally, the method further includes: before forming the first sidewall spacer, forming a first dielectric layer on the surface of the substrate, wherein the first dielectric layer is also located on the sidewall surfaces of the gate structure, the first protection structure, the first conductive structure and the second protection structure.

[0016] Optionally, the method further includes: after forming the second sidewall, etching at least a portion of the first protection structure to form a first conductive opening in the first dielectric layer, wherein the bottom of the first conductive opening exposes the top surface of the gate structure; and forming a second conductive structure in the first conductive opening.

[0017] Optionally, the method further includes: after forming the second sidewall, etching at least a portion of the second protective structure to form a second conductive opening in the first dielectric layer, wherein the bottom of the second conductive opening exposes the top surface of the first conductive structure; and forming a third conductive structure in the second conductive opening.

[0018] Optionally, the method further includes: after forming the second sidewall spacer, forming a second dielectric layer on the first dielectric layer, the first protective structure, the second protective structure and the surface of the second sidewall spacer.

[0019] Optionally, the material of the first protection structure includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride and aluminum oxide.

[0020] Optionally, the material of the second protection structure includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride and aluminum oxide.

[0021] Optionally, the material of the first spacer includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxycarbide, silicon carbide, a low dielectric constant medium and an air gap.

[0022] Optionally, the material of the second spacer includes one or more combinations of silicon carbide nitride, silicon oxycarbide, silicon carbide, aluminum nitride and aluminum oxide.

[0023] Optionally, the material of the gate structure includes metal or polysilicon.

[0024] Optionally, the base includes a substrate and a plurality of fin structures located on the substrate, and the gate structure spans across the fin structures.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] In the method for forming a semiconductor structure provided by the technical solution of the present invention, an initial first sidewall is etched to form a first sidewall and an opening, wherein the opening exposes the sidewall surface of the first protective structure, the sidewall surface of the second protective structure and the top surface of the first sidewall, and a second sidewall is formed in the opening. On the one hand, when etching the first protective structure and the second protective structure, the first sidewall can be protected by the second sidewall, thereby reducing the loss of the first sidewall and the possibility of exposing the sidewall surface of the first conductive structure or the gate structure, thereby reducing the risk of short circuit between the gate structure and the first conductive structure and improving the reliability of the semiconductor structure. On the other hand, since the first sidewall and the second sidewall are formed separately, the material selection of the first sidewall and the second sidewall is freer, and the first sidewall and the second sidewall can be made of different materials. Thus, by selecting the material of the second side wall, when etching the first protection structure and the second protection structure, the etching selectivity ratio between the first protection structure and the second side wall, and between the second protection structure and the second side wall can be increased respectively, so as to reduce the loss of the second side wall and increase the ability of the second side wall to block the etching process, so that the second side wall can better protect the first side wall and reduce the loss of the first side wall, thereby reducing the risk of short circuit between the gate structure and the first conductive structure and improving the reliability of the semiconductor structure.

[0027] Furthermore, since the width of the top of the second side wall is greater than the width of the first side wall, when etching the first protection structure and the second protection structure, the margin of the second side wall that can be consumed is increased, thereby improving the blocking ability of the second side wall to the etching process, so that the first side wall is better protected, further reducing the risk of short circuit between the gate structure and the first conductive structure, and improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 to Figure 2 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure;

[0029] Figure 3 is a schematic cross-sectional structural diagram of a step in another method for forming a semiconductor structure;

[0030] Figures 4 to 14 is a schematic cross-sectional structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention;

[0031] Fig.15 It is a schematic cross-sectional structural diagram of a step of a method for forming a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, the reliability of semiconductor structures still needs to be improved. The reasons why the reliability of semiconductor structures is poor are described in detail below with reference to the accompanying drawings.

[0033] It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

[0034] Figure 1 to Figure 2 The invention is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure.

[0035] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 includes an active area A, and a plurality of mutually separate fins (not shown) are formed on the substrate 100; a plurality of gate structures 110 spanning the fins, source-drain doped regions 101 located on both sides of the gate structure 110, a gate protection structure 111 located on the top surface of the gate structure 110, an interconnection structure 120 located on the surface of the source-drain doped regions 101, an etch stop layer 130 located between the sidewalls of the gate structure 110 and the interconnection structure 120, a conductive protection structure 121 located on the top surface of the interconnection structure 120 and the top surface of the etch stop layer 130, and a dielectric structure (not shown) surrounding the gate structure 110 are formed on the substrate 100.

[0036] Please refer to Figure 2, the gate protection structure 111 on a portion of the active area A is removed to form a first plug opening (not shown), and the gate structure 110 is exposed at the bottom of the first plug opening; the conductive protection structure 121 on a portion of the active area A is removed to form a second plug opening 141, and the interconnection structure 120 is exposed at the bottom of the second plug opening 141; a first plug (not shown) is formed in the first plug opening, and a second plug (not shown) is formed in the second plug opening 141.

[0037] exist Figure 1 to Figure 2 In the illustrated embodiment, by increasing the width of the conductive protection structure 121 (located not only on the top surface of the interconnect structure 120, but also on the top surface of the etch stop layer 130), when etching the gate protection structure 111 to form the first plug opening, the etching process can better block the loss of the etch stop layer 130, thereby reducing the risk of short circuit between the first plug and the interconnect structure 120.

[0038] However, on the one hand, in order to increase the width of the conductive protection structure 121, the etch stop layer 130 has less margin for consumption when etching the conductive protection structure 121. Therefore, when etching the conductive protection structure 121, the etch stop layer 130 is easily consumed to expose the sidewall surface of the gate structure 110 (such as Figure 2 As shown in region B, the second plug and the gate structure 110 are short-circuited, that is, the interconnection structure 120 and the gate structure 110 are short-circuited, resulting in poor reliability of the semiconductor structure.

[0039] In order to solve the above problems, Figure 1 to Figure 2 Based on the embodiment shown, another method for forming a semiconductor structure is proposed. Figure 3 By increasing the height of the etch stop layer 131 (the etch stop layer 131 is also located between the conductive protection structure 122 and the gate protection structure 111), the margin of the etch stop layer 131 that can be consumed when etching the conductive protection structure 122 is increased, thereby improving the risk of short circuit between the second plug and the gate structure 110.

[0040] However, on the one hand, since the material of the etch stop layer 131 will affect the electrical properties of the gate structure 120, the material selection of the etch stop layer 131 is limited, resulting in that in the process of etching the gate protection structure 111, it is difficult to have a large etching selectivity ratio between the material of the gate protection structure 111 and the material of the etch stop layer 131; on the other hand, in order to increase the contact area between the first plug and the gate structure to reduce the contact resistance, the patterned layer used to form the first plug opening not only exposes the gate protection structure 111, but also exposes the etch stop layer 131. Therefore, when etching the gate protection structure 111, the etch stop layer 131 is easily exposed to the side wall surface of the interconnection structure 120 after being worn, thereby causing a short circuit between the first plug and the interconnection structure 120, that is, causing a short circuit between the interconnection structure 120 and the gate structure 110, resulting in poor reliability of the semiconductor structure.

[0041] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, by etching an initial first side wall to form a first side wall and an opening, the opening exposing the first protection structure side wall surface, the second protection structure side wall surface and the top surface of the first side wall, and forming a second side wall in the opening, thereby improving the reliability of the semiconductor structure.

[0042] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 4 to 14 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0044] Please refer to Figure 4 , providing a substrate.

[0045] In this embodiment, the base includes a substrate 200 and a plurality of fin structures 201 that are separated from each other and located on the substrate 200 .

[0046] The substrate 200 is made of a semiconductor material.

[0047] In this embodiment, the material of the substrate 200 is silicon.

[0048] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multinary semiconductor materials composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, multinary semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0049] In this embodiment, before the subsequent formation of the dummy gate structure, an isolation dielectric layer (not shown) is formed on the surface of the substrate 200, and the isolation dielectric layer is also located on a partial side wall surface of the fin structure 201, thereby enabling electrical insulation between the substrate 200 and other semiconductor structures, and electrical insulation between adjacent fin structures 201.

[0050] Next, a plurality of source-drain structures are formed in the substrate, and a plurality of gate structures, a first protection structure located on the top surface of the gate structure, a first conductive structure located between adjacent gate structures, a second protection structure located on the top surface of the first conductive structure, and an initial first sidewall between the gate structure and the first conductive structure are formed on the substrate. The initial first sidewall is also located between the first protection structure and the second protection structure. The source-drain structures are located in the substrate on both sides of the gate structure, and the first conductive structure is located on the source-drain structures. For the specific process, please refer to Figures 5 to 9 .

[0051] Please refer to Figure 5 , forming a plurality of source-drain structures 220 in the substrate, and forming an initial first spacer 230 on the substrate.

[0052] In this embodiment, the method for forming the initial first sidewall 230 includes: forming a plurality of dummy gate structures 210 on the surface of the substrate, wherein the dummy gate structure 210 spans the fin structure 201; forming an initial first sidewall material layer (not shown) on the surface of the dummy gate structure 210 and the surface of the substrate; and etching back the initial first sidewall material layer until the top surface of the dummy gate structure 210 and the surface of the substrate are exposed to form an initial first sidewall 230.

[0053] In this embodiment, the dummy gate structure 210 can play a positioning role when a gate structure is subsequently formed.

[0054] In other embodiments, the method for forming the initial first spacer includes: forming a plurality of gate structures on the surface of the substrate, wherein the gate structures are part of the structure of the semiconductor device; and forming the initial first spacer on the sidewall surface of the gate structure.

[0055] In this embodiment, the process of forming the initial first spacer material layer includes a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0056] In this embodiment, the process of etching the initial first spacer material layer includes at least one of a dry etching process and a wet etching process.

[0057] In this embodiment, the material of the dummy gate structure 210 includes polysilicon.

[0058] In this embodiment, the method for forming the dummy gate structure 210 includes: forming a dummy gate material film (not shown) on the substrate covering the surface of the fin structure 201; patterning the dummy gate material film until the substrate surface is exposed, and forming a dummy gate structure 210 on the substrate that spans the fin structure 201, wherein the top surface of the dummy gate structure 210 is higher than the top surface of the fin structure 201.

[0059] Please refer to Figure 6 , a plurality of source-drain structures 220 are formed in the substrate on both sides of the dummy gate structure 210 .

[0060] In this embodiment, the method for forming the source-drain structure 220 includes: after forming the initial first side wall 230, using the pseudo gate structure 210 and the initial first side wall 230 as masks, etching the fin structure 201 on both sides of the pseudo gate structure 210, and forming a plurality of source-drain openings (not shown) in the fin structure 201; and using an epitaxial growth process to form the source-drain structure 220 in the source-drain openings.

[0061] In this embodiment, the top surface of the source / drain structure 220 is flush with or higher than the top surface of the fin structure 201 .

[0062] In other embodiments, the method for forming the source-drain structure includes: using the dummy gate structure and the initial first side wall as a mask, performing ion implantation on the fin structure on both sides of the dummy gate structure to form doped regions on both sides of the dummy gate structure, and using the doped regions as the source-drain structure.

[0063] In this embodiment, the process of etching the fin structure 201 on both sides of the dummy gate structure 210 includes at least one of a dry etching process and a wet etching process.

[0064] Please refer to Figure 7 After forming the source-drain structure 220 , a first dielectric layer 240 is formed on the surface of the substrate.

[0065] Specifically, in this embodiment, the first dielectric layer 240 is located on the surface of the source-drain structure 220 and the surface of the isolation dielectric layer, and the first dielectric layer 240 is also located on the sidewall surface of the initial first spacer 230 .

[0066] The method for forming the first dielectric layer 240 includes: forming a first dielectric material layer (not shown) on the surface of the source-drain structure 220, the surface of the isolation dielectric layer, the top surface of the dummy gate structure 210, and the surface of the initial first sidewall 230; and planarizing the first dielectric material layer until the top surface of the dummy gate structure 210 and the top surface of the initial first sidewall 230 are exposed.

[0067] In this embodiment, the process of forming the first dielectric material layer includes: a spin coating process or a deposition process, etc. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0068] In this embodiment, the process of planarizing the first dielectric material layer includes: at least one of a chemical mechanical polishing process, a dry etching process or a wet etching process.

[0069] In this embodiment, the material of the first dielectric layer 240 includes silicon oxide.

[0070] In other embodiments, the material of the first dielectric layer includes at least one of SiOCH, SiOH and SiCN.

[0071] Please continue to refer to Figure 7 After forming the first dielectric layer 240 , the dummy gate structure 210 is removed to form a gate opening (not shown); and an initial gate structure 250 is formed in the gate opening.

[0072] Since the initial gate structure 250 is formed in the gate opening, the first dielectric layer 240 is located on the sidewall surface of the initial gate structure 250. Accordingly, the first dielectric layer 240 is also located on the sidewall surface of the gate structure and the first protection structure formed subsequently.

[0073] Specifically, in this embodiment, the method for forming the initial gate structure 250 includes: forming a gate structure material layer (not shown) in the gate opening, on the surface of the first dielectric layer 240, and on the top surface of the initial first side wall 230; and flattening the gate structure material layer until the top surface of the initial first side wall 230 and the surface of the first dielectric layer 240 are exposed.

[0074] The gate structure material layer includes: a gate dielectric material layer located on the inner wall surface of the gate opening, the surface of the first dielectric layer 240, and the top surface of the initial first sidewall 230; a work function material layer located on the surface of the gate dielectric material layer; and a gate electrode material layer located on the surface of the work function material layer and filling the gate opening.

[0075] The process of forming the gate dielectric material layer includes an oxidation process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0076] The process of forming the work function material layer includes a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0077] The process of forming the gate electrode material layer includes a metal electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0078] The process of planarizing the gate electrode material layer, the work function material layer and the gate dielectric material layer includes an etch-back process or a chemical mechanical polishing process.

[0079] Please refer to Figure 8 , etching the initial gate structure 250 to form a gate structure 251 spanning the fin structure 201, wherein the thickness of the gate structure 251 is less than the depth of the gate opening in a direction perpendicular to the substrate surface; after forming the gate structure 251, forming a first protection structure 260 in the gate opening at the top of the gate structure 251, wherein the first protection structure 260 is located on the top surface of the gate structure 251, and the source-drain structure 220 is located in the substrate on both sides of the gate structure 251.

[0080] Specifically, in this embodiment, the source-drain structure 220 is located in the fin structure 201 on both sides of the gate structure 251 .

[0081] In this embodiment, the process of etching the initial gate structure 250 includes at least one of a dry etching process and a wet etching process.

[0082] In this embodiment, the gate structure 251 includes: a gate dielectric layer (not shown) located on the inner wall surface of the gate opening; a work function layer (not shown) located on the surface of the gate dielectric layer; and a gate electrode layer (not shown) located on the surface of the work function layer, and the gate electrode layer fills the gate opening.

[0083] The material of the gate dielectric layer includes a high dielectric constant material (dielectric constant greater than 3.9), which includes hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0084] The material of the gate electrode layer includes a metal material, for example, one or a combination of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0085] The material of the work function layer includes titanium nitride, tantalum nitride or titanium aluminum.

[0086] In other embodiments, the material of the gate structure includes polysilicon.

[0087] In this embodiment, the method for forming the first protection structure 260 includes: forming a first protection structure material layer (not shown) in the gate opening on the top surface of the gate structure 251 and on the surface of the first dielectric layer 240; and planarizing the first protection structure material layer until the surface of the first dielectric layer 240 is exposed.

[0088] The process of forming the first protective structure material layer includes a spin coating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0089] The process of planarizing the first protection structure material layer includes an etch-back process or a chemical mechanical polishing process.

[0090] The first protection structure 260 and the second protection structure formed subsequently are made of different materials.

[0091] In the present embodiment, the material of the first protection structure 260 includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride, and aluminum oxide.

[0092] The first protection structure 260 is used to protect the gate structure 251 and reduce the damage to the gate structure 251 caused by processes such as etching in subsequent semiconductor manufacturing processes. At the same time, it can better insulate the gate structure 251 from conductive structures other than the subsequently formed first conductive structure.

[0093] Please refer to Fig. 9 A first conductive structure 270 is formed between adjacent gate structures 251, and the first conductive structure 270 is located on the source-drain structure 220; a second protective structure 280 is formed on the top surface of the first conductive structure 270, and the initial first sidewall 230 is located between the gate structure 251 and the first conductive structure 270, and the initial first sidewall 230 is also located between the first protective structure 260 and the second protective structure 280.

[0094] The method for forming the first conductive structure 270 includes: etching the first dielectric layer 240 between adjacent gate structures 251, forming a third conductive opening (not shown) in the first dielectric layer 240, the bottom of the third conductive opening exposing the surface of the source-drain structure 220; forming a first conductive structure material layer (not shown) in the third conductive opening, on the top surface of the initial first sidewall 230, and on the surface of the first protection structure 260; and etching back the first conductive structure material layer until the surface of the first conductive structure material layer is lower than the top surface of the initial first sidewall 230.

[0095] In this embodiment, the top surface of the first conductive structure 270 is lower than the top surface of the first protective structure 260 , and the top surface of the first conductive structure 270 is higher than the bottom surface of the first protective structure 260 .

[0096] The process of forming the first conductive structure material layer includes: a deposition process or a metal electroplating process, etc. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, etc. The metal electroplating process is, for example, a selective metal electroplating process, etc.

[0097] In this embodiment, the process of etching back the first conductive structure material layer includes at least one of a dry etching process and a wet etching process.

[0098] In this embodiment, the material of the first conductive structure 270 includes a metal material, for example, one or a combination of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0099] The method for forming the second protection structure 280 includes: after forming the first conductive structure 270, forming a second protection structure material layer (not shown) in the third conductive opening at the top of the first conductive structure 270, as well as on the top surface of the initial first sidewall 230 and the surface of the first protection structure 260; and planarizing the second protection structure material layer until the top surface of the initial first sidewall 230 and the top surface of the first protection structure 260 are exposed.

[0100] Since the first conductive structure 270 and the second protective structure 280 are located in the third conductive opening, the first dielectric layer 240 is also located on the sidewalls of the first conductive structure 270 and the second protective structure 280 .

[0101] The process of forming the second protective structure material layer includes a spin coating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0102] The process of planarizing the second protection structure material layer includes an etch-back process or a chemical mechanical polishing process.

[0103] In this embodiment, the material of the second protection structure 280 includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride, and aluminum oxide.

[0104] Please refer to Fig.10 , the initial first sidewall spacer 230 is etched to form a first sidewall spacer 231 and an opening 290 , wherein the opening 290 exposes the sidewall surface of the first protection structure 260 , the sidewall surface of the second protection structure 280 and the top surface of the first sidewall spacer 231 .

[0105] Specifically, the top surface of the first sidewall 231 is higher than the bottom surface of the first protection structure 260 and the bottom surface of the second protection structure 280 .

[0106] The opening 290 provides space for subsequently forming a second sidewall.

[0107] Due to the etching of the initial first sidewall 230, a first sidewall 231 and an opening 290 are formed, and the opening 290 exposes the sidewall surface of the first protection structure 260, the sidewall surface of the second protection structure 280 and the top surface of the first sidewall 231, and subsequently a second sidewall is formed in the opening 290. On the one hand, when etching the first protection structure 260 and the second protection structure 280, the first sidewall 231 can be protected by the second sidewall, the loss of the first sidewall 231 is reduced, and the possibility of exposing the sidewall surface of the first conductive structure 270 or the gate structure 251 is reduced, thereby reducing the risk of short circuit between the gate structure 251 and the first conductive structure 270 and improving the reliability of the semiconductor structure. On the other hand, since the first sidewall 231 and the second sidewall are formed separately, the material selection of the first sidewall 231 and the second sidewall is more free, and the first sidewall 231 and the second sidewall can be made of different materials. Thus, by selecting the material of the second side wall, when etching the first protection structure 260 and the second protection structure 280, the etching selectivity ratio between the first protection structure 260 and the second side wall 290, and between the second protection structure 280 and the second side wall 290 can be increased, respectively, so as to reduce the loss of the second side wall 290 and increase the ability of the second side wall 290 to block the etching process, so that the second side wall 290 can better protect the first side wall 231 and reduce the loss of the first side wall 231, thereby reducing the risk of short circuit between the gate structure 251 and the first conductive structure 270 and improving the reliability of the semiconductor structure.

[0108] Furthermore, since the ability of the second sidewall 290 to block the etching process has been increased, in the subsequent etching process of forming the second conductive structure and the third conductive structure, the size of the first conductive opening that provides space for the second conductive structure and the size of the second conductive opening that provides space for the third conductive structure can be increased while ensuring the reliability of the semiconductor structure. This increases the process window for forming the second conductive structure and the third conductive structure, reduces the process difficulty, and at the same time, reduces the contact resistance between the second conductive structure and the gate structure 251, and the contact resistance between the third conductive structure and the first conductive structure 270, thereby improving the performance of the semiconductor structure.

[0109] In this embodiment, the method for forming the opening 290 further includes: etching at least one of the sidewalls of the first protection structure 260 and the sidewalls of the second protection structure 280 while or after etching the initial first sidewall 230. Thus, the width of the opening 290 can be further expanded to provide a larger space for the subsequent formation of the second sidewall, and then, at least the maximum width of the top of the second sidewall is greater than the width of the first sidewall 231.

[0110] Since the width of the top of the second side wall is greater than the width of the first side wall 231, when etching the first protection structure 260 and the second protection structure 280, the margin of the second side wall that can be consumed is increased, thereby improving the blocking ability of the second side wall to the etching process, so that the first side wall 231 is better protected, further reducing the short circuit risk between the gate structure 251 and the first conductive structure 270, and improving the reliability of the semiconductor structure.

[0111] In other embodiments, the sidewalls of the first protection structure and the sidewalls of the second protection structure are not etched.

[0112] In this embodiment, the process of etching the initial first sidewall spacer 230 includes at least one of a dry etching process and a wet etching process.

[0113] In this embodiment, the process of etching at least one of the sidewall of the first protection structure 260 and the sidewall of the second protection structure 280 includes at least one of a dry etching process and a wet etching process.

[0114] In this embodiment, the material of the first spacer 231 includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxycarbide, silicon carbide, a low-k dielectric, and an air gap.

[0115] Please refer to Fig.11 , a second sidewall 291 is formed in the opening 290 .

[0116] The method for forming the second sidewall 291 includes: forming a second sidewall material layer (not shown) in the opening 290 and on the top surfaces of the first protection structure 260 and the second protection structure 280; and planarizing the second sidewall material layer until the top surfaces of the first protection structure 260 and the second protection structure 280 are exposed.

[0117] In this embodiment, the width of the top of the second sidewall 291 is greater than the width of the first sidewall 231 .

[0118] In this embodiment, on a plane perpendicular to the extending direction of the gate structure 251 , the projection shape of the second sidewall 291 is a trapezoid with a top width greater than a bottom width.

[0119] In the trapezoid, the distance a between the top edge of the first protection structure 260 and the sidewall surface of the adjacent first spacer 231 is 1 angstrom to 30 angstroms.

[0120] In the trapezoid, a distance b between the top edge of the second protection structure 280 and the sidewall surface of the adjacent first spacer 231 is 1 angstrom to 30 angstroms.

[0121] It should be noted that, according to the requirements on the blocking performance of the second sidewall 291 , the interval a and the interval b may be equal or unequal.

[0122] In another embodiment, on a plane perpendicular to the extending direction of the gate structure 251, the second sidewall spacer 292 (eg Fig.15 The projection shape of the first protective structure 260 is a rectangle. In the rectangle, the spacing c between the top edge of the first protective structure 260 and the side wall surface of the adjacent first sidewall 231 is 1 angstrom to 30 angstroms. In the rectangle, the spacing d between the top edge of the second protective structure 280 and the side wall surface of the adjacent first sidewall 231 is 1 angstrom to 30 angstroms. It should be noted that, according to the requirements for the blocking performance of the second sidewall 292, the spacing c and the spacing d can be equal or unequal.

[0123] In this embodiment, the process of forming the second spacer material layer includes: a spin coating process or a deposition process, etc. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0124] In this embodiment, the process of planarizing the second spacer material layer includes: at least one of a chemical mechanical polishing process, a dry etching process or a wet etching process.

[0125] In this embodiment, the material of the second spacer 291 includes one or more of silicon carbide nitride, silicon oxycarbide, silicon carbide, aluminum nitride and aluminum oxide.

[0126] Please refer to Fig.12 After the second sidewall spacer 291 is formed, a second dielectric layer 300 is formed on the surfaces of the first dielectric layer 240 , the first protective structure 260 , the second protective structure 280 and the second sidewall spacer 291 .

[0127] The process of forming the second dielectric layer 300 includes: a spin coating process or a deposition process, etc. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, etc.

[0128] In this embodiment, the material of the second dielectric layer 300 includes silicon oxide.

[0129] In other embodiments, the material of the second dielectric layer includes at least one of SiOCH, SiOH and SiCN.

[0130] The second dielectric layer 300 , on the one hand, protects the surface of the semiconductor structure and reduces damage to the surface of the semiconductor structure caused by the etching process during the subsequent etching process for forming the second conductive structure and the third conductive structure; on the other hand, provides support for forming the second conductive structure and the third conductive structure.

[0131] In other embodiments, the second dielectric layer is not formed.

[0132] Please refer to Fig.13 After forming the second sidewall 291, at least a portion of the first protection structure 260 is etched to form a first conductive opening 310 in the first dielectric layer 240, and the bottom of the first conductive opening 310 exposes the top surface of the gate structure 251; after forming the second sidewall 291, at least a portion of the second protection structure 280 is etched to form a second conductive opening 320 in the first dielectric layer 240, and the bottom of the second conductive opening 320 exposes the top surface of the first conductive structure 270.

[0133] Since the second dielectric layer 300 is formed in this embodiment, the first conductive opening 310 is also located in the second dielectric layer 300 , and the second conductive opening 320 is also located in the second dielectric layer 300 .

[0134] In this embodiment, the first conductive opening 310 and the second conductive opening 320 are formed simultaneously.

[0135] The method for forming the first conductive opening 310 and the second conductive opening 320 includes: forming a conductive opening patterned layer (not shown) on the surface of the second dielectric layer 300, wherein the conductive opening patterned layer has a first opening (not shown) and a second opening (not shown), wherein the bottom of the first opening exposes at least a portion of the surface of the second dielectric layer on the first protection structure 260, and the bottom of the second opening exposes at least a portion of the surface of the second dielectric layer on the second protection structure 280; using the conductive opening patterned layer as a mask, etching the second dielectric layer 300, the first dielectric layer 240, the first protection structure 260 and the second protection structure 280 until the top surface of the gate structure 251 and the top surface of the first conductive structure 270 are exposed.

[0136] In this embodiment, the process of forming the first conductive opening 310 and the second conductive opening 320 includes at least one of a dry etching process and a wet etching process.

[0137] Please refer to Fig.14, a second conductive structure 311 is formed in the first conductive opening 310 ; and a third conductive structure 321 is formed in the second conductive opening 320 .

[0138] The second conductive structure 311 is electrically interconnected with the gate structure 251 .

[0139] The third conductive structure 321 is electrically interconnected with the first conductive structure 270 .

[0140] In this embodiment, the method for forming the second conductive structure 311 and the third conductive structure 321 includes: forming a conductive structure material layer (not shown) in the first conductive opening 310, in the second conductive opening 320, and on the surface of the second dielectric layer 300; and planarizing the conductive structure material layer until the surface of the second dielectric layer 300 is exposed.

[0141] The process of forming the conductive structure material layer includes a metal electroplating process or a deposition process. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0142] The process of planarizing the conductive structure material layer includes an etch-back process or a chemical mechanical polishing process.

[0143] In other embodiments, different conductive opening patterning layers are formed on the surface of the second dielectric layer, and the first conductive opening and the second conductive opening are formed respectively, and the second conductive structure and the third conductive structure are formed respectively. It should be noted that the third conductive structure can be formed after the second conductive structure is formed, or the second conductive structure can be formed after the third conductive structure is formed. The third conductive structure is formed after the second conductive structure is formed as an example. Specifically, a first conductive opening patterned layer is formed on the surface of the second dielectric layer, the first conductive opening patterned layer has a first opening (not shown), and the bottom of the first opening exposes at least a portion of the second dielectric layer surface on the first protective structure; the second dielectric layer, the first dielectric layer, and the first protective structure are etched using the first conductive opening patterned layer as a mask until the top surface of the gate structure is exposed to form a first conductive opening; the second conductive structure is formed in the first conductive opening; after the second conductive structure is formed, a second conductive opening patterned layer is formed on the surface of the second conductive structure and the surface of the second dielectric layer, the second conductive opening patterned layer has a second opening (not shown), and the bottom of the second opening exposes at least a portion of the second dielectric layer surface on the second protective structure; the second conductive opening patterned layer is used as a mask to etch the second dielectric layer 300, the first dielectric layer 240, and the second protective structure until the top surface of the first conductive structure 270 is exposed to form a second conductive opening; and the third conductive structure is formed in the second conductive opening.

[0144] In this embodiment, the material of the second conductive structure 311 is the same as the material of the third conductive structure 321 .

[0145] In other embodiments, the material of the second conductive structure 311 and the material of the third conductive structure 321 may be different.

[0146] The material of the second conductive structure 311 includes a metal material, for example, one or a combination of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0147] The material of the third conductive structure 321 includes a metal material, for example, one or a combination of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0148] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.11 , including: a substrate; a plurality of gate structures 251 located on the substrate; a plurality of source-drain structures 220 located in the substrate on both sides of the gate structure 251; a first protection structure 260 located on the top surface of the gate structure 251; a first conductive structure 270 located between adjacent gate structures, and the first conductive structure 270 is located on the source-drain structure 220; a second protection structure 280 located on the top surface of the first conductive structure 270; a first sidewall 231 located between the gate structure 351 and the first conductive structure 260; a second sidewall 291 located on the top surface of the first sidewall 231, and the second sidewall 291 is also located between the first protection structure 260 and the second protection structure 280.

[0149] In this embodiment, the base includes a substrate 200 and a plurality of fin structures 201 that are separated from each other and located on the substrate 200 .

[0150] The substrate 200 is made of a semiconductor material.

[0151] In this embodiment, the material of the substrate 200 is silicon.

[0152] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multinary semiconductor materials composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, multinary semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0153] In this embodiment, the material of the first spacer 231 includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxycarbide, silicon carbide, a low-k dielectric, and an air gap.

[0154] In this embodiment, the material of the second spacer 291 includes one or more of silicon carbide nitride, silicon oxycarbide, silicon carbide, aluminum nitride and aluminum oxide.

[0155] In this embodiment, the width of the top of the second sidewall 291 is greater than the width of the first sidewall 231 .

[0156] In this embodiment, on a plane perpendicular to the extending direction of the gate structure 251 , the projection shape of the second sidewall 291 is a trapezoid with a top width greater than a bottom width.

[0157] In the trapezoid, a distance a between the top edge of the first protection structure 260 and the sidewall surface of the adjacent first spacer 231 is 1 angstrom to 30 angstroms.

[0158] In the trapezoid, a distance b between the top edge of the second protection structure 280 and the sidewall surface of the adjacent first spacer 231 is 1 angstrom to 30 angstroms.

[0159] It should be noted that, according to the requirements on the blocking performance of the second sidewall 291 , the interval a and the interval b may be equal or unequal.

[0160] In another embodiment, on a plane perpendicular to the extending direction of the gate structure 251, the second sidewall spacer 292 (eg Fig.15 The projection shape of the first protective structure 260 is a rectangle. In the rectangle, the spacing c between the top edge of the first protective structure 260 and the side wall surface of the adjacent first sidewall 231 is 1 angstrom to 30 angstroms. In the rectangle, the spacing d between the top edge of the second protective structure 280 and the side wall surface of the adjacent first sidewall 231 is 1 angstrom to 30 angstroms. It should be noted that, according to the requirements for the blocking performance of the second sidewall 292, the spacing c and the spacing d can be equal or unequal.

[0161] In this embodiment, the first protection structure 260 and the second protection structure 280 are made of different materials.

[0162] In the present embodiment, the material of the first protection structure 260 includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride, and aluminum oxide.

[0163] In this embodiment, the material of the second protection structure 280 includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride, and aluminum oxide.

[0164] In this embodiment, the source-drain structure 220 is located in the fin structure 201 on both sides of the gate structure 251 .

[0165] In this embodiment, the top surface of the source / drain structure 220 is flush with or higher than the top surface of the fin structure 201 .

[0166] In this embodiment, the gate structure 251 includes: a gate dielectric layer (not shown) located on the inner wall surface of the gate opening; a work function layer (not shown) located on the surface of the gate dielectric layer; and a gate electrode layer (not shown) located on the surface of the work function layer, and the gate electrode layer fills the gate opening.

[0167] The material of the gate dielectric layer includes a high dielectric constant material (dielectric constant greater than 3.9), which includes hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0168] The material of the gate electrode layer includes a metal material, for example, one or a combination of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0169] The material of the work function layer includes titanium nitride, tantalum nitride or titanium aluminum.

[0170] In other embodiments, the material of the gate structure includes polysilicon.

[0171] In this embodiment, the top surface of the first conductive structure 270 is lower than the top surface of the first protective structure 260 , and the top surface of the first conductive structure 270 is higher than the bottom surface of the first protective structure 260 .

[0172] In this embodiment, the material of the first conductive structure 270 includes a metal material, for example, one or a combination of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0173] In this embodiment, the semiconductor structure also includes: an isolation dielectric layer (not shown) located on the surface of the substrate 200, and the isolation dielectric layer is also located on a partial side wall surface of the fin structure 201, thereby enabling electrical insulation between the substrate 200 and other semiconductor structures, and electrical insulation between adjacent fin structures 201.

[0174] In this embodiment, the semiconductor structure further includes: a first dielectric layer 240 located on the surface of the isolation dielectric layer, and the first dielectric layer 240 is also located on the sidewall surface of the first spacer 231 , the sidewall surface of the first protection structure 260 , and the sidewall surface of the second protection structure 280 .

[0175] In this embodiment, the material of the first dielectric layer 240 includes silicon oxide.

[0176] In other embodiments, the material of the first dielectric layer includes at least one of SiOCH, SiOH and SiCN.

[0177] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; a plurality of gate structures located on the substrate; A plurality of source-drain structures located in the substrate on both sides of the gate structure; A first protection structure located on a top surface of the gate structure; a first conductive structure located between adjacent gate structures, and the first conductive structure is located on the source-drain structure; A second protection structure located on the top surface of the first conductive structure; A first spacer located between the gate structure and the first conductive structure; A second side wall is located on the top surface of the first side wall, and the second side wall is also located between the first protection structure and the second protection structure.

2. The semiconductor structure according to claim 1, wherein: The width of the top of the second side wall is greater than the width of the first side wall.

3. The semiconductor structure according to claim 2, wherein: On a plane perpendicular to the extending direction of the gate structure, a projection shape of the second sidewall spacer is a trapezoid with a top width greater than a bottom width.

4. The semiconductor structure according to claim 2, characterized in that On a plane perpendicular to the extending direction of the gate structure, a projection shape of the second sidewall spacer is a rectangle.

5. The semiconductor structure according to claim 3 or 4, characterized in that: The distance between the top edge of the first protection structure and the sidewall surface of the adjacent first spacer is 1 angstrom to 30 angstroms.

6. The semiconductor structure according to claim 3 or 4, characterized in that: The distance between the top edge of the second protection structure and the sidewall surface of the adjacent first spacer is 1 angstrom to 30 angstroms.

7. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A plurality of source-drain structures are formed in the substrate, and a plurality of gate structures, a first protection structure located on the top surface of the gate structure, a first conductive structure located between adjacent gate structures, a second protection structure located on the top surface of the first conductive structure, and an initial first spacer located between the gate structure and the first conductive structure are formed on the substrate, wherein the initial first spacer is also located between the first protection structure and the second protection structure, the source-drain structures are located in the substrate on both sides of the gate structure, and the first conductive structure is located on the source-drain structures; Etching an initial first sidewall to form a first sidewall and an opening, wherein the opening exposes the sidewall surface of the first protection structure, the sidewall surface of the second protection structure, and the top surface of the first sidewall; A second sidewall is formed in the opening.

8. The method for forming a semiconductor structure according to claim 7, wherein: The maximum width of the second side wall is greater than the width of the first side wall.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the opening further includes: etching at least one of the sidewalls of the first protection structure and the sidewalls of the second protection structure while or after etching the initial first spacer.

10. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: Before forming the first spacer, a first dielectric layer is formed on the surface of the substrate, and the first dielectric layer is also located on the sidewalls of the gate structure, the first protection structure, the first conductive structure and the second protection structure.

11. The method for forming a semiconductor structure according to claim 10, wherein: Also includes: After forming the second sidewall spacer, at least a portion of the first protection structure is etched to form a first conductive opening in the first dielectric layer, wherein the bottom of the first conductive opening exposes the top surface of the gate structure; and a second conductive structure is formed in the first conductive opening.

12. The method for forming a semiconductor structure according to claim 10, wherein: Also includes: After forming the second sidewall spacer, etching at least a portion of the second protection structure to form a second conductive opening in the first dielectric layer, wherein the bottom of the second conductive opening exposes the top surface of the first conductive structure; A third conductive structure is formed in the second conductive opening.

13. The method for forming a semiconductor structure according to claim 10, wherein: Also includes: After forming the second sidewall spacer, a second dielectric layer is formed on the first dielectric layer, the first protective structure, the second protective structure and the surface of the second sidewall spacer.

14. The method for forming a semiconductor structure according to claim 7, wherein: The material of the first protection structure includes one or more of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride and aluminum oxide.

15. The method for forming a semiconductor structure according to claim 7, wherein: The material of the second protection structure includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride and aluminum oxide.

16. The method for forming a semiconductor structure according to claim 7, wherein: The material of the first spacer includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxycarbide, silicon carbide, a low dielectric constant medium and an air gap.

17. The method for forming a semiconductor structure according to claim 7, wherein: The material of the second spacer includes one or more of silicon carbide nitride, silicon oxycarbide, silicon carbide, aluminum nitride and aluminum oxide.

18. The method for forming a semiconductor structure according to claim 7, wherein: The material of the gate structure includes metal or polysilicon.

19. The method for forming a semiconductor structure according to claim 7, wherein: The base includes a substrate and a plurality of fin structures located on the substrate, and the gate structure crosses the fin structures.

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