reset circuit

Abstract

The application provides a reset circuit, comprising: a starting circuit, a bias circuit, a reference voltage circuit, a power voltage sampling circuit and a comparator circuit, wherein the starting circuit is used for controlling the starting of the bias circuit and automatically shutting down after the bias circuit is successfully started; the bias circuit is used for generating a voltage bias to provide voltage bias for the reference voltage circuit, the power voltage sampling circuit and the comparator circuit; the reference voltage circuit is used for generating a reference voltage; the power voltage sampling circuit is used for detecting a power voltage and outputting a power voltage sampling signal; and the comparator circuit is used for comparing the reference voltage generated by the reference voltage circuit with the power voltage sampling signal output by the power voltage sampling circuit and outputting a reset signal. The application realizes the reset detection function during power-on and abnormal power-off, and consumes low power consumption in the normal working range of the power voltage.

Description

Technical Field

[0001] This application relates to the field of circuit structure technology, and in particular to a reset circuit. Background Technology

[0002] In recent years, programmable logic devices (PLCs) such as microcontrollers have been increasingly widely used in industrial automation, process control, and intelligent instrumentation, effectively improving production efficiency, control quality, and economic benefits. Since any PLC can only execute an application program after a reliable reset, the design of the reset circuit is crucial. For example, reset circuits are commonly used in integrated circuit systems to reset registers and initialize mixed-signal circuits during power-on or when the power supply is low, preventing the chip from operating in abnormal conditions. Therefore, reset circuits are an indispensable part of integrated circuit systems. Summary of the Invention

[0003] The purpose of this application is to provide a reset circuit.

[0004] According to an embodiment of this application, a reset circuit is provided, comprising:

[0005] The circuit consists of a startup circuit, a bias circuit, a reference voltage circuit, a power supply voltage sampling circuit, and a comparator circuit.

[0006] The startup circuit is used to control the startup of the bias circuit and automatically shuts down after the bias circuit has successfully started.

[0007] Bias circuits are used to generate voltage bias, providing voltage bias for reference voltage circuits, power supply voltage sampling circuits, and comparator circuits;

[0008] Reference voltage circuit, used to generate a reference voltage;

[0009] The power supply voltage sampling circuit is used to detect the power supply voltage and output a power supply voltage sampling signal.

[0010] The comparator circuit is used to compare the reference voltage generated by the reference voltage circuit with the power supply voltage sampling signal output by the power supply voltage sampling circuit, and outputs a reset signal.

[0011] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0012] By setting up a startup circuit, bias circuit, reference voltage circuit, power supply voltage sampling circuit, and comparator circuit, the system accurately realizes the reset detection function when the power supply is powered on and when it fails due to abnormal power loss, while consuming low power within the normal operating range of the power supply voltage. Attached Figure Description

[0013] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0014] Figure 1 A structural block diagram of a reset circuit provided in an embodiment of this application;

[0015] Figure 2 A circuit diagram of the startup circuit and bias circuit in a reset circuit provided in an embodiment of this application;

[0016] Figure 3 A circuit diagram of a reference circuit in a reset circuit provided for an embodiment of this application;

[0017] Figure 4 A circuit diagram of a power supply voltage sampling circuit in a reset circuit provided in an embodiment of this application;

[0018] Figure 5 This is a circuit diagram of a comparator circuit in a reset circuit provided in an embodiment of this application. Detailed Implementation

[0019] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0020] In recent years, programmable logic devices (PLCs) such as microcontrollers have been increasingly widely used in industrial automation, process control, and intelligent instrumentation, effectively improving production efficiency, control quality, and economic benefits. Since any PLC can only execute an application program after a reliable reset, the design of the reset circuit is crucial. For example, reset circuits are commonly used in integrated circuit systems to reset registers and initialize mixed-signal circuits during power-on or when the power supply is low, preventing the chip from operating in abnormal conditions. Therefore, reset circuits are an indispensable part of integrated circuit systems.

[0021] Therefore, this application provides a reset circuit. Specifically, the reset circuit of the embodiment of this application is described below with reference to the accompanying drawings.

[0022] Figure 1 A structural block diagram of the reset circuit provided in the embodiments of this application is shown below. Figure 1 As shown, the reset circuit may include a startup circuit 110, a bias circuit 120, a reference voltage circuit 130, a power supply voltage sampling circuit 140, and a comparator circuit 150.

[0023] The startup circuit 110 is used to control the startup of the bias circuit and automatically shuts down after the bias circuit is successfully started.

[0024] Bias circuit 120 is used to generate voltage bias, providing voltage bias for reference voltage circuit, power supply voltage sampling circuit and comparator circuit.

[0025] Reference voltage circuit 130 is used to generate a reference voltage.

[0026] The reference voltage can be used in voltage regulators of power supply systems, analog-to-digital converters and digital-to-analog converters, as well as many other measurement and control systems.

[0027] The power supply voltage sampling circuit 140 is used to detect the power supply voltage and output the power supply voltage sampling signal.

[0028] It should be noted that in one implementation, the power supply voltage sampling circuit also includes a hysteresis structure, which is used to generate hysteresis when the reset signal switches, thereby avoiding jitter in the reset signal.

[0029] The comparator circuit 150 is used to compare the reference voltage generated by the reference voltage circuit with the power supply voltage sampling signal output by the power supply voltage sampling circuit, and output a reset signal.

[0030] It should be noted that both the reference voltage generated by the reference voltage circuit and the power supply voltage sampling signal output by the power supply voltage sampling circuit have positive temperature coefficients.

[0031] It should be noted that the specific structures of the startup circuit and the bias circuit are as follows: Figure 2 As shown, Figure 2 This is a circuit diagram of the startup circuit and the bias circuit. The startup circuit includes a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor; the bias circuit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a resistor. As an example, the first PMOS transistor can be PMOS transistor MPS0, the second PMOS transistor can be PMOS transistor MPS1, the first NMOS transistor can be NMOS transistor MNS0, the third PMOS transistor can be PMOS transistor MPB1, the fourth PMOS transistor can be PMOS transistor MPB2, the fifth PMOS transistor can be PMOS transistor MPB3, the second NMOS transistor can be NMOS transistor MNB1, the third NMOS transistor can be NMOS transistor MNB2, the fourth NMOS transistor can be NMOS transistor MNB3, and the resistor can be resistor R0.

[0032] In other words, such as Figure 2As shown, the startup circuit 110 may include PMOS transistors MPS0, MPS1 and NMOS transistor MNS0, which are used to ensure the normal startup of the bias circuit 120 when powered on; the bias circuit 120 may include PMOS transistors MPB1, MPB2, MPB3 and NMOS transistors MNB1, MNB2, MNB3 and resistor R0, which are used to generate quiescent current and form a gate bias voltage through the gate of PMOS transistor MPB3 and the gate of NMOS transistor MNB3 to provide voltage bias for other modules.

[0033] Among them, such as Figure 2 As shown, the sources of PMOS transistors MPS0, MPS1, MPB1, MPB2, and MPB3 are connected to the power supply. The sources and drains of NMOS transistor MNS0, and the sources of NMOS transistors MNB2 and MNB3, are connected to ground. The drain of PMOS transistor MPS0 is connected to the gate of PMOS transistor MPS1 and the gate of NMOS transistor MNS0. The drain of PMOS transistor MPS1 is connected to the drain of NMOS transistor MN2, the gate of NMOS transistor MNB3, and the drain of PMOS transistor MPB2. The gates of PMOS transistors MPB1, MPB2, and MPB3 are connected to the drain of MPB3 and... The drain of NMOS transistor MNB3 is connected; the drain of PMOS transistor MPB1 is connected to the drain and gate of NMOS transistor MNB1; the source of NMOS transistor MNB1 is connected to one end of resistor R0, and the other end of resistor R0 is connected to ground potential; PMOS transistors MPB1, MPB2, and MPB3 form a current mirror structure, and NMOS transistors MNB1 and MNB2 form a current mirror structure, and a feedback loop is formed through NMOS transistor MNB3 and PMOS transistor MPB3 to ensure that the current ratio of the branches of PMOS transistors MPB1, MPB2, and MPB3 is the same as the width-to-length ratio of MPB1, MPB2, and MPB3.

[0034] For example, assuming that PMOS transistors MPB1, MPB2, and MPB3 have the same width-to-length ratio, and NMOS transistors MNB2 and MNB3 have the same width-to-length ratio, then I MNB1 =I MNB2 -I MNB3 =I0,I MNB1 and I MNB2 Let MPB1 and MPB2 be the branch currents, respectively. By appropriately setting the dimensions of NMOS transistors MNB1, MNB2, and MNB3 to ensure they operate in the saturation region, we can conclude that:

[0035]

[0036] Where: K MNB1 =μ n C ox (W / L) MNB1 K MNB2 =μn C ox (W / L) MNB2 ,μ n C represents the electron mobility of an NMOS transistor. ox The gate oxide capacitance per unit area of ​​the MOSFET gate (W / L) MNB1 and (W / L) MNB2 These are the width-to-length ratios of NMOS transistors MNB1 and MNB2, respectively.

[0037] Therefore, we can know that:

[0038]

[0039] As can be seen from formula (2), this current is a current that is independent of the power supply voltage. By reasonably setting the size of NMOS transistors MNB1, MNB2, and MNB3 and the resistance value of resistor R0, the expected bias current can be obtained, and finally the bias voltage is provided to other modules through NMOS transistors MNB3 and MPB3.

[0040] When the power supply is turned on, the initial gate voltage of NMOS transistor MNS0 is 0V, which controls PMOS transistor MPS1 to turn on. PMOS transistor MPS1 charges the gate of NMOS transistor MNB3 until MNB3 turns on, which in turn pulls down the gate potential of PMOS transistors MPB1, MPB2, MPB3, and MPS0 to turn them on, thus starting the bias circuit. MPS0 turns on when the gates of NMOS transistors MNS0 and PMOS transistor MPS1 are charged to a high level, and PMOS transistor MPS1 eventually turns off.

[0041] It should be noted that, in one implementation, the reference voltage circuit 130 may include N sub-reference voltage circuits; each sub-reference voltage circuit includes: a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; wherein, the connection relationship of each component in each sub-reference voltage circuit may be as follows: the gate of the sixth PMOS transistor is connected to the gate of the fifth PMOS transistor in the bias circuit, the source of the sixth PMOS transistor is connected to the power supply line, the drain of the sixth PMOS transistor is connected to the drain and gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor, and the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor; the drain of the sixth NMOS transistor serves as the output of the sub-reference voltage circuit; wherein, N is a positive integer.

[0042] Furthermore, in this embodiment, in the first-stage sub-reference voltage circuit located at the first position among the N sub-reference voltage circuits, the source of the sixth NMOS transistor in the first-stage sub-reference voltage circuit is connected to ground potential; in the i-th stage sub-reference voltage circuit located at other positions among the N sub-reference voltage circuits, the source of the sixth NMOS transistor in the i-th stage sub-reference voltage circuit is connected to the output of the (i+1)-th stage sub-reference voltage circuit; wherein, 1 <i≤N。

[0043] For example, such as Figure 3 The diagram shows a schematic of a reference voltage circuit. It is assumed that the reference voltage circuit 130 consists of N sub-reference voltage circuits 131 (N is a positive integer greater than or equal to 1), including N PMOS transistors and 2N NMOS transistors. The N PMOS transistors are composed of PM1, PM2...PMn, and the 2N NMOS transistors are composed of NM1S0, NM2S0...NMNS0, NM2S1, NM2S1...NMNS1.

[0044] Among them, such as Figure 3 As shown, PMOS transistor PMi and NMOS transistors NMiS0 and NMiS1 constitute the i-th sub-reference voltage circuit 131 (where 1≤i≤N and are positive integers, the same below); the connection of each PMOS transistor and NMOS transistor in the i-th sub-reference voltage circuit 131 can be as follows: the gate of PMOS transistor PMi is connected to the gate of PMOS transistor MPB3 in the bias circuit, the source of PMOS transistor PMi is connected to the power supply line, the drain of PMOS transistor PMi is connected to the drain and gate of NMOS transistor NMiS0 and the gate of NMiS1, and the source of NMOS transistor NMiS0 is connected to the drain of NMiS1; at the same time, the drain of NMiS1 serves as the output of the i-th sub-reference voltage circuit. Furthermore, if i > 1, the source of NMiS1 is connected to the output of the sub-reference voltage circuit of stage i-1. When i = 1, the source of NM1S1 is grounded. Appropriately select the dimensions of PMOS transistor PMi and NMOS transistors NMiS0 and NMiS1 so that NMOS transistors NMiS0 and NMiS1 operate in the subthreshold region. From the subthreshold region formula, we can obtain formula (3):

[0045]

[0046] In formula (3), I bias V is the branch current where PMi is located, I0 is a process-dependent current parameter, W0 / L0 and W1 / L1 are the aspect ratios of NMiS0 and NMiS1, respectively. T For thermal voltage, V thnξ represents the threshold voltage of the NMOS transistor, VGS0 and VGS1 are the gate-source voltage differences of NMiS0 and NMiS1 respectively, and VDS0 and VDS1 are the drain voltage differences of NMiS0 and NMiS1 respectively; n This is the subthreshold slope factor of the NMOS transistor, a process-dependent constant.

[0047] Additionally, when V DS0 With V DS1 greater than 3V T When, formula (3) can be ignored and Then formula (3) simplifies to:

[0048]

[0049] Therefore, we get:

[0050] V DS1 =V GS1 -V VGS0 ≈ξ n V T lnk1 (5)

[0051] Where k1 = (W0 / L0) / (W1 / L1);

[0052] In summary, ignoring the influence of the subsequent sub-reference voltage circuit on the preceding stage and the effect of the substrate bias, the final output reference voltage of the corresponding reference voltage circuit is:

[0053] V ptat ≈nV DS1 ≈nξ n V T lnk1 (6).

[0054] Furthermore, all NMOS transistors in the sub-reference voltage circuits of the reference voltage circuit operate in the subthreshold region, and the quiescent current can be very low, so the circuit structure can achieve low power consumption design.

[0055] It should be noted that, in one implementation, the specific structure of the power supply voltage sampling circuit is as follows: Figure 4 As shown, Figure 4 This is a circuit diagram of the power supply voltage sampling circuit. The power supply voltage sampling circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a diode; wherein:

[0056] As an example, the seventh PMOS transistor can be PMOS transistor PMT0, the eighth PMOS transistor can be PMOS transistor PMT1, the ninth PMOS transistor can be PMOS transistor PMT2, the seventh NMOS transistor can be NMOS transistor NMT0, the eighth NMOS transistor can be NMOS transistor NMT1, and the diode can be diode D0.

[0057] like Figure 4 As shown, the connection between the PMOS transistors, NMOS transistors, and diodes in the power supply voltage sampling circuit is as follows: the sources of PMOS transistors PMT0 and PMT2 are connected to the power supply; the drains of PMOS transistors PMT0 and PMT2 are connected to the source of PMT1 and the drain of diode D0; the gate of PMOS transistor PMT0 is connected to the gate and drain of PMT1 and the drain of NMOS transistor NMT0; the gate of PMOS transistor PMT2 is connected to the output signal POR of the overall reset circuit; the gates of NMOS transistors NMT0 and NMT1 are connected to the gate of NMOS transistor MNB3 in the bias circuit; the sources of NMOS transistors NMT0 and NMT1 are connected to ground potential; and the drain of NMT1 is connected to the negative terminal of the diode and serves as the output of the power supply voltage sampling circuit, connected to the comparator circuit.

[0058] It should be noted that in one implementation, NMOS transistors NMT0 and NMT1 are connected to the gate of NMOS transistor MNB3 in the bias circuit, forming a current mirror structure, which provides current bias for the branches containing PMT1 and D0, respectively; PMOS transistors PMT0 and PMT1 operate in the subthreshold region, and as mentioned above, the source-drain voltage difference of PMT0 is:

[0059] V DSP =V GSPMT0 -V GSPMT1 ≈ξ P V T lnk2 (7)

[0060] Where, k2=(W PMT1 / L PMT1 ) / (W PMT0 / L PMT0 ), W PMT1 / L PMT1 and W PMT0 / L PMT0 The width-to-length ratios of PMOS transistors PMT1 and PMT0 are respectively, ξ p The subthreshold slope factor for the PMOS transistor is a process-dependent constant.

[0061] When POR is high, the output voltage Vsamp = Vsamp1 of the power supply voltage sampling circuit is:

[0062] V samp1 =VDD -V DSP -V pn ≈V DD -ξ P V T lnk2-V pn (8)

[0063] Where Vpn is the voltage difference between the positive and negative terminals of diode D0.

[0064] When POR is low, the output voltage of the power supply voltage sampling circuit is Vsamp = Vsamp2.

[0065] It is worth noting that the diode PN junction voltage Vpn has a negative temperature coefficient, so Vsamp1 and Vsamp2 both have positive temperature coefficients. In addition, the quiescent current of the power supply voltage sampling embodiment circuit is limited by the current of NMOS transistors NMT0 and NMT1, and the current of NMOS transistors NMT0 and NMT1 is generated by the voltage bias signal output by the bias circuit. The quiescent operating current of the power supply voltage sampling circuit will not change with the power supply voltage. It can still operate in a constant low power consumption state when the power supply voltage operating range is relatively wide.

[0066] In one implementation, such as Figure 5 The diagram shows a circuit diagram of a comparator circuit. The output Vptat of the reference voltage circuit and the output voltage Vsamp of the power supply voltage sampling circuit are compared by the comparator, and finally a power supply reset signal POR is output. Taking the above embodiment as an example, the operation process of the high-precision, low-power reset circuit is as follows:

[0067] When the power supply is powered on, as the power supply voltage increases, the startup circuit controls the bias circuit to start and provides bias for the reference voltage circuit, the power supply voltage sampling circuit, and the comparator circuit. When the power supply voltage is high enough, the reference voltage circuit is pre-stabilized and outputs a stable reference voltage VPTAT. At the same time, the power supply voltage sampling circuit outputs a voltage Vsamp that varies with the power supply, at which point Vsamp = Vsamp1. The comparator circuit compares the reference voltage Vptat and the voltage Vsamp and outputs a reset signal POR.

[0068] When the power supply voltage reaches the power-on reset threshold VDD_TH1:

[0069] V samp1 =V ptat (10)

[0070] From formulas (6) and (8), we can obtain:

[0071] V DD_TH1 =nξ n V T lnk1+ξp V T lnk2+V pn (11)

[0072] And because of the thermal voltage V in formula (11) T =kT / q, which is positively correlated with temperature, while the diode PN junction voltage Vpn has a negative temperature coefficient, and other parameters are independent of temperature; therefore, by adjusting n, k1, k2 and the area of ​​the diode, the power-on reset threshold VDD_TH1 can be adjusted and made to have a lower temperature coefficient, thereby greatly reducing the correlation between the power-on reset threshold voltage and temperature.

[0073] Furthermore, when the power supply VDD > VDD_TH1, the reset signal POR is released. In this embodiment, the reset signal POR is pulled low after release. The reset signal controls the PMOS transistor PMT2 in the power supply voltage sampling circuit embodiment, causing the output of the power supply voltage sampling circuit to change from Vsamp1 to Vsamp2, thereby generating a hysteresis voltage.

[0074] In another implementation, when the power supply fails, the power supply voltage sampling circuit outputs a voltage Vsamp that varies with the power supply, at which point Vsamp = Vsamp2; the comparator circuit compares the reference voltage VPTAT and the voltage Vsamp2 and outputs a reset signal POR.

[0075] When the power supply voltage drops to the power-down reset threshold VDD_TH2:

[0076] V samp2 =V ptat (12)

[0077] From formula (6), we can obtain:

[0078] V DD_TH2 =nξ n V T lnk1+V pn (13)

[0079] As mentioned above, the thermal voltage V in formula (12) T = kT / q, which is positively correlated with temperature, while the diode PN junction voltage Vpn has a negative temperature coefficient. Therefore, temperature compensation between the two can greatly reduce the correlation between the power-down reset threshold voltage VDD_TH2 and temperature.

[0080] According to the reset circuit of this application embodiment, the high-precision low-power reset circuit ensures normal startup of the entire reset circuit upon power-up through a startup circuit, provides voltage bias for other modules through a low-power bias circuit, generates a reference voltage through a low-power reference voltage circuit, accurately detects the power supply voltage through a low-power power supply voltage sampling circuit, and outputs a power supply voltage sampling signal; a comparator circuit compares the reference voltage output by the reference voltage circuit with the power supply voltage sampling signal, and finally outputs a reset signal; furthermore, the reference voltage generated by the reference voltage circuit has a positive temperature coefficient, and the power supply voltage sampling signal output by the power supply voltage sampling circuit also has a positive temperature coefficient, and the temperature coefficients of the two cancel each other out, thereby greatly reducing the correlation between the power supply voltage reset threshold and temperature; further still, the reset signal feedback controls the power supply voltage sampling circuit, forming a hysteresis effect, thereby making the power-on reset threshold and the power-down reset threshold form a hysteresis interval, ensuring the stability of the reset signal; in addition, the static operating current of each module of the low-power and high-stability reset circuit is very low and is independent of the power supply, effectively realizing a low-power design scheme.

Claims

1. A reset circuit, characterized in that, include: The circuit consists of a startup circuit, a bias circuit, a reference voltage circuit, a power supply voltage sampling circuit, and a comparator circuit. The startup circuit is used to control the startup of the bias circuit and automatically shuts down after the bias circuit is successfully started. The bias circuit is used to generate a voltage bias, providing a voltage bias for the reference voltage circuit, the power supply voltage sampling circuit, and the comparator circuit; The reference voltage circuit is used to generate a reference voltage; The power supply voltage sampling circuit is used to detect the power supply voltage and output a power supply voltage sampling signal; The comparator circuit is used to compare the reference voltage generated by the reference voltage circuit and the power supply voltage sampling signal output by the power supply voltage sampling circuit, and output a reset signal; the startup circuit includes a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor; the bias circuit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a resistor; wherein, The sources of the first, second, third, fourth, and fifth PMOS transistors are connected to a power supply; the sources and drains of the first NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are all connected to ground potential; the drain of the first PMOS transistor is connected to the gate of the second PMOS transistor and the gate of the first NMOS transistor, respectively; the drain of the second PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the fourth NMOS transistor, and the drain of the fourth PMOS transistor, respectively; the third PMOS transistor... The gates of the first, fourth, and fifth PMOS transistors are connected to the drain of the fifth PMOS transistor and the drain of the fourth NMOS transistor; the drain of the third PMOS transistor is connected to the drain and gate of the second NMOS transistor; the source of the second NMOS transistor is connected to one end of the resistor, and the other end of the resistor is connected to the ground potential; the third, fourth, and fifth PMOS transistors form a current mirror structure, the second and third NMOS transistors form a current mirror structure, and a feedback loop is formed through the fourth NMOS transistor and the fifth PMOS transistor; The reference voltage circuit includes N sub-reference voltage circuits; each sub-reference voltage circuit includes: a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; wherein... The gate of the sixth PMOS transistor is connected to the gate of the fifth PMOS transistor in the bias circuit. The source of the sixth PMOS transistor is connected to the power supply line. The drain of the sixth PMOS transistor is connected to the drain and gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor. The source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor. The drain of the sixth NMOS transistor serves as the output of the sub-reference voltage circuit. Wherein, N is a positive integer.

2. The reset circuit according to claim 1, characterized in that, The second, third, and fourth NMOS transistors all operate in the saturation region.

3. The reset circuit according to claim 1, characterized in that, The first-stage sub-reference voltage circuit, located at the first position among the N sub-reference voltage circuits, has its source of the sixth NMOS transistor connected to ground potential; the i-th-stage sub-reference voltage circuit, located at other positions among the N sub-reference voltage circuits, has its source of the sixth NMOS transistor connected to the output of the (i+1)-th stage sub-reference voltage circuit; wherein, 1 <i≤N。 4. The reset circuit according to claim 1 or 3, characterized in that, The fifth and sixth NMOS transistors operate in the subthreshold region.

5. The reset circuit according to claim 1, characterized in that, The power supply voltage sampling circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a diode; wherein, The sources of the seventh and ninth PMOS transistors are connected to the power supply. The drains of the seventh and ninth PMOS transistors are connected to the source of the eighth PMOS transistor and the drain of the diode. The gate of the seventh PMOS transistor is connected to the gate and drain of the eighth PMOS transistor and the drain of the seventh NMOS transistor. The gate of the ninth PMOS transistor is connected to the output signal of the reset circuit. The gates of the seventh and eighth NMOS transistors are connected to the gate of the fourth NMOS transistor in the bias circuit. The sources of the seventh and eighth NMOS transistors are connected to ground potential. The drain of the eighth NMOS transistor is connected to the negative terminal of the diode and serves as the output of the power supply voltage sampling circuit, which is connected to the comparator circuit.

6. The reset circuit according to claim 5, characterized in that, The seventh NMOS transistor and the eighth NMOS transistor are connected to the gate of the fourth NMOS transistor in the bias circuit to form a current mirror structure, which provides current bias for the eighth PMOS transistor and the branch where the diode is located, respectively.

7. The reset circuit according to claim 1, characterized in that, The power supply voltage sampling circuit also includes a hysteresis structure; wherein... The hysteresis structure is used to generate hysteresis when the reset signal switches.

8. The reset circuit according to claim 1, characterized in that, The reference voltage generated by the reference voltage circuit and the power supply voltage sampling signal output by the power supply voltage sampling circuit both have a positive temperature coefficient.

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