Battery protection chip and test system

Abstract

The present application relates to the field of battery testing technology, and provides a battery protection chip and a testing system. The chip includes: a chip power supply terminal connected to a first terminal of a first test mode signal generating circuit, a battery voltage positive sampling terminal connected to a second terminal of the first test mode signal generating circuit, and an output terminal of the first test mode signal generating circuit connected to a first input terminal of a driving circuit; a battery voltage positive sampling terminal connected to a first terminal of a second test mode signal generating circuit, a battery voltage negative sampling terminal connected to a second terminal of the second test mode signal generating circuit, and an output terminal of the second test mode signal generating circuit connected to a second input terminal of the driving circuit; an output terminal of a timer connected to a third input terminal of the driving circuit, an input terminal of the timer connected to a timing signal output terminal of the driving circuit, and a control mode total signal output terminal of the driving circuit used to connect to a chip test mode signal terminal.

Description

Technical Field

[0001] The present application relates to the technical field of battery testing, and in particular to a battery protection chip and a testing system. Background Art

[0002] In multi-cell battery protection chips, there are often many functional items, mainly including open and short circuit, power consumption, overcharge protection, overcharge recovery, over-discharge protection, over-discharge recovery, overcurrent protection, short circuit protection, overcurrent recovery, charging overcurrent protection, charging overcurrent recovery, disconnection protection, temperature protection, temperature recovery, etc., and the detection and judgment delays of various functions involved are very long. The maximum test time for a single functional item can reach tens of seconds, resulting in a long time for normal chip testing, low test efficiency, high test cost, and extremely slow mass production output, affecting product delivery and other aspects.

[0003] like Figure 1 As shown in the figure, it is a general n-cell battery protection chip system, VCC is the chip power supply terminal, VC1~VCn (n>=2) is the battery voltage sampling terminal, VSS is the chip ground, VM is the charger load detection terminal, RTV and RTS are temperature detection terminals, VIN is the charge and discharge current detection terminal, CO is the charge control terminal, and DO is the discharge control terminal. In order to shorten the test time, the chip is usually designed with the original functional terminal of the chip for expansion, so that the chip enters the test mode. After the chip enters the test mode, the delay of each function will be shortened from tens, hundreds or even thousands of milliseconds in the original design to a few milliseconds, and the overall test time is greatly reduced. Therefore, it is extremely important to design a reliable test mode.

[0004] The principle of designing the test mode is to power on the chip without affecting the normal functional application, so that the chip enters the test mode. In the traditional solution, the negative voltage of the VM detection terminal is used for judgment to generate the test mode control signal, such as Figure 2 This design method is relatively simple, but the inventors have found that in certain application environments, such as under extreme conditions of high current charging, that is, charging overcurrent state, there is a possibility of misjudgment. VM will detect a large negative pressure, and the chip will mistakenly enter the test mode, resulting in abnormal delay of charging overcurrent protection. For example, after entering the test mode using this method, due to the effect of the charger detection function, the negative pressure at the VM end causes the chip to over-discharge without recovery value, and other functional tests are affected. It can be seen that the traditional test scheme has limitations. Summary of the invention

[0005] The present application provides a battery protection chip and a test system for solving the limitation problem of the traditional solution of misjudging the entry into the test mode.

[0006] A battery protection chip comprises a chip power supply terminal, a battery voltage positive sampling terminal, a battery voltage negative sampling terminal, a first test mode signal generating circuit, a second test mode signal generating circuit, a test mode total signal driving circuit and a timer;

[0007] The chip power supply terminal is connected to the first terminal of the first test mode signal generating circuit, the battery voltage positive sampling terminal is connected to the second terminal of the first test mode signal generating circuit, and the output terminal of the first test mode signal generating circuit is connected to the first input terminal of the test mode total signal driving circuit;

[0008] The battery voltage positive sampling terminal is connected to the first terminal of the second test mode signal generating circuit, the battery voltage negative sampling terminal is connected to the second terminal of the second test mode signal generating circuit, and the output terminal of the second test mode signal generating circuit is connected to the second input terminal of the test mode total signal driving circuit;

[0009] The output end of the timer is connected to the third input end of the test mode total signal driving circuit, the input end of the timer is connected to the timing signal output end of the test mode total signal driving circuit, and the control mode total signal output end of the test mode total signal driving circuit is used to connect to the chip test mode signal end.

[0010] In one embodiment, the first test mode signal generating circuit includes a first resistor, a second resistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor and a positive phase Schmitt trigger;

[0011] One end of the first resistor serves as the first end of the first test mode signal generating circuit, the other end of the first resistor is connected to the drain of the first PMOS tube, the gate and source of the first PMOS tube are connected together and then connected to the drain of the second PMOS tube, the gate and drain of the second PMOS tube are connected together and then connected to the drain of the third PMOS tube, and the gate and source of the third PMOS tube are connected together and then connected to the drain of the fourth PMOS tube;

[0012] One end of the second resistor serves as the second end of the first test mode signal generating circuit, the other end of the second resistor is connected to the gate of the fourth PMOS tube, the source of the fourth PMOS tube is connected to the drain of the first NMOS tube, the gate of the first NMOS tube is connected to a low voltage power supply voltage, the source of the first NMOS tube, the drain of the second NMOS tube and the output end of the positive phase Schmitt trigger are connected in common, the gate of the second NMOS tube is connected to a bias voltage, and the source of the second NMOS tube is connected to a chip ground terminal;

[0013] The output end of the positive phase Schmitt trigger serves as the output end of the first test mode signal generating circuit.

[0014] In one embodiment, the second test mode signal generating circuit includes a third resistor, a fourth resistor, a voltage comparator, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a first inverter;

[0015] One end of the third resistor and the fourth resistor are connected together and then connected to the negative input end of the voltage comparator, the positive input end of the voltage comparator is connected to the reference voltage end, and the output end of the voltage comparator is connected to the gate of the fifth PMOS tube; the other end of the third resistor and the drain of the fifth PMOS tube are connected together as the first end of the second test mode signal generating circuit, and the other end of the fourth resistor serves as the second end of the second test mode signal generating circuit;

[0016] The source of the fifth PMOS tube is connected to the drain of the third NMOS tube, the gate of the third NMOS tube is connected to the low-voltage power supply voltage, the source of the third NMOS tube, the drain of the fourth NMOS tube and the input end of the first inverter are connected in common, the gate of the fourth NMOS tube is connected to the bias voltage, the source of the fourth NMOS tube is connected to the chip ground terminal, and the output end of the first inverter serves as the output end of the second test mode signal generating circuit.

[0017] In one embodiment, the test mode total signal driving circuit includes a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate, a second NAND gate, an XOR gate, a NOR gate, a D flip-flop and an oscillator;

[0018] The R terminal of the D flip-flop and the input terminal of the second inverter are connected together as the first input terminal of the test mode total signal driving circuit, and the output terminal of the second inverter is connected to the first output terminal of the NOR gate;

[0019] The input end of the third inverter and the second input end of the NOR gate are connected together as the second input end of the test mode total signal driving circuit, the output end of the third inverter, the first input end of the first NAND gate and the first input end of the XOR gate are connected together, and the second input end of the first NAND gate serves as the third input end of the test mode total signal driving circuit;

[0020] The output end of the first NAND gate is connected to the input end of the fourth inverter, the output end of the fourth inverter is connected to the clock end of the D flip-flop, the positive Q end of the D flip-flop is connected to the second input end of the XOR gate and serves as the chip test mode signal end of the test mode total signal driving circuit, and the D end of the D flip-flop is connected to the power supply end;

[0021] The output end of the XOR gate is connected to the first input end of the second NAND gate, the output end of the NOR gate is connected to the second input end of the second NAND gate, the output end of the second NAND gate is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the oscillator, and the output end of the oscillator serves as the timing signal output end of the test mode total signal driving circuit.

[0022] A test system comprises a test battery and the battery protection chip.

[0023] In the scheme provided by the present application, the chip can be controlled to enter the test mode by powering on the three terminals of the chip, namely, VCC, VC1 and VC2. First, the voltage between VCC and VC1 is increased to greater than 5V, so that the first test signal 1 inside the chip is valid. Then, a voltage higher than the overcharge value is given between VC1 and VC2, so that the second test mode signal is generated inside the chip. At this time, the internal timer is triggered to start timing. However, after the timing reaches the designed Ttm delay, the total signal of the control test mode is valid. Finally, the chip test mode end is connected through the total signal of the test mode to make the chip enter the test mode. The present application avoids the possibility of misjudgment under extreme conditions such as high current charging, that is, the charging overcurrent state, and can make the chip enter the test mode effectively and accurately, greatly shortening the test time, improving the test efficiency, and reducing the test cost. It not only ensures that the chip is completely undisturbed during normal application, effectively preventing the abnormality of false triggering to enter the test mode, but also does not cause the negative pressure at the VM end of the chip to cause the chip to over-discharge without recovery value, and other situations that affect the functional test. It can ensure that after the chip-level test enters the test mode, all functional items can be fully covered and tested, and the application is safer and more reliable, effectively improving the quality of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0025] Figure 1 A schematic diagram of the structure of a conventional n-cell battery protection chip system;

[0026] Figure 2 A schematic diagram of a control circuit for a chip entering a test mode in a traditional solution;

[0027] Figure 3 A schematic diagram of external connections of a battery protection chip provided in this application;

[0028] Figure 4 A schematic diagram of the structure of a battery protection chip provided in this application;

[0029] Figure 5 A schematic diagram of a structure of a first test mode signal generating circuit provided in an embodiment of the present application;

[0030] Figure 6 A schematic diagram of a structure of a second test mode signal generating circuit provided in an embodiment of the present application;

[0031] Figure 7 A schematic diagram of the connection between the test mode total signal driving circuit and the timer provided in an embodiment of the present application;

[0032] Figure 8 A signal timing diagram of a battery protection chip entering a test mode provided in the present application. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0034] In order to illustrate the technical solution of the present application, a specific embodiment is provided below for illustration.

[0035] like Figure 3 and Figure 4 As shown, Figure 3 This is a schematic diagram of the external connection of a battery protection chip provided in this application. Figure 4 1 is a schematic diagram of the structure of a battery protection chip provided by the present application, including a chip power supply terminal VCC, a battery voltage sampling terminal (VC1~VCn (n>=2)), the battery voltage sampling terminal includes a battery voltage positive sampling terminal and a battery voltage negative sampling terminal, wherein, for ease of description, all embodiments of the present application are described by taking the chip highest battery voltage positive sampling terminal VC1 and the chip highest battery voltage negative sampling terminal VC2 as examples, a first test mode signal generating circuit 101, a second test mode signal generating circuit 102, a test mode total signal driving circuit 103 and a timer 104;

[0036] The chip power supply terminal VCC is connected to the first terminal of the first test mode signal generating circuit 101, the battery voltage positive sampling terminal VC1 is connected to the second terminal of the first test mode signal generating circuit 101, and the output terminal of the first test mode signal generating circuit 101 is connected to the first input terminal of the test mode total signal driving circuit 103;

[0037] The battery voltage positive sampling terminal VC1 is connected to the first terminal of the second test mode signal generating circuit 102, the battery voltage negative sampling terminal VC2 is connected to the second terminal of the second test mode signal generating circuit 102, and the output terminal of the second test mode signal generating circuit 102 is connected to the second input terminal of the test mode total signal driving circuit 103;

[0038] The output end of the timer 104 is connected to the third input end of the test mode total signal driving circuit 103, the input end of the timer 104 is connected to the timing signal output end of the test mode total signal driving circuit 103, and the control mode total signal output end of the test mode total signal driving circuit 103 is used to connect to the chip test mode signal end.

[0039] The first test mode signal generating circuit 101 is controlled by the voltage between the chip power supply terminal VCC and the battery voltage positive sampling terminal VC1 to output the first test mode signal, and the first test mode signal is a high level (1) or a low level (0). Specifically, for example, taking the preset voltage as 5V as an example, when VCC-VC1 is less than 5V, the first test mode signal output by the first test mode signal generating circuit 101 is a low level 0, and when VCC-VC1 is greater than or equal to 5, the first test mode signal output by the first test mode signal generating circuit 101 is a high level 1.

[0040] In a specific embodiment, Figure 5 As shown, an embodiment of the present application provides a specific implementation of a first test mode signal generating circuit 101, wherein the first test mode signal generating circuit 101 includes a first resistor RQ, a second resistor R2, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a first NMOS transistor NM1, a second NMOS transistor NM2 and a positive phase Schmitt trigger schmitt;

[0041] One end of the first resistor R1 serves as the first end of the first test mode signal generating circuit 101, the other end of the first resistor R1 is connected to the drain of the first PMOS transistor PM1, the gate and source of the first PMOS transistor PM1 are connected together and then connected to the drain of the second PMOS transistor PM2, the gate and drain of the second PMOS transistor PM2 are connected together and then connected to the drain of the third PMOS transistor PM3, the gate and source of the third PMOS transistor PM3 are connected together and then connected to the drain of the fourth PMOS transistor PM4;

[0042] One end of the second resistor R2 serves as the second end of the first test mode signal generating circuit 101, and the other end of the second resistor R2 is connected to the gate of the fourth PMOS tube PM4, the source of the fourth PMOS tube PM4 is connected to the drain of the first NMOS tube NM1, the gate of the first NMOS tube NM1 is connected to the low-voltage power supply voltage V_5V, the source of the first NMOS tube NM1, the drain of the second NMOS tube NM2 and the output end of the positive phase Schmitt trigger schmitt are connected in common, the gate of the second NMOS tube NM2 is connected to the bias voltage VBN, and the source of the second NMOS tube NM2 is connected to the chip ground terminal VSS; wherein, exemplarily, the low-voltage power supply voltage V_5V can be a low-voltage power supply voltage inside the chip, and the bias voltage VBN can be a bias voltage inside the chip.

[0043] The output end of the positive phase Schmitt trigger serves as the output end of the first test mode signal generating circuit 101 .

[0044] In this embodiment, the first resistor R1 and the second resistor R2 are current limiting protection resistors, which are used to prevent the voltage between the chip power supply terminal VCC and the battery voltage positive sampling terminal VC1 from being too high and damaging the internal components of the chip. The PMO tubes PM1 to PM3 are voltage control MOS, which are used to adjust the judgment voltage between the chip power supply terminal VCC and the battery voltage positive sampling terminal VC1. It should be noted that Figure 5 The example shown uses three PMOS tubes as the adjustment voltage. In actual applications, other numbers may be set, and there is no specific limitation.

[0045] V_5V is the low voltage power supply voltage inside the chip, and VBN is the bias voltage inside the chip, which is used to generate a pull-down bias current. Specifically, in a normal state, when VCC-VC1<5V, the fourth PMOS tube PM4 remains off, and the drain terminal of the second NMOS tube NM2 is pulled down to the chip ground terminal VSS by the bias current controlled by the bias voltage VBN, and after passing through the positive phase Schmitt trigger schmitt, the first test mode signal 1 is output as a low level 0; conversely, when VCC-VC1 is greater than or equal to 5V, the fourth PMOS tube PM4 is turned on, so the drain terminal of the second NMOS tube NM2 is pulled up to a high level and clamped, and after passing through the schmitt positive phase Schmitt trigger, the first test mode signal output becomes a high level 1.

[0046] It should be noted that the above Figure 5 The embodiments shown here are only for illustrative purposes. Based on the above circuit structure, there may be other transformation structures, such as changing the type, quantity or circuit mode of the switch tube device, etc., which are not specifically limited.

[0047] The second test mode signal generating circuit 102 is controlled by the voltage between the battery voltage positive sampling terminal VC1 and the battery voltage negative sampling terminal VC2 to output the second test mode signal, and the first test mode signal is a high level (1) or a low level (0). Specifically, exemplarily, when the voltage between the battery voltage positive sampling terminal VC1 and the battery voltage negative sampling terminal VC2 is a normal voltage, the second test mode signal output by the second test mode signal generating circuit 102 is a high level 1, and when the voltage between the battery voltage positive sampling terminal VC1 and the battery voltage negative sampling terminal VC2 is higher than the battery overcharge value, the second test mode signal output by the second test mode signal generating circuit 102 is a low level 0.

[0048] like Figure 6 As shown, the second test mode signal generating circuit 102 includes a third resistor R3, a fourth resistor R4, a voltage comparator COMP, a fifth PMOS transistor PM5, a third NMOS transistor NM3, a fourth NMOS transistor NM4 and a first inverter inv1;

[0049] One end of the third resistor R3 and the fourth resistor R4 are connected to the negative input end of the voltage comparator COMP. The positive input end of the voltage comparator COMP is connected to a reference voltage end, which is used to provide a reference voltage Vref. Figure 6In the embodiment, a reference voltage module is provided, which is connected in parallel between VC1 and VC2, and the output end of the voltage comparator COMP is connected to the gate of the fifth PMOS transistor PM5; the other end of the third resistor R3 and the drain of the fifth PMOS transistor PM5 are connected together as the first end of the second test mode signal generating circuit 102, and the other end of the fourth resistor R4 is used as the second end of the second test mode signal generating circuit 102;

[0050] The source of the fifth PMOS tube PM5 is connected to the drain of the third NMOS tube NM3, the gate of the third NMOS tube NM3 is connected to the low-voltage power supply voltage V_5V, the source of the third NMOS tube NM3, the drain of the fourth NMOS tube NM4 and the input end of the first inverter inv1 are connected in common, the gate of the fourth NMOS tube NM4 is connected to the bias voltage VBN, the source of the fourth NMOS tube NM4 is connected to the chip ground terminal VSS, and the output end of the first inverter inv1 serves as the output end of the second test mode signal generating circuit 102, wherein, exemplarily, the low-voltage power supply voltage V_5V can be a low-voltage power supply voltage inside the chip, and the bias voltage VBN can be a bias voltage inside the chip.

[0051] The third resistor R3 and the fourth resistor R4 are voltage-dividing resistors for reducing the voltage between the battery voltage positive sampling terminal VC1 and the battery voltage negative sampling terminal VC2. Meanwhile, the reference voltage module is used to generate a reference voltage Vref referring to the battery voltage negative sampling terminal VC2. When the voltage between VC1 and VC2 is a normal voltage, that is, the voltage divided by the third resistor R3 and the fourth resistor R4 is less than Vref, the comparator COMP outputs 1, the fifth PMOS tube PM5 is turned off, so the drain terminal of the fourth NMOS tube NM4 is pulled down to the chip ground terminal VSS by the bias current controlled by the programming voltage VBN, and after passing through the first inverter inv1, the second test mode signal is output as a high level 1; when the voltage of the battery voltage positive sampling terminal VC1 and the battery voltage negative sampling terminal VC2 is higher than the battery overcharge value, that is, the voltage divided by the third resistor R3 and the fourth resistor R4 is greater than the reference voltage Vref, the comparator COMP outputs 0, so that the fifth PMOS tube PM5 is turned on, so the drain terminal of the fourth NMOS tube NM4 is pulled up to a high level and clamped, and after passing through the first inverter inv1, the second test mode signal is output as a low level 0.

[0052] It should be noted that the above Figure 5 The embodiments shown here are only for illustrative purposes. Based on the above circuit structure, there may be other transformation structures, such as the voltage divider circuit, changing the type or quantity of the switch tube devices, or replacing other circuit methods, etc., without specific limitation.

[0053] The test mode total signal driving circuit 103 is controlled by the first test mode signal, the second test mode signal and the output signal of the timer, and outputs the test mode total signal, which is a high level (1) or a low level (0). In this embodiment, when the first test mode signal 1 is a low level 0, the test mode total signal output is a low level 0, and when the first test mode signal 1 is a high level 1, when the second test mode signal is a low level 0, the test mode total signal driving circuit 103 outputs a timing signal to drive the timer 104 to work, and after the timer 104 delays the preset time length Ttm, the test mode total signal flips from a low level 0 to a high level 1, triggering the chip to enter the test mode.

[0054] In one embodiment, if Figure 7 As shown, an embodiment of the present application provides a test mode total signal driving circuit, which includes a second inverter inv2, a third inverter inv3, a fourth inverter inv4, a fifth inverter inv5, a first NAND gate Nand2, a second NAND gate Nand2_2, an XOR gate xor2, a NOR gate nor2, a D flip-flop and an oscillator;

[0055] The R terminal of the D flip-flop and the input terminal of the second inverter inv2 are connected together as the first input terminal of the test mode total signal driving circuit 103, and the output terminal of the second inverter inv2 is connected to the first output terminal of the NOR gate nor2;

[0056] The input end of the third inverter inv3 and the second input end of the NOR gate nor2 are connected together as the second input end of the test mode total signal driving circuit 103, the output end of the third inverter inv3, the first input end of the first NAND gate Nand2 and the first input end of the XOR gate xor2 are connected together, and the second input end of the first NAND gate Nand2 serves as the third input end of the test mode total signal driving circuit 103;

[0057] The output end of the first NAND gate Nand2 is connected to the input end of the fourth inverter inv4, the output end of the fourth inverter inv4 is connected to the clock end CLK of the D flip-flop, the positive Q end of the D flip-flop is connected to the second input end of the XOR gate xor2 and serves as the chip test mode signal end of the test mode total signal driving circuit 103, the chip test mode signal end is used to output the test mode total signal, the D end of the D flip-flop is connected to the power supply end VDD, and the power supply end VDD can be the voltage provided inside the chip.

[0058] The output end of the XOR gate xor2 is connected to the first input end of the second NAND gate Nand2_2, the output end of the NOR gate nor2 is connected to the second input end of the second NAND gate Nand2_2, the output end of the second NAND gate Nand2_2 is connected to the input end of the fifth inverter inv5, the output end of the fifth inverter inv5 is connected to the input end of the oscillator, and the output end of the oscillator serves as the timing signal output end of the test mode total signal driving circuit 103, and is used to output a timing signal.

[0059] When the first test mode signal is low level 0, the directly controlled D flip-flop is reset, and the output terminal positive Q terminal outputs low level 0, that is, the total signal output of the test mode is low level 0. When the first test mode signal is high level 1, the directly controlled D flip-flop is valid. At this time, when the second test mode signal is low level 0, the first and second test mode signals together make the output of the NOR gate nor2 high level 1, and the output of the XOR gate xor2 is high level 1, so the second NAND gate nand2_2 outputs low level 0, and outputs a timing signal after passing through the fifth inverter inv5, which is used to control the operation of the oscillator and the timer. When the timer times to the delay time Ttm for entering the test mode, the clock terminal CLK of the D flip-flop is valid, triggering the output level of the positive Q terminal to flip from low level 0 to high level 1, that is, the total signal of the test mode flips to high level 1, so the chip enters the test mode.

[0060] like Figure 8 For easier understanding of the working sequence, please refer to Figure 5 As shown, Figure 5 For the working timing diagram of each signal in this application, first, it must be ensured that the first test mode signal changes to high level 1 first, so that the D flip-flop is effective. Secondly, the time for the second test mode signal to maintain high level 1 must be greater than the delay time Ttm to ensure that there is enough time to enter the test mode. When both conditions are met, when the timing reaches Ttm, the test mode total signal is sent to enter the test mode. After entering the test mode, the second test mode signal is reset to a normal low level.

[0061] It can be seen that in the embodiment of the present application, Figure 3 As shown, power is supplied only through the original chip terminals VCC, VC1 and VC2 (such as Figure 3The chip can be controlled to enter the test mode by adding the voltage between VCC and VC1 to greater than 5V, so that the first test signal 1 inside the chip is valid. Then, a voltage higher than the overcharge value is applied between VC1 and VC2, so that the second test mode signal is generated inside the chip. At this time, the internal timer 104 is triggered to start timing, but after the timing reaches the designed Ttm delay, the total signal of the control test mode is valid. Finally, the chip test mode end is connected through the total signal of the test mode to enter the test mode. The present application avoids the possibility of misjudgment under extreme conditions such as high current charging, that is, the charging overcurrent state, and can make the chip enter the test mode effectively and accurately, greatly shortening the test time, improving the test efficiency, and reducing the test cost. It not only ensures that the chip is completely undisturbed during normal use, effectively preventing the abnormality of false triggering to enter the test mode, but also does not cause the negative pressure at the VM end of the chip to cause the chip to over-discharge without recovery value, and other situations that affect the functional test. It can ensure that after the chip-level test enters the test mode, all functional items can be fully covered and tested, making the application safer and more reliable, and effectively improving the quality of the product.

[0062] In one embodiment, a test system is further provided, comprising a test battery and the battery protection chip as described in the above embodiment.

[0063] It should be noted that, based on the battery protection chip provided in the embodiment of the present application, the control method of the test mode provided is suitable for battery protection chips with n>=2 cells. The judgment voltage 5V for generating the first test mode signal in the above embodiment is not limited to 5V, and can be designed to be any voltage according to different actual applications. There is no specific limitation. Different voltage judgments can be achieved by adjusting the number of PMOS between VCC and VC1. In addition, the initial logic levels in the above test modes are not limited to the initial high or low, and can be changed to the initial opposite logic in the present embodiment by adding logic gates. There is no specific limitation.

[0064] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A battery protection chip, characterized in that: It includes a chip power supply terminal, a battery voltage positive sampling terminal, a battery voltage negative sampling terminal, a first test mode signal generating circuit, a second test mode signal generating circuit, a test mode total signal driving circuit and a timer; The chip power supply terminal is connected to the first terminal of the first test mode signal generating circuit, the battery voltage positive sampling terminal is connected to the second terminal of the first test mode signal generating circuit, and the output terminal of the first test mode signal generating circuit is connected to the first input terminal of the test mode total signal driving circuit; The battery voltage positive sampling terminal is connected to the first terminal of the second test mode signal generating circuit, the battery voltage negative sampling terminal is connected to the second terminal of the second test mode signal generating circuit, and the output terminal of the second test mode signal generating circuit is connected to the second input terminal of the test mode total signal driving circuit; The output end of the timer is connected to the third input end of the test mode total signal driving circuit, the input end of the timer is connected to the timing signal output end of the test mode total signal driving circuit, and the control mode total signal output end of the test mode total signal driving circuit is used to connect to the chip test mode signal end; The first test mode signal generating circuit is controlled by the voltage between the chip power supply terminal and the battery voltage positive sampling terminal to output the first test mode signal, and the second test mode signal generating circuit is controlled by the voltage between the battery voltage positive sampling terminal and the battery voltage negative sampling terminal to output the second test mode signal; When the voltage between the chip power supply terminal and the battery voltage positive sampling terminal is added to be greater than the preset voltage, the first test mode signal output by the first test mode signal generating circuit is valid, and a voltage higher than the overcharge value is given between the battery voltage positive sampling terminal and the battery voltage negative sampling terminal, so that the second test mode signal generating circuit generates a second test mode signal to trigger the internal timer to start timing. When the timing reaches the Ttm delay, the control test mode total signal is valid, and finally the chip test mode terminal is connected through the test mode total signal.

2. The battery protection chip according to claim 1, characterized in that: The first test mode signal generating circuit includes a first resistor, a second resistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor and a positive phase Schmitt trigger; One end of the first resistor serves as the first end of the first test mode signal generating circuit, the other end of the first resistor is connected to the drain of the first PMOS tube, the gate and source of the first PMOS tube are connected together and then connected to the drain of the second PMOS tube, the gate and drain of the second PMOS tube are connected together and then connected to the drain of the third PMOS tube, and the gate and source of the third PMOS tube are connected together and then connected to the drain of the fourth PMOS tube; One end of the second resistor serves as the second end of the first test mode signal generating circuit, the other end of the second resistor is connected to the gate of the fourth PMOS tube, the source of the fourth PMOS tube is connected to the drain of the first NMOS tube, the gate of the first NMOS tube is connected to a low voltage power supply voltage, the source of the first NMOS tube, the drain of the second NMOS tube and the output end of the positive phase Schmitt trigger are connected in common, the gate of the second NMOS tube is connected to a bias voltage, and the source of the second NMOS tube is connected to a chip ground terminal; The output end of the positive phase Schmitt trigger serves as the output end of the first test mode signal generating circuit.

3. The battery protection chip according to claim 1, characterized in that: The second test mode signal generating circuit includes a third resistor, a fourth resistor, a voltage comparator, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a first inverter; One end of the third resistor and the fourth resistor are connected together and then connected to the negative input end of the voltage comparator, the positive input end of the voltage comparator is connected to the reference voltage end, and the output end of the voltage comparator is connected to the gate of the fifth PMOS tube; the other end of the third resistor and the drain of the fifth PMOS tube are connected together as the first end of the second test mode signal generating circuit, and the other end of the fourth resistor serves as the second end of the second test mode signal generating circuit; The source of the fifth PMOS tube is connected to the drain of the third NMOS tube, the gate of the third NMOS tube is connected to the low-voltage power supply voltage, the source of the third NMOS tube, the drain of the fourth NMOS tube and the input end of the first inverter are connected in common, the gate of the fourth NMOS tube is connected to the bias voltage, the source of the fourth NMOS tube is connected to the chip ground terminal, and the output end of the first inverter serves as the output end of the second test mode signal generating circuit.

4. The battery protection chip according to any one of claims 1 to 3, characterized in that: The test mode total signal driving circuit comprises a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate, a second NAND gate, an XOR gate, a NOR gate, a D flip-flop and an oscillator; The R terminal of the D flip-flop and the input terminal of the second inverter are connected together as the first input terminal of the test mode total signal driving circuit, and the output terminal of the second inverter is connected to the first output terminal of the NOR gate; The input end of the third inverter and the second input end of the NOR gate are connected together as the second input end of the test mode total signal driving circuit, the output end of the third inverter, the first input end of the first NAND gate and the first input end of the XOR gate are connected together, and the second input end of the first NAND gate serves as the third input end of the test mode total signal driving circuit; The output end of the first NAND gate is connected to the input end of the fourth inverter, the output end of the fourth inverter is connected to the clock end of the D flip-flop, the positive Q end of the D flip-flop is connected to the second input end of the XOR gate and serves as the chip test mode signal end of the test mode total signal driving circuit, and the D end of the D flip-flop is connected to the power supply end; The output end of the XOR gate is connected to the first input end of the second NAND gate, the output end of the NOR gate is connected to the second input end of the second NAND gate, the output end of the second NAND gate is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the oscillator, and the output end of the oscillator serves as the timing signal output end of the test mode total signal driving circuit.

5. A testing system, characterized in that: It comprises a test battery and a battery protection chip as described in any one of claims 1 to 4.

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