Storage device and method for manufacturing the same

Abstract

The present disclosure provides a memory device and a preparation method thereof, and relates to the field of semiconductor technology. The memory device includes: a substrate; a memory cell array on the substrate, including a plurality of memory cells, wherein each memory cell includes: a left stack and a right stack arranged at intervals in the horizontal direction, the left stack and the right stack each include a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer and a second NMOS layer stacked sequentially on the substrate, the PMOS layer, the first NMOS layer and the second NMOS layer each include a first source / drain layer, a channel layer and a second source / drain layer stacked vertically, and the channel layer is laterally recessed relative to the first source / drain layer and the second source / drain layer; a gate stack, which is located between the first source / drain layer and the second source / drain layer in the vertical direction, and is disposed on opposite sides of the channel layer to embed the lateral recess of the channel layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a memory device and a method for preparing the same. Background Art

[0002] As semiconductor devices continue to miniaturize, it is increasingly difficult to manufacture high-density interconnect structures because it is difficult to reduce the size in the lateral direction. In addition, in order to increase the integration level, multiple layers of devices can be stacked. Based on this, it is desirable to be able to set interconnections for such stacked devices in a flexible manner. Summary of the invention

[0003] In view of this, an object of the present disclosure is at least partially to provide a memory device and a method for manufacturing the same that can reduce standby leakage without increasing the device threshold voltage.

[0004] According to one aspect of the present disclosure, a memory device is provided, comprising: a substrate; a memory cell array on the substrate, comprising a plurality of memory cells, wherein each memory cell comprises: a left stack and a right stack arranged at intervals in a horizontal direction, the left stack and the right stack each comprising a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer and a second NMOS layer sequentially stacked on the substrate, the PMOS layer, the first NMOS layer and the second NMOS layer each comprising a first source / drain layer, a channel layer and a second source / drain layer stacked vertically, the channel layer being laterally recessed relative to the first source / drain layer and the second source / drain layer; and a gate stack, which is located between the first source / drain layer and the second source / drain layer in a vertical direction and is disposed on opposite sides of the channel layer to embed the lateral recess of the channel layer.

[0005] According to another aspect of the present disclosure, a method for preparing a memory device is provided, comprising: forming a left stack and a right stack arranged in a horizontal direction on a substrate, wherein the left stack and the right stack both comprise a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer and a second NMOS layer stacked in sequence, wherein the PMOS layer, the first NMOS layer and the second NMOS layer both comprise a first source / drain layer, a channel layer and a second source / drain layer stacked vertically, wherein the channel layer is laterally recessed relative to the first source / drain layer and the second source / drain layer; sequentially depositing a gate dielectric layer and a p-type gate conductor layer in the lateral recess of the channel layer; depositing SiO2 at the bottom of the left stack and the right stack, then etching the SiO2 and stopping at a first preset height to form a first spacer; etching the p-type gate conductor layer at positions corresponding to the first NMOS layer and the second NMOS layer, and depositing an n-type gate conductor layer at positions corresponding to the etched p-type gate conductor layer; etching the first spacer to form a memory cell, wherein the memory device comprises a memory cell array of a plurality of memory cells.

[0006] According to another aspect of the present disclosure, an electronic device is provided, comprising the above-mentioned storage device.

[0007] Compared with the prior art, the memory device and the preparation method thereof provided by the present disclosure have at least the following beneficial effects: the memory device uses a 6T SRAM unit as the smallest memory unit, has a smaller number of transistors, simplifies the computer's storage and computing structure, saves computing resources, and improves computing progress and efficiency.

[0008] In addition, for the vertical stack of semiconductor devices, a sidewall interconnect structure adjacent to it in the lateral direction can be provided. For several layers of devices, one mask layer can be used, thereby reducing the number of photolithography steps in the manufacturing process and reducing the manufacturing cost. In addition, the three-dimensional structure allows more space for the interconnection between devices, and thus can have low resistance and high bandwidth. Due to the presence of the sidewall interconnect structure, the semiconductor device can have a lead terminal, so the manufacture of the semiconductor device can be separated from the manufacture of the metallized stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1 The circuit diagram of a 6T SRAM cell is schematically shown;

[0011] Figures 2 to 29 The cross-sectional views of the method for preparing a memory device according to an embodiment of the present disclosure at different stages are schematically shown. In these drawings:

[0012] Figure 2 schematically shows a cross-sectional view of forming a stack on a substrate;

[0013] FIG. 3( a ) schematically shows a top view of a photoresist patterning region; FIG. 3( b ) is a cross-sectional view along line AA′ formed according to FIG. 3( a );

[0014] FIG. 4( a ) schematically shows a top view of a photoresist patterning region; FIG. 4( b ) is a cross-sectional view along line AA′ formed according to FIG. 4( a );

[0015] FIG5(a) schematically shows a top view of a photoresist patterning region; FIG5(b) is a cross-sectional view along line 11′ formed according to FIG5(a);

[0016] FIG6(a) schematically shows a top view of a photoresist patterning region; FIG6(b) is a cross-sectional view along line 11′ formed according to FIG6(a); FIG6(c) is a cross-sectional view along line AA′ formed according to FIG6(a);

[0017] Figure 7 A cross-sectional view along line AA′ is schematically shown;

[0018] Figure 8 A cross-sectional view along line AA′ is schematically shown;

[0019] Fig. 9 A cross-sectional view along line AA′ is schematically shown;

[0020] Fig.10 A cross-sectional view along line AA′ is schematically shown;

[0021] Fig.11 A cross-sectional view along line AA′ is schematically shown;

[0022] Fig.12 A cross-sectional view along line AA′ is schematically shown;

[0023] Fig.13 A cross-sectional view along line AA′ is schematically shown;

[0024] Fig.14 A cross-sectional view along line AA′ is schematically shown;

[0025] Fig.15 A cross-sectional view along line AA′ is schematically shown;

[0026] Fig.16 A cross-sectional view along line AA′ is schematically shown;

[0027] FIG. 17( a ) schematically shows a top view of a photoresist patterning region; FIG. 17( b ) is a cross-sectional view along line AA′ formed according to FIG. 17( a ); and FIG. 17( c ) is a cross-sectional view along line BB′ formed according to FIG. 17( a );

[0028] FIG. 18( a ) schematically shows a top view of a photoresist patterning region; FIG. 18( b ) is a cross-sectional view along line AA′ formed according to FIG. 18( a ); FIG. 18( c ) is a cross-sectional view along line BB′ formed according to FIG. 18( a ); FIG. 18( d ) is a cross-sectional view along line CC′ formed according to FIG. 18( a );

[0029] FIG. 19( a ) schematically shows a top view of a photoresist patterning region; FIG. 19( b ) is a cross-sectional view along line AA′ formed according to FIG. 19( a ); FIG. 19( c ) is a cross-sectional view along line BB′ formed according to FIG. 19( a ); FIG. 19( d ) is a cross-sectional view along line CC′ formed according to FIG. 19( a );

[0030] Fig. 20 A cross-sectional view along line AA′ is schematically shown;

[0031] FIG. 21( a ) schematically shows a top view of a photoresist patterning region; FIG. 21( b ) is a cross-sectional view along line AA′ formed according to FIG. 21( a );

[0032] Fig. 22 A cross-sectional view along line AA′ is schematically shown;

[0033] FIG. 23( a ) schematically shows a top view of a photoresist patterning region; FIG. 23( b ) is a cross-sectional view along line BB′ formed according to FIG. 23( a );

[0034] Fig.24 A cross-sectional view along line BB′ is schematically shown;

[0035] Fig.25 A cross-sectional view along line BB′ is schematically shown;

[0036] Fig.26 A cross-sectional view along line BB′ is schematically shown;

[0037] FIG. 27( a ) schematically shows a top view of a photoresist patterning region; FIG. 27( b ) is a cross-sectional view along line BB′ formed according to FIG. 27( a );

[0038] FIG. 28( a ) schematically shows a top view of a photoresist patterning region; FIG. 28( b ) is a cross-sectional view along line BB′ formed according to FIG. 28( a );

[0039] Fig.29 A cross-sectional view along line BB' is schematically shown.

[0040] Description of reference numerals:

[0041] 1001-substrate; 10021-lower isolation layer; 10022-upper isolation layer;

[0042] 10031 / 10032 / 10033-first source / drain layer; 10051 / 10052 / 10053-channel defining layer;

[0043] 10071 / 10072 / 10073-second source / drain layer; 1009-hard mask layer;

[0044] 2001-first SiC layer; 2002-second SiC layer; 2003-third SiC layer;

[0045] 2004-fourth SiC layer; 2011-first SiO2 layer; 2012-second SiO2 layer;

[0046] 2013-third SiO2 layer; 2014-fourth SiO2 layer; 2015-fifth SiO2 layer;

[0047] 2016-sixth SiO2 layer; 2017-seventh SiO2 layer; 2018-eighth SiO2 layer;

[0048] 3001-first epitaxial layer; 3002-second epitaxial layer; 4001-gate dielectric layer;

[0049] 4002-p-type gate conductor layer; 4003-n-type gate conductor layer; 200-channel layer;

[0050] 301 - first spacer; 302 - second spacer; 5001 - first metal layer;

[0051] 5002 - second metal layer; 5003 - third metal layer; 5004 - fourth metal layer;

[0052] 5005 - fifth metal layer; 6001 - first contact portion; 6002 - second contact portion.

[0053] Throughout the drawings, the same or similar reference numerals denote the same or similar components. The drawings are not necessarily drawn to scale, and in particular, for the sake of clarity, the scale of the cross-sectional views is different from that of the top views. DETAILED DESCRIPTION

[0054] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0055] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0056] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0057] The present disclosure may be presented in various forms, some examples of which are described below. In the following description, various material selections are involved. In addition to considering its function (for example, semiconductor materials are used to form active areas and dielectric materials are used to form electrical isolation), the selection of materials also takes into account etching selectivity. In the following description, the required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when the following mentions etching a certain material layer, if it is not mentioned that other layers are also etched or it is not shown in the figure that other layers are also etched, then such etching can be selective, and the material layer can have etching selectivity relative to other layers exposed to the same etching recipe.

[0058] Figure 1 The circuit principle diagram of a 6T SRAM cell is schematically shown.

[0059] like Figure 1 As shown, the 6T SRAM cell includes transistors M1 to M6, where G in the figure represents the gate of the transistor, S represents the source of the transistor, and D represents the drain of the transistor. Among them, the source of transistor M2 and the source of transistor M4 are both connected to the power supply Vdd, the source of transistor M1 and the source of transistor M3 are both grounded GND, the drain of transistor M1 is connected to the drain of transistor M2, and the drain of transistor M3 is connected to the drain of transistor M4; the gate of transistor M1, the gate of transistor M2 and the drain of transistor M3 are connected, and the gate of transistor M3, the gate of transistor M4 and the drain of transistor M1 are connected.

[0060] The gate of transistor M5 and the gate of transistor M6 are both connected to word line WL (Word Line), and the drain of transistor M5 is connected to bit line The drain of transistor M6 is connected to the bit line BL (Bit Line), and the bit line BL and the bit line They are opposite signals to each other. The source of the transistor M5 is connected to the drain of the transistor M1 , and the source of the transistor M6 is connected to the drain of the transistor M3 .

[0061] Thus, the 6T SRAM cell is used as the minimum unit, wherein transistors M1 and M3 are NMOS (N-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor field effect) transistors, transistors M2 and M4 are PMOS (positive channel Metal Oxide Semiconductor, p-type metal oxide semiconductor field effect) transistors, and transistors M5 and M6 are transmission gate NMOS transistors. Transistors M1 and M2 constitute a first CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor), and transistors M3 and M4 constitute a second CMOS.

[0062] To facilitate the exchange of data between inside and outside, the drains of transistors M1 and M2 are connected to the instrument to form the output node OUT1 of the first CMOS, and the drains of transistors M3 and M4 are connected to the instrument to form the output node OUT2 of the second CMOS. The gates of transistors M1 and M2 are connected together to form the input node IN1 of the first CMOS, and the gates of transistors M3 and M4 are connected together to form the input node IN2 of the second CMOS.

[0063] The 6T SRAM cell is described in detail above. The memory device provided in the embodiment of the present disclosure uses the 6T SRAM cell as the smallest memory cell, has a smaller number of transistors, simplifies the computer's storage and computing structure, saves computing resources, and improves computing progress and efficiency.

[0064] The memory device provided by the embodiment of the present disclosure includes: a substrate; a memory cell array on the substrate, including a plurality of memory cells, wherein each memory cell includes: a left stack and a right stack arranged at intervals in the horizontal direction, the left stack and the right stack each include a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer and a second NMOS layer stacked in sequence on the substrate, the PMOS layer, the first NMOS layer and the second NMOS layer each include a first source / drain layer, a channel layer and a second source / drain layer stacked vertically, and the channel layer is laterally recessed relative to the first source / drain layer and the second source / drain layer; and a gate stack, which is located between the first source / drain layer and the second source / drain layer in the vertical direction and is disposed on opposite sides of the channel layer to embed the lateral recess of the channel layer.

[0065] According to an embodiment of the present disclosure, the memory device further includes: a hard mask layer disposed on the first source / drain layer of the second NMOS layer.

[0066] According to an embodiment of the present disclosure, the gate stack includes a gate dielectric layer and a gate conductor layer, and the gate dielectric layer includes a work function regulating metal and a gate conductive metal disposed on the work function regulating metal.

[0067] According to an embodiment of the present disclosure, the gate conductor layer includes a p-type gate conductor layer and an n-type gate conductor layer, wherein: the p-type gate conductor layer is arranged between the first source / drain layer and the second source / drain layer of the PMOS layer; the n-type gate conductor layer is arranged between the first source / drain layer and the second source / drain layer of the first NMOS layer, and between the first source / drain layer and the second source / drain layer of the second NMOS layer.

[0068] According to an embodiment of the present disclosure, the lateral peripheral portions of the first source / drain layer and the second source / drain layer are recessed and the recessed portions are filled with a third SiC layer; and / or the lateral peripheral portions of the gate conductor layer are recessed and the recessed portions are filled with a third SiC layer.

[0069] According to an embodiment of the present disclosure, the outer sidewall of the third SiC layer is coplanar with the left and right stacking layers in the vertical direction.

[0070] According to an embodiment of the present disclosure, the memory device also includes: a fifth SiO2 layer formed on the substrate between the left stack and the right stack, the top of the fifth SiO2 layer being higher than the bottom of the first source / drain layer of the PMOS layer and lower than the top of the first source / drain layer of the PMOS layer.

[0071] According to an embodiment of the present disclosure, the memory device also includes: a first metal layer formed on the fifth SiO2 layer at the longitudinal middle position of the left stack and the right stack, the top of the first metal layer is higher than the top of the first source / drain layer of the PMOS layer and lower than the bottom of the second source / drain layer of the PMOS layer.

[0072] According to an embodiment of the present disclosure, the memory device also includes: a sixth SiO2 layer and a second metal layer sequentially formed on the first metal layer, the top of the sixth SiO2 layer is higher than the top of the first source / drain layer of the first NMOS layer and lower than the bottom of the second source / drain layer of the first NMOS layer; the top of the second metal layer is higher than the bottom of the second source / drain layer of the first NMOS layer and lower than the top of the second source / drain layer of the first NMOS layer.

[0073] According to an embodiment of the present disclosure, the memory device also includes: a seventh SiO2 layer, formed on the fifth SiO2 layer except for the middle position in the longitudinal direction, and the top of the seventh SiO2 layer is higher than the top of the first source / drain layer of the PMOS layer and lower than the bottom of the second source / drain layer of the PMOS layer.

[0074] According to an embodiment of the present disclosure, the memory device further includes: a third metal layer formed on the seventh SiO2 layer, the top of the third metal layer being higher than the top of the first source / drain layer of the first NMOS layer and lower than the bottom of the second source / drain layer of the first NMOS layer.

[0075] According to an embodiment of the present disclosure, the storage device also includes: an eighth SiO2 layer formed on the third metal layer, the top of the eighth SiO2 layer is higher than the bottom of the first source / drain layer of the second NMOS layer and lower than the top of the first source / drain layer of the second NMOS layer; the middle position of the top of the eighth SiO2 layer is relatively recessed and exposes the third metal layer, forming a second spacer portion separated from the left and right and having a step structure.

[0076] According to an embodiment of the present disclosure, the inner sidewall and bottom surface of the second spacer are formed with a fourth metal layer that is higher than the top of the eighth SiO2 layer; the top of the fourth metal layer is higher than the bottom of the first source / drain layer of the second NMOS layer and lower than the top of the first source / drain layer of the second NMOS layer.

[0077] According to an embodiment of the present disclosure, the memory device further includes: a fifth metal layer, formed on one of the left stack and the right stack, and contacting the outer side wall of the n-type gate conductor layer in the second NMOS layer; a word line, connected to the fifth metal layer, the word line spanning between the left stack and the right stack at different longitudinal positions on the same memory cell to contact and electrically connect to the outer side wall of the n-type gate conductor layer of the left stack or the right stack in the second NMOS layer.

[0078] According to an embodiment of the present disclosure, the storage device also includes: a first contact portion and a second contact portion, the first contact portion is embedded in the second source / drain layer of the second NMOS layer of the left stack, and the second contact portion is embedded in the second source / drain layer of the second NMOS layer of the right stack, and the first contact portion and the second contact portion are respectively connected to a first bit line and a second bit line with opposite signals.

[0079] It should be noted that the implementation method of the device part is similar to the implementation method of the method part, and the technical effects achieved are also similar. For specific details, please refer to the implementation method of the method part, which will not be repeated here.

[0080] The present disclosure also provides a method for preparing a memory device, including:

[0081] Step S1, forming a left stack and a right stack arranged in a horizontal direction on a substrate, wherein the left stack and the right stack each include a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer and a second NMOS layer stacked in sequence, wherein the PMOS layer, the first NMOS layer and the second NMOS layer each include a first source / drain layer, a channel layer and a second source / drain layer stacked vertically, and the channel layer is laterally recessed relative to the first source / drain layer and the second source / drain layer;

[0082] Step S2, depositing a gate dielectric layer and a p-type gate conductor layer in sequence in the lateral recess of the channel layer;

[0083] Step S3, depositing SiO2 at the bottom of the left stack and the right stack, and then etching the SiO2 and stopping at a first preset height to form a first spacer;

[0084] Step S4, etching the p-type gate conductor layer at the corresponding positions of the first NMOS layer and the second NMOS layer, and depositing an n-type gate conductor layer at the corresponding positions of the etched p-type gate conductor layer;

[0085] Step S5, etching the first spacer to form a memory cell, wherein the memory device includes a memory cell array of a plurality of the memory cells.

[0086] The following Figure 2 to Figure 29 A method for manufacturing a memory device according to an embodiment of the present disclosure is described in detail. Figures 2 to 29 The flowchart schematically shows a method for preparing a memory device according to an embodiment of the present disclosure at different stages.

[0087] Figure 2 A cross-sectional view schematically shows a stacked layer formed on a substrate. Figure 2 As shown, a substrate 1001 is provided. The substrate 1001 may be a substrate of various forms, including but not limited to a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor on insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, etc. In the following description, for convenience of explanation, a bulk Si substrate is used as an example. Here, a silicon wafer is provided as the substrate 1001.

[0088] A well region may be formed in the substrate 1001. If a p-type device is to be formed, the well region may be an n-type well; if an n-type device is to be formed, the well region may be a p-type well. Therefore, for example, a p-type well may be formed by implanting a p-type dopant such as boron (B) into the substrate 1001 and then performing thermal annealing.

[0089] On the substrate 1001, a PMOS layer, a first NMOS layer, and a second NMOS layer stacked sequentially on the substrate can be formed by epitaxial growth. The PMOS layer is a p-type device, and the first NMOS layer and the second NMOS layer are both n-type devices. Those skilled in the art know that the doping of semiconductor materials can be achieved by in-situ doping during epitaxial growth, or by other doping methods such as ion implantation. By appropriately adjusting the conductivity type of the doping, a p-type device or an n-type device can be formed.

[0090] The PMOS layer includes a first source / drain layer 10031, a channel defining layer 10051, and a second source / drain layer 10071 vertically stacked in sequence. Similarly, the first NMOS layer includes a first source / drain layer 10032, a channel defining layer 10052, and a second source / drain layer 10072 vertically stacked in sequence. The second NMOS layer includes a first source / drain layer 10033, a channel defining layer 10053, and a second source / drain layer 10073 vertically stacked in sequence. The thickness of the first source / drain layer 10031 / 10032 / 10033 is, for example, about 20 nm to 50 nm, the thickness of the channel defining layer 10051 / 10052 / 10053 is, for example, about 15 nm to 100 nm, and the thickness of the second source / drain layer 10071 / 10072 / 10073 is, for example, about 20 nm to 50 nm.

[0091] To distinguish different MOS layers, a lower isolation layer 10021 is disposed between the substrate 1001 and the first source / drain layer 10031 of the PMOS layer, and an upper isolation layer 10022 is disposed between the second source / drain layer 10072 of the first NMOS layer and the first source / drain layer 10033 of the second NMOS layer.

[0092] Adjacent layers on the substrate 1001 may have etching selectivity relative to each other. For example, the first source / drain layer 10031 / 10032 / 10033 may include Si; the channel defining layer 10051 / 10052 / 10053 may be SiGe, and the composition of Ge is about 10% to 20%; the second source / drain layer 10071 / 10072 / 10073 may be Si. The upper isolation layer 10022 and the lower isolation layer 10021 may both be SiGe, with a thickness of about 10nm to 20nm, and a composition of Ge of about 10% to 20%.

[0093] In addition, a hard mask layer 1009 is deposited on the second source / drain layer 10073 of the second NMOS layer to facilitate patterning. The hard mask layer 1009 may include nitride, such as SiN, and has a thickness of about 50 nm to 200 nm.

[0094] Fig. 3(a) schematically shows a top view of a photoresist patterning region. Fig. 3(b) is a cross-sectional view along line AA' formed according to Fig. 3(a).

[0095] Then, if Figure 3(a) and 3(b) As shown, photoresist is spin-coated on the hard mask layer 1009, and the photoresist is patterned into the shape of the photolithography device area defined in Figure 3(a) through processes such as exposure and development. The patterned photoresist is used as a mask to sequentially etch the hard mask layer 1009 along the vertical direction until the upper surface of the substrate 1001, and then the photoresist is removed.

[0096] It should be noted that the AA cross-sectional view of FIG3(b) only captures the AA cross-sectional view in the rectangular frame area outside the bold double-dash line in FIG3(a), and the subsequent AA' cross-sectional view, 11' cross-sectional view, BB' cross-sectional view and CC' cross-sectional view are all cross-sectional views corresponding to the rectangular frame area outside the bold double-dash line in the corresponding top view. The subsequent top view display area is obviously larger than the cross-sectional view area, which is only to show the overall shape of the storage array formed by the interconnection of multiple minimum SRAM storage cells in the top view. The PR (Photoresist) area in FIG4(a) represents the area where the photoresist is spun on, which is not etched away and retains the original laminated structure; the dark area represents the area without photoresist, that is, the area where the substrate 1001 is exposed in the top view after etching.

[0097] Thus, as shown in FIG3(b), on a single SRAM memory cell in the cross section along line AA′, after etching, a left stack and a right stack arranged alternately in the horizontal direction are formed, and the cross section of each stack on the substrate 1001 is formed into a rectangular column. Thus, the corresponding side walls of each layer in the stack can be coplanar in the vertical direction.

[0098] In addition, just to illustrate the specific structure of the minimum SRAM memory cell, the spacing between the left stack and the right stack in the middle of FIG. 3(b) is significantly larger than the spacing between two adjacent rectangular photoresists along the horizontal direction in FIG. 3(a).

[0099] Fig. 4(a) schematically shows a top view of a photoresist patterning region. Fig. 4(b) is a cross-sectional view along line AA' formed according to Fig. 4(a).

[0100] Next, as shown in FIG. 4( a ), a first SiC layer 2001 is deposited in the region where the two upper and lower transverse stripes and the plurality of longitudinal stripes in the horizontal direction are located, and the deposition of the first SiC layer 2001 is controlled to stop at the upper surface of the hard mask layer 1009 by chemical mechanical polishing (CMP). Then, except for the two upper and lower transverse stripes, the other parts are spin-coated with photoresist, and the first SiC layer 2001 deposited on the two upper and lower transverse stripes is etched from top to bottom, and the etching stops at the upper surface of the substrate 1001. The material of the first SiC layer 2001 is SiC.

[0101] Thus, the upper and lower transverse stripes expose the substrate 1001 , and the other exposed areas of the substrate 1001 are filled with the first SiC layer 2001 .

[0102] As shown in FIG. 4( b ), on the AA′ section and before etching, the hard mask layer 1009 and the first SiC layer 2001 at the top of the stacked structure are alternately arranged in the horizontal direction, and the upper surfaces of the hard mask layer 1009 and the first SiC layer 2001 are coated with photoresist.

[0103] Fig. 5(a) schematically shows a top view of a photoresist patterning region. Fig. 5(b) is a cross-sectional view taken along line 11' formed according to Fig. 5(a).

[0104] Then, if Figure 5(a) and 4(b) As shown, the photoresist of FIG. 4 (b) is removed, and the corresponding sidewalls of the lower isolation layer 10021, the upper isolation layer 10022, and the channel defining layer 10051 / 10052 / 10053 are partially etched along the direction perpendicular to the upper and lower transverse stripes, that is, the vertical direction, so that the transverse SiGe grooves shown in FIG. 5 (b) are formed in the lower isolation layer 10021, the upper isolation layer 10022, and the channel defining layer 10051 / 10052 / 10053. Since the lower isolation layer 10021, the upper isolation layer 10022, and the channel defining layer 10051 / 10052 / 10053 can all be SiGe, it is convenient to uniformly etch.

[0105] Then, a first SiO2 layer 2011 is deposited in the lateral SiGe groove, and the first SiO2 layer 2011 can be etched by reactive ion etching (RIE) to fill and occupy the lateral SiGe groove, and keep the outer sidewall of the first SiO2 layer 2011 aligned with the outer sidewall of the stack. The material of the first SiO2 layer 2011 is SiO2.

[0106] Thus, a portion of the lower isolation layer 10021 , the upper isolation layer 10022 and the channel defining layer 10051 / 10052 / 10053 are each etched away, while another portion is retained, wherein the etched away portion forms a lateral SiGe groove and is then replaced by the first SiO 2 layer 2011 .

[0107] Figure 6(a) schematically shows a top view of a photoresist patterning region. Figure 6(b) is a cross-sectional view along line 11' formed according to Figure 6(a). Figure 6(c) is a cross-sectional view along line AA' formed according to Figure 6(a).

[0108] Next, as shown in FIG6(a), a first SiC layer 2001 is deposited on the exposed area of ​​the substrate 1001 where the upper and lower horizontal stripes are located, and the deposition of the first SiC layer 2001 is controlled by CMP to stop at the upper surface of the hard mask layer 1009. Then, the formed first SiC layer 2001 is etched downward at the vertical narrow stripes in FIG6(a), and the etching stops at the upper surface of the substrate 1001. The end point detection method can be used to determine the etching stop moment.

[0109] Therefore, as shown in FIG6(b), in the cross section along line 11′ and before etching, a first SiC layer 2001 is deposited on the substrate 1001 at the locations of the two lateral stripes to a height of the hard mask layer 1009, and the upper surfaces of the hard mask layer 1009 and the first SiC layer 2001 are coated with photoresist.

[0110] As shown in FIG6(c), in the cross section along the AA′ line, a first SiC layer 2001 is deposited between the left stack and the right stack to a height of the hard mask layer 1009, and the outer sides of the left stack and the right stack are etched away at the position where the first SiC layer 2001 was previously formed, forming a groove reaching the substrate 1001.

[0111] Figure 7 A cross-sectional view along line AA' is schematically shown.

[0112] Then, if Figure 7 As shown, the photoresist is removed, and then the lower isolation layer 10021, the upper isolation layer 10022 and the channel defining layer 10051 / 10052 / 10053 are partially etched in the cross section along the AA′ line, so that lateral SiGe grooves are formed in the lower isolation layer 10021, the upper isolation layer 10022 and the channel defining layer 10051 / 10052 / 10053.

[0113] The first epitaxial layer 3001 is epitaxially grown in the lateral SiGe groove formed after etching and extending to the outer surface of the entire device except the substrate 1001. The first epitaxial layer 3001 may be SiGe, and the composition of Ge is about 10% to 40%.

[0114] It should be noted that, since the thickness of the lower isolation layer 10021 and the upper isolation layer 10022 is relatively small, the epitaxial thickness of the first epitaxial layer 3001 needs to be controlled to be greater than half of the maximum thickness of the lower isolation layer 10021 and the upper isolation layer 10022 and less than half of the maximum thickness of the channel defining layer 10051 / 10052 / 10053. Thus, after the epitaxial process, the lateral SiGe grooves can be maintained inside the channel defining layer 10051 / 10052 / 10053, and the groove spaces of the lower isolation layer 10021 and the upper isolation layer 10022 are substantially filled by the first epitaxial layer 3001.

[0115] Figure 8 A cross-sectional view along line AA' is schematically shown.

[0116] Then, if Figure 8 As shown, the first epitaxial layer 3001 is isotropically etched. Since the groove space of the lower isolation layer 10021 and the upper isolation layer 10022 is substantially filled with the first epitaxial layer 3001, the first epitaxial layer 3001 filling the groove space can be retained during the isotropic etching process, and the other parts of the first epitaxial layer 3001 in FIG. 7 are all etched away.

[0117] Fig. 9 A cross-sectional view along line AA' is schematically shown.

[0118] Then, if Fig. 9 As shown, in Figure 8 A second SiO2 layer 2012 is deposited in the lateral SiGe groove of the channel defining layer 10051 / 10052 / 10053, and then the outer sidewall of the second SiO2 layer 2012 is anisotropically etched to fill and occupy the lateral SiGe groove, and to keep the outer sidewall of the second SiO2 layer 2012 aligned with the outer sidewall of the stack. The material of the second SiO2 layer 2012 is SiO2.

[0119] As a result, the etched away portions of the channel defining layers 10051 / 10052 / 10053 are each filled with the second SiO 2 layer 2012 .

[0120] Fig.10 A cross-sectional view along line AA' is schematically shown.

[0121] Then, if Fig.10 As shown, the lower isolation layer 10021, the upper isolation layer 10022 and the first epitaxial layer 3001 filled with the groove space of the lower isolation layer 10021 and the upper isolation layer 10022 are etched, and the second SiC layer 2002 is deposited on the corresponding positions of the lower isolation layer 10021 and the upper isolation layer 10022, and then the second SiC layer 2002 is etched back to make the outer side wall of the second SiC layer 2002 and the outer side wall of the stacked layer aligned with each other. The material of the second SiC layer 2002 is SiC.

[0122] Thus, the lower isolation layer 10021 and the upper isolation layer 10022 are replaced by the second SiC layer 2002. Fig.10 A first SiC layer 2001 is previously formed between the left and right stacks in the middle, and the second SiC layer 2002 inside the left and right stacks can be connected to the first SiC layer 2001 of the same material. Therefore, the second SiC layer 2002 not only forms interlayer isolation between different stacks, but also forms interlayer isolation between different material layers within the same stack.

[0123] Fig.11 A cross-sectional view along line AA' is schematically shown.

[0124] Then, if Fig.11 As shown, the second SiO2 layer 2012 is etched, and the first source / drain layer 10031 / 10032 / 10033, the channel defining layer 10051 / 10052 / 10053 and the second source / drain layer 10071 / 10072 / 10073 are etched at the same preset thickness near the second SiO2 layer 2012, and the second epitaxial layer 3002 is epitaxially generated at the etched position, and then the second epitaxial layer 3002 is anisotropically etched, so that a "C"-shaped channel is formed between the adjacent first source / drain layer, the channel defining layer and the second source / drain layer of the same MOS layer. The material of the second epitaxial layer 3002 can be Si. For the convenience of explanation, the "C"-shaped channel is marked as the channel layer 200.

[0125] Fig.12 A cross-sectional view along line AA' is schematically shown.

[0126] Then, if Fig.12 As shown, a third SiO2 layer 2013 is deposited in the outer grooves of the left and right stacks in the middle, and the deposition of the third SiO2 layer 2013 is controlled by CMP to stop at the upper surface of the hard mask layer 1009. Then, the first SiC layer 2001 between the left and right stacks is etched downward, and the etching stops at the upper surface of the substrate 1001.

[0127] Among them, the material of the third SiO2 layer 2013 is SiO2, and the end point detection method can be used to determine the etching stop time.

[0128] Fig.13 A cross-sectional view along line AA' is schematically shown.

[0129] Then, if Fig.13 As shown, the channel defining layer 10051 / 10052 / 10053 is selectively etched, and a fourth SiO2 layer 2014 is deposited on the corresponding position of the channel defining layer 10051 / 10052 / 10053. The deposition of the third SiO2 layer 2013 is controlled by CMP to stop at the upper surface of the hard mask layer 1009. Then, the fourth SiO2 layer 2014 between the left stack and the right stack and the third SiO2 layer 2013 formed outside the left stack and the right stack are etched downwards, so that the outer sidewalls of the fourth SiO2 layer 2014 and the third SiO2 layer 2013 are aligned with the outer sidewalls of the stack.

[0130] Thus, the channel defining layers 10051 / 10052 / 10053 previously located in different MOS layers are replaced by the third SiO 2 layer 2013 , the fourth SiO 2 layer 2014 , and the channel layer 200 disposed between the third SiO 2 layer 2013 and the fourth SiO 2 layer 2014 .

[0131] Fig.14 A cross-sectional view along line AA' is schematically shown.

[0132] Then, if Fig.14 As shown, the fourth SiO2 layer 2014 and the third SiO2 layer 2013 are etched, and a gate dielectric layer 4001 and a p-type gate conductor layer 4002 are sequentially deposited at corresponding positions of the fourth SiO2 layer 2014 and the third SiO2 layer 2013 to form a p-type gate stack. Thus, the gate dielectric layer 4001 is filled into the recessed portions of the fourth SiO2 layer 2014 and the third SiO2 layer 2013, and the p-type gate conductor layer 4002 fills the inner wall of the gate dielectric layer 4001. In order to control the etching depth, the formed p-type gate conductor layer 4002 needs to be etched back at the end.

[0133] The gate dielectric layer 4001 may be made of a dielectric material with a high dielectric constant, such as HfO2, with a thickness of about 1 nm to 5 nm. The p-type gate conductor layer 4002 may be deposited on the surface of the gate dielectric layer 4001 in a substantially conformal manner, thereby filling the inner wall of the gate dielectric layer 4001. The p-type gate conductor layer 4002 may include a p-type work function adjustment metal and a p-type gate conductive metal.

[0134] The p-type gate stack (including the gate dielectric layer 4001 and the p-type gate conductor layer 4002) formed in this way is respectively formed on the lateral periphery of the channel layer 200 where the PMOS layer, the first NMOS layer and the second NMOS layer are located. The p-type gate stack can be embedded between the first source / drain layer 10031 / 10032 / 10033 and the second source / drain layer 10071 / 10072 / 10073, and surround the lateral periphery of the channel layer 200.

[0135] Fig.15 A cross-sectional view along line AA' is schematically shown.

[0136] Then, if Fig.15 As shown, SiO2 is deposited at the bottom of each stack, and then the SiO2 is etched and stopped at a first preset height to form a first spacer 301. Specifically, the first preset height is higher than the bottom of the second source / drain layer 10071 of the PMOS layer, and lower than the top of the first source / drain layer 10032 of the first NMOS layer. Thus, the first spacer 301 can isolate the p-type gate conductor layer 4002 where the PMOS layer is located to avoid subsequent influences.

[0137] Then, the p-type gate conductor layer 4002 at the corresponding positions of the first NMOS layer and the second NMOS layer is etched, and the n-type gate conductor layer 4003 is deposited at the corresponding positions of the p-type gate conductor layer 4002 to form an n-type gate stack. To control the etching depth, the formed n-type gate conductor layer 4003 needs to be etched back.

[0138] Thus, on the first NMOS layer and the second NMOS layer, the n-type gate conductor layer 4003 can be deposited on the surface of the gate dielectric layer 4001 in a substantially conformal manner, thereby filling the inner wall of the gate dielectric layer 4001. The n-type gate conductor layer 4003 can include an n-type work function adjusting metal and an n-type gate conductive metal.

[0139] The n-type gate stack (including the gate dielectric layer 4001 and the n-type gate conductor layer 4003) formed in this way is respectively formed on the lateral periphery of the channel layer 200 where the first NMOS layer and the second NMOS layer are located. The n-type gate stack can be embedded between the first source / drain layer 10032 / 10033 and the second source / drain layer 10072 / 10073 and surround the lateral periphery of the channel layer 200.

[0140] Fig.16 A cross-sectional view along line AA' is schematically shown.

[0141] Then, if Fig.16 As shown, the first spacer 301 is etched to form a minimum SRAM memory cell structure.

[0142] Specifically, the SRAM memory cell may include: a substrate; a memory cell array on the substrate, including a plurality of memory cells, wherein each memory cell includes: a left stack and a right stack arranged at intervals in the horizontal direction, the left stack and the right stack each include a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer and a second NMOS layer stacked sequentially on the substrate, the PMOS layer, the first NMOS layer and the second NMOS layer each include a first source / drain layer, a channel layer and a second source / drain layer stacked vertically, the channel layer is laterally recessed relative to the first source / drain layer and the second source / drain layer; a gate stack, located between the first source / drain layer and the second source / drain layer in the vertical direction, and disposed on opposite sides of the channel layer to embed the lateral recess of the channel layer. At the same time, the SRAM memory cell also includes: a hard mask layer, disposed on the first source / drain layer of the second NMOS layer.

[0143] Figure 17(a) schematically shows a top view of a photoresist patterning region. Figure 17(b) is a cross-sectional view along line AA' formed according to Figure 17(a). Figure 17(c) is a cross-sectional view along line BB' formed according to Figure 17(a).

[0144] Next, as shown in FIG17( a), a photoresist is spin-coated in the area where the PR is located, and the first source / drain layer 10031 / 10032 / 10033 and the second source / drain layer 10071 / 10072 / 10073 are partially etched in the horizontal direction in the area where the photoresist is not spin-coated. Preferably, the etching depth of the first source / drain layer 10031 / 10032 / 10033 and the second source / drain layer 10071 / 10072 / 10073 can be half of the p-type gate conductor layer 4002 or the n-type gate conductor layer 4003 in the horizontal direction.

[0145] Therefore, as shown in FIG17(b), the cross section along the AA′ line is coated with photoresist PR and is not etched. As shown in FIG17(c), the left stack in the middle of the cross section along the BB′ line is not spin-coated with photoresist, so the first source / drain layer 10031 / 10032 / 10033 and the second source / drain layer 10071 / 10072 / 10073 in this part are partially etched, and the etching depth is approximately half of the p-type gate conductor layer 4002 or the n-type gate conductor layer 4003 in the horizontal direction.

[0146] FIG. 18( a ) schematically shows a top view of a photoresist patterning region. FIG. 18( b ) is a cross-sectional view along line AA′ formed according to FIG. 18( a ). FIG. 18( c ) is a cross-sectional view along line BB′ formed according to FIG. 18( a ). FIG. 18( d ) is a cross-sectional view along line CC′ formed according to FIG. 18( a ).

[0147] Next, as shown in FIG18( a), a photoresist is spin-coated in the area where the PR is located, and the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 are partially etched in the horizontal direction in the area where the photoresist is not spin-coated. Preferably, the etching depth of the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 can be half of the p-type gate conductor layer 4002 or the n-type gate conductor layer 4003 in the horizontal direction.

[0148] It should be noted that, in the best case, the region where PR in FIG. 18( a ) is located is complementary to the region where PR in FIG. 17( a ) is located, that is, the two regions have no common intersection and together constitute the outer contour of the device in the entire top view.

[0149] Therefore, as shown in FIG. 18( b ), no photoresist is spin-coated on the cross section along line AA′, and the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 of the cross section are partially etched, and the etching depth is approximately one-half of the p-type gate conductor layer 4002 or the n-type gate conductor layer 4003 in the horizontal direction.

[0150] As shown in FIG18(c), the left stack in the middle of the cross section along the BB' line is coated with photoresist while the right stack is not coated with photoresist, and the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 on the right stack in the figure are partially etched. In addition, since the left stack in the middle of the cross section is not covered by photoresist in the aforementioned FIG17(a), the first source / drain layer 10031 / 10032 / 10033 and the second source / drain layer 10071 / 10072 / 10073 on the left stack in the figure are partially etched in the aforementioned FIG17(a).

[0151] As shown in FIG18(d), the cross section along the CC' line is not coated with photoresist, so the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 on all the stacked structures are partially etched. It should also be noted that since the middle left stacked layer of the cross section along the CC' line is also exposed to the outside in the aforementioned FIG17(a), that is, not covered by photoresist, the first source / drain layer 10031 / 10032 / 10033 and the second source / drain layer 10071 / 10072 / 10073 of the middle left stacked layer on the cross section are also partially etched. Therefore, the first source / drain layer 10031 / 10032 / 10033, the second source / drain layer 10071 / 10072 / 10073, the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 of the middle left stack in Figure 18(d) are all partially etched. Due to the unavoidable gap in the photolithography process, several gate metal nanowires can be seen extending out of the gate metal and the source / drain layer.

[0152] FIG. 19( a ) schematically shows a top view of a photoresist patterning region. FIG. 19( b ) is a cross-sectional view along line AA′ formed according to FIG. 19( a ). FIG. 19( c ) is a cross-sectional view along line BB′ formed according to FIG. 19( a ). FIG. 19( d ) is a cross-sectional view along line CC′ formed according to FIG. 19( a ).

[0153] Next, as shown in FIG. 19( a), a third SiC layer 2003 is deposited on the exposed area of ​​the substrate 1001, and the deposition of the third SiC layer 2003 is controlled by CMP to stop at the upper surface of the hard mask layer 1009. Then, the formed third SiC layer 2003 is etched downward, and the etching stops at the upper surface of the substrate 1001. The third SiC layer 2003 can be made of SiC material, and the end point detection method can be used to determine the etching stop moment.

[0154] Thus, the recessed portions of each stack exposed by partial etching are filled with the third SiC layer 2003 to isolate the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 at different heights of the same stack. In addition, the corresponding outer sidewalls of each layer in the stack can be coplanar in the vertical direction.

[0155] Then, as shown in FIG. 19( b ), in the cross section along line AA′, the recessed portions of the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 in different MOS layers in FIG. 18( b ) are filled with the third SiC layer 2003 .

[0156] As shown in FIG. 19( c ), on the cross section along line BB′, the first source / drain layer 10031 / 10032 / 10033, the second source / drain layer 10071 / 10072 / 10073, and the concave portions of the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 in FIG. 18( c ) are all filled with the third SiC layer 2003. Similarly, as shown in FIG. 19( d ), on the cross section along line CC′, the first source / drain layer 10031 / 10032 / 10033, the second source / drain layer 10071 / 10072 / 10073, and the concave portions of the p-type gate conductor layer 4002 and the n-type gate conductor layer 4003 in FIG. 18( d ) are all filled with the third SiC layer 2003.

[0157] Fig. 20 A cross-sectional view along line AA' is schematically shown.

[0158] Then, if Fig. 20 As shown, in the cross section along the AA′ line, a fifth SiO2 layer 2015 is deposited on the exposed area of ​​the substrate 1001, and the deposition of the fifth SiO2 layer 2015 is controlled by CMP to stop at the upper surface of the hard mask layer 1009. Thus, the fifth SiO2 layer 2015 can form a shallow trench isolation (STI) between the left stack and the right stack.

[0159] Fig. 21(a) schematically shows a top view of a photoresist patterning region. Fig. 21(b) is a cross-sectional view taken along line AA' formed according to Fig. 21(a).

[0160] As shown in FIG. 21( a), the horizontal wide stripes on the upper and lower sides of the AA′ cross section are not covered by the photoresist, and the other parts are covered with the photoresist. The fifth SiO2 layer 2015 is etched downward at the horizontal wide stripes, and the etching stops at a second preset height. The second preset height is higher than the bottom of the first source / drain layer 10031 and lower than the top of the first source / drain layer 10031.

[0161] Then, in order to reduce the series resistance and contact resistance of the active area, metal silicide needs to be formed on the active area, and the surface of the fifth SiO2 layer 2015 is processed by a metal silicide process. Silicide can prevent the metal from reacting with the contacting SiO2 material, so Silicide can be well aligned with the active area and the polysilicon gate.

[0162] Next, a first metal layer 5001 is deposited on the etched fifth SiO2 layer 2015, and the deposition of the first metal layer 5001 is controlled by CMP to stop at the upper surface of the hard mask layer 1009. Then, the first metal layer 5001 is etched downwards, and the etching stops at a third preset height.

[0163] The third preset height is higher than the top of the first source / drain layer 10031 and lower than the bottom of the second source / drain layer 10071. Figure 1 It can be seen that the first metal layer 5001 can be used to form a power line Vdd.

[0164] Fig. 22 A cross-sectional view along line AA' is schematically shown.

[0165] Then, if Fig. 22 As shown, refer to Fig. 20 , Figure 21(a) and 21(b) The sixth SiO2 layer 2016 and the second metal layer 5002 are sequentially formed on the first metal layer 5001. Fig. 20 , Figure 21(a) and 21(b) The difference between the processes is that the etching of the sixth SiO2 layer 2016 stops at the fourth preset height, and the etching of the second metal layer 5002 stops at the fifth preset height.

[0166] Specifically, a sixth SiO2 layer 2016 is deposited on the first metal layer 5001, and the deposition of the sixth SiO2 layer 2016 is controlled by CMP to stop at the upper surface of the hard mask layer 1009, so that the sixth SiO2 layer 2016 forms an STI between the left stack and the right stack. Then, the sixth SiO2 layer 2016 is etched downward, and the etching stops at a fourth preset height, thereby forming the sixth SiO2 layer 2016 on the first metal layer 5001.

[0167] Next, a second metal layer 5002 is deposited on the sixth SiO2 layer 2016, and the deposition of the second metal layer 5002 is controlled by CMP to stop at the upper surface of the hard mask layer 1009. Then, the second metal layer 5002 is etched downward, and the etching stops at a fourth preset height, thereby forming the second metal layer 5002 on the sixth SiO2 layer 2016.

[0168] The fourth preset height is higher than the top of the first source / drain layer 10032 and lower than the bottom of the second source / drain layer 10072. Thus, the sixth SiO2 layer 2016 can form a shallow trench isolation between the left stack and the right stack.

[0169] The fifth preset height is higher than the bottom of the second source / drain layer 10072 and lower than the top of the second source / drain layer 10072. Figure 1 It can be known that the second metal layer 5002 can be used to form a ground line GND.

[0170] After the second metal layer 5002 is formed, a seventh SiO 2 layer 2017 needs to be deposited on the second metal layer 5002 . The deposition of the seventh SiO 2 layer 2017 is controlled to stop at the upper surface of the hard mask layer 1009 by CMP.

[0171] Fig. 23(a) schematically shows a top view of a photoresist patterning region. Fig. 23(b) is a cross-sectional view along line BB' formed according to Fig. 23(a).

[0172] Next, as shown in Figures 23(a) and 23(b), the small rectangular frames on the upper and lower sides of the BB' section are not covered by the photoresist and belong to the exposed area of ​​the substrate 1001, and the other parts are covered with the photoresist PR. Moreover, the exposed area of ​​the substrate 1001 just exposes the area between the left stack and the right stack of the single minimum SRAM storage unit.

[0173] The seventh SiO2 layer 2017 is etched downward in the rectangular frame areas on both sides of the BB′ cross section, and the etching stops at a sixth preset height, and then the photoresist is removed. The sixth preset height is higher than the top of the first source / drain layer 10031 and lower than the bottom of the second source / drain layer 10071.

[0174] In order to reduce the series resistance and contact resistance of the active area, it is also necessary to form metal silicide on the active area, and the surface of the seventh SiO2 layer 2017 is processed by a metal silicide process (Silicide).

[0175] Fig.24 A cross-sectional view along line BB' is schematically shown.

[0176] Then, if Fig.24 As shown, a third metal layer 5003 is deposited on the seventh SiO2 layer 2017 of the BB′ cross section, and the deposition of the third metal layer 5003 is controlled by CMP to stop at the upper surface of the hard mask layer 1009. Then, the third metal layer 5003 is etched downwards and the etching stops at the seventh preset height.

[0177] The seventh preset height is higher than the top of the first source / drain layer 10032 and lower than the bottom of the second source / drain layer 10072. Figure 1 It can be seen that the third metal layer 5003 can be used to connect the input node IN1 of the first CMOS with the output node OUT2 of the second CMOS, and at the same time connect the input node IN2 of the second CMOS with the output node OUT1 of the first CMOS.

[0178] Fig.25 A cross-sectional view along line BB' is schematically shown.

[0179] Then, if Fig.25 As shown, a fourth SiC layer 2004 is deposited on the third metal layer 5003 of the BB′ cross section, and the deposition of the fourth SiC layer 2004 is controlled by CMP to stop at the upper surface of the hard mask layer 1009. Then, the fourth SiC layer 2004 is etched downward and stopped at an eighth preset height, and the etching is continued at the middle position of the top of the fourth SiC layer 2004 and stopped at the upper surface of the third metal layer 5003, forming a second spacer separated from the left and right and having a step structure.

[0180] The eighth preset height is higher than the bottom of the first source / drain layer 10033 and lower than the top of the first source / drain layer 10033. Thus, the second spacer can isolate the n-type gate conductor layer 4003 of the first NMOS layer to avoid subsequent influences.

[0181] Fig.26 A cross-sectional view along line BB' is schematically shown.

[0182] Then, if Fig.26 As shown, a fourth metal layer 5004 is deposited on the inner sidewall, bottom surface and upper surface of the second spacer of the BB′ section, and the deposition of the fourth metal layer 5004 is controlled by CMP to stop at the upper surface of the hard mask layer 1009. Then, the fourth metal layer 5004 is etched downward and stops at a ninth preset height.

[0183] The ninth preset height is higher than the bottom of the first source / drain layer 10033 and lower than the top of the first source / drain layer 10033. Figure 1 It can be seen that the fourth metal layer 5004 can be used to connect the input node IN1 of the first CMOS, the output node OUT2 of the second CMOS and the source of the transistor M6, and simultaneously connect the input node IN2 of the second CMOS, the output node OUT1 of the first CMOS and the source of the transistor M5.

[0184] Fig. 27(a) schematically shows a top view of a photoresist patterning region. Fig. 27(b) is a cross-sectional view along line BB' formed according to Fig. 27(a).

[0185] Next, as shown in FIG. 27( a ) and FIG. 27 ( b ), the photoresist is removed, and an eighth SiO 2 layer 2018 is deposited on all upper surfaces so that the upper surfaces of all material layers are covered with the eighth SiO 2 layer 2018 .

[0186] Fig. 28(a) schematically shows a top view of a photoresist patterning region. Fig. 28(b) is a cross-sectional view along line BB' formed according to Fig. 28(a).

[0187] Next, as shown in FIG. 28( a), a photoresist (not shown) is spin-coated on the upper surface of the eighth SiO2 layer 2018 to define the regional shape of the word line WL. From the top view, the word line WL spans the front end face of the left stack and the rear end face of the right stack on the same memory cell. Using the patterned photoresist as a mask, the eighth SiO2 layer 2018 is etched downward, and the etching stops at the tenth preset height. The tenth preset height is higher than the top of the first source / drain layer 10033 and lower than the bottom of the second source / drain layer 10073, so that the n-type gate conductor layer 4003 in the second NMOS layer is partially exposed.

[0188] Then, a fifth metal layer 5005 is deposited on the outer sidewall of the n-type gate conductor layer 4003 in the second NMOS layer, and the deposition of the fifth metal layer 5005 is controlled by CMP to stop at the upper surface of the hard mask layer 1009. Then, the fifth metal layer 5005 is etched downward and stops at the eleventh preset height. The eleventh preset height is higher than the bottom of the second source / drain layer 10073 and lower than the top of the second source / drain layer 10073. At the same time, along the BB′ cross section, the fifth metal layer 5005 adjacent to the outer sidewall of the n-type gate conductor layer 4003 is partially etched, so that the etched fifth metal layer 5005 is isolated from the outer sidewalls of the left stack and the right stack respectively.

[0189] Therefore, as shown in Figure 28(b), on the BB′ cross section along the horizontal direction, only the n-type gate conductor layer 4003 in the second NMOS layer of the left stack is not in contact with the fifth metal layer 5005, and the n-type gate conductor layer 4003 in the second NMOS layer of the right stack is also not in contact with the fifth metal layer 5005, thereby forming a step-like connecting line.

[0190] Combined with Figure 1 It can be seen that the fifth metal layer 5005 can be used to define a word line WL, so that the word line WL spans the front end surface of the left stack and the rear end surface of the right stack on the same memory cell to contact and electrically connect to the outer side wall of the n-type gate conductor layer 4003 of the second NMOS layer where the front end surface of the left stack or the rear end surface of the right stack is located.

[0191] Fig.29 A cross-sectional view along line BB' is schematically shown.

[0192] Then, if Fig.29 As shown in FIG. 1 , metal contacts are formed on the second source / drain layer 10073 of the left stack and the right stack, respectively. Figure 1It can be seen that the metal contact portion can be used to form the bit line BL and the bit line BL with opposite signals.

[0193] Specifically, the metal contact portion includes: a first contact portion 6001 embedded in the second source / drain layer 10073 of the left stack, and a second contact portion 6001 embedded in the second source / drain layer 10073 of the right stack. The first contact portion 6001 can be connected to the bit line BL, and correspondingly, the second contact portion 6002 can be connected to the bit line

[0194] The metal contact portion may be formed by conventional processes. For example, the metal contact portion may be formed by sequentially etching holes in the hard mask layer 1009 and the second source / drain layer 10073 and filling the holes with a conductive material such as metal.

[0195] Thus, the memory device of the embodiment of the present disclosure is prepared. The memory device uses a 6T SRAM unit as the smallest memory unit, has a smaller number of transistors, simplifies the computer's storage and computing structure, saves computing resources, and improves computing progress and efficiency.

[0196] The memory device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, the electronic device may include a memory device and a processor. The memory device may store data required for the operation of the electronic device or obtained during operation. The processor may operate based on the data and / or application stored in the memory device. Such electronic devices include smart phones, computers, tablet computers (PCs), wearable smart devices, artificial intelligence devices, mobile power supplies, etc.

[0197] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0198] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A storage device, comprising: substrate; The memory cell array on the substrate includes a plurality of memory cells. Each storage unit includes: A left stack and a right stack arranged alternately in the horizontal direction, each of the left stack and the right stack comprises a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer and a second NMOS layer sequentially stacked on the substrate, each of the PMOS layer, the first NMOS layer and the second NMOS layer comprises a first source / drain layer, a channel layer and a second source / drain layer stacked vertically, and the channel layer is laterally recessed relative to the first source / drain layer and the second source / drain layer; The gate stack is located between the first source / drain layer and the second source / drain layer in a vertical direction and is disposed on opposite sides of the channel layer to embed a lateral recess of the channel layer.

2. The memory device according to claim 1, further comprising: The hard mask layer is disposed on the first source / drain layer of the second NMOS layer.

3. The memory device according to claim 1, wherein: The gate stack includes a gate dielectric layer and a gate conductor layer, and the gate dielectric layer includes a work function regulating metal and a gate conductive metal disposed on the work function regulating metal.

4. The memory device according to claim 3, wherein: The gate conductor layer includes a p-type gate conductor layer and an n-type gate conductor layer, wherein: The p-type gate conductor layer is disposed between the first source / drain layer and the second source / drain layer of the PMOS layer; The n-type gate conductor layer is disposed between the first source / drain layer and the second source / drain layer of the first NMOS layer, and between the first source / drain layer and the second source / drain layer of the second NMOS layer.

5. The memory device according to claim 3, wherein: The lateral peripheral portions of the first source / drain layer and the second source / drain layer are recessed and the recessed portions are filled with a third SiC layer; and / or A lateral peripheral portion of the gate conductor layer is recessed and the recessed portion is filled with a third SiC layer.

6. The memory device according to claim 5, wherein: The outer sidewall of the third SiC layer is coplanar with the left and right stacking layers in a vertical direction.

7. The memory device according to claim 1, further comprising: A fifth SiO2 layer is formed on the substrate between the left stack and the right stack, wherein the top of the fifth SiO2 layer is higher than the bottom of the first source / drain layer of the PMOS layer and lower than the top of the first source / drain layer of the PMOS layer.

8. The memory device according to claim 7, further comprising: A first metal layer is formed on the fifth SiO2 layer between the left stack and the right stack, wherein the top of the first metal layer is higher than the top of the first source / drain layer of the PMOS layer and lower than the bottom of the second source / drain layer of the PMOS layer.

9. The memory device according to claim 8, further comprising: A sixth SiO2 layer and a second metal layer are sequentially formed on the first metal layer, The top of the sixth SiO2 layer is higher than the top of the first source / drain layer of the first NMOS layer and lower than the bottom of the second source / drain layer of the first NMOS layer; A top of the second metal layer is higher than a bottom of the second source / drain layer of the first NMOS layer and lower than a top of the second source / drain layer of the first NMOS layer.

10. The memory device according to claim 8, further comprising: A seventh SiO2 layer is formed on the fifth SiO2 layer, wherein a top of the seventh SiO2 layer is higher than a top of the first source / drain layer of the PMOS layer and lower than a bottom of the second source / drain layer of the PMOS layer.

11. The memory device according to claim 10, further comprising: A third metal layer is formed on the seventh SiO2 layer, wherein a top of the third metal layer is higher than a top of the first source / drain layer of the first NMOS layer and lower than a bottom of the second source / drain layer of the first NMOS layer.

12. The memory device according to claim 11, further comprising: a fourth SiC layer, formed on the third metal layer, wherein a top of the fourth SiC layer is higher than a bottom of the first source / drain layer of the second NMOS layer and lower than a top of the first source / drain layer of the second NMOS layer; The middle position of the top of the fourth SiC layer is relatively recessed and exposes the third metal layer, forming a second spacing portion separated from the left and right and having a step structure.

13. The memory device according to claim 12, wherein: A fourth metal layer higher than the top of the fourth SiC layer is formed on the inner sidewall and the bottom surface of the second spacer; The top of the fourth metal layer is higher than the bottom of the first source / drain layer of the second NMOS layer and lower than the top of the first source / drain layer of the second NMOS layer.

14. The memory device according to claim 4, further comprising: a fifth metal layer, formed on a first deep end surface of the left stack and a second deep end surface of the right stack, and contacting an outer side wall of the n-type gate conductor layer in the second NMOS layer; wherein the first deep end surface and the second deep end surface are two end surfaces arranged opposite to each other in the depth direction; A word line is connected to the fifth metal layer, and the word line spans the first deep end surface of the left stack and the second deep end surface of the right stack of the same memory cell to contact and electrically connect to the outer side wall of the n-type gate conductor layer of the left stack or the right stack in the second NMOS layer.

15. The memory device according to claim 1, further comprising: A first contact portion and a second contact portion, wherein the first contact portion is embedded in the second source / drain layer of the second NMOS layer of the left stack, and the second contact portion is embedded in the second source / drain layer of the second NMOS layer of the right stack, and the first contact portion and the second contact portion are respectively connected to a first bit line and a second bit line with opposite signals.

16. A method for preparing a memory device, comprising: A left stack and a right stack are formed on a substrate and are arranged alternately in a horizontal direction. The left stack and the right stack both include a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer and a second NMOS layer stacked in sequence. The PMOS layer, the first NMOS layer and the second NMOS layer both include a first source / drain layer, a channel layer and a second source / drain layer stacked vertically. The channel layer is laterally recessed relative to the first source / drain layer and the second source / drain layer. Depositing a gate dielectric layer and a p-type gate conductor layer in sequence in the lateral recess of the channel layer; Depositing SiO2 at the bottom of the left stack and the right stack, then etching the SiO2 and stopping at a first preset height to form a first spacer; Etching the p-type gate conductor layer at the corresponding positions of the first NMOS layer and the second NMOS layer, and depositing the n-type gate conductor layer at the corresponding positions of the etched p-type gate conductor layer; The first spacer is etched to form a memory cell, and the memory device includes a memory cell array including a plurality of the memory cells.

17. The preparation method according to claim 16, wherein: The material of the first source / drain layer and the second source / drain layer is Si, and the material of the lower isolation layer, the upper isolation layer and the channel layer is SiGe.

18. The preparation method according to claim 16, wherein: The first preset height is higher than a bottom of the second source / drain layer of the PMOS layer and lower than a top of the first source / drain layer of the first NMOS layer.

19. The preparation method according to claim 16, further comprising: Partially etching the first source / drain layer and the second source / drain layer along a horizontal direction at a first deep position of the left stack and a second deep position of the right stack; and / or At the second deep position of the left stack and the first deep position of the right stack, the p-type gate conductor layer and the n-type gate conductor layer are partially etched along the horizontal direction; wherein the first deep position and the second deep position are two positions relatively arranged along the depth direction.

20. The preparation method according to claim 19, wherein: The etching depths of the first source / drain layer, the second source / drain layer, the p-type gate conductor layer and the n-type gate conductor layer are each half of the p-type gate conductor layer or the n-type gate conductor layer in the horizontal direction.

21. The preparation method according to claim 19, further comprising: Depositing a third SiC layer in the area where the first source / drain layer and the second source / drain layer are partially etched; A third SiC layer is deposited in the regions where the p-type gate conductor layer and the n-type gate conductor layer are partially etched, so that the outer sidewalls of the third SiC layer are coplanar with the left stack and the right stack in a vertical direction.

22. The preparation method according to claim 16, further comprising: A fifth SiO2 layer is deposited on the substrate between the left and right stack layers, so that a top of the fifth SiO2 layer is higher than a bottom of the first source / drain layer of the PMOS layer and lower than a top of the first source / drain layer of the PMOS layer.

23. The preparation method according to claim 22, further comprising: A first metal layer is deposited on the fifth SiO2 layer between the left and right stacks, so that a top of the first metal layer is higher than a top of the first source / drain layer of the PMOS layer and lower than a bottom of the second source / drain layer of the PMOS layer.

24. The preparation method according to claim 23, wherein: Before the step of depositing the first metal layer, the method further comprises: The surface of the fifth SiO2 layer is processed by a metal silicide process.

25. The preparation method according to claim 23, further comprising: forming a sixth SiO2 layer and a second metal layer on the first metal layer in sequence, so that a top of the sixth SiO2 layer is higher than a top of the first source / drain layer of the first NMOS layer and lower than a bottom of the second source / drain layer of the first NMOS layer; as well as A top of the second metal layer is higher than a bottom of the second source / drain layer of the first NMOS layer and lower than a top of the second source / drain layer of the first NMOS layer.

26. The preparation method according to claim 23, further comprising: A seventh SiO2 layer is deposited on the fifth SiO2 layer, so that a top of the seventh SiO2 layer is higher than a top of the first source / drain layer of the PMOS layer and lower than a bottom of the second source / drain layer of the PMOS layer.

27. The preparation method according to claim 26, further comprising: A third metal layer is deposited on the seventh SiO2 layer, so that a top of the third metal layer is higher than a top of the first source / drain layer of the first NMOS layer and lower than a bottom of the second source / drain layer of the first NMOS layer.

28. The preparation method according to claim 27, further comprising: Depositing a fourth SiC layer on the third metal layer so that a top of the fourth SiC layer is higher than a bottom of the first source / drain layer of the second NMOS layer and lower than a top of the first source / drain layer of the second NMOS layer; The top middle position of the fourth SiC layer is etched and stopped at the upper surface of the third metal layer to form a second spacer separated from the left and right and having a step structure.

29. The preparation method according to claim 28, further comprising: A fourth metal layer is deposited on the inner sidewall, bottom surface and upper surface of the second spacer, so that the top of the fourth metal layer is higher than the bottom of the first source / drain layer of the second NMOS layer and lower than the top of the first source / drain layer of the second NMOS layer.

30. The preparation method according to claim 16, further comprising: A fifth metal layer is deposited on the outer side wall of the n-type gate conductor layer in the second NMOS layer, so that the fifth metal layer bridges the first deep end surface of the left stack and the second deep end surface of the right stack on the same storage unit, so as to contact and be electrically connected to the outer side wall of the n-type gate conductor layer of the left stack or the right stack in the second NMOS layer; wherein the first deep end surface and the second deep end surface are two end surfaces arranged opposite to each other along the depth direction.

31. The preparation method according to claim 16, further comprising: Embedding a first contact portion on the second source / drain layer of the second NMOS layer of the left stack, and embedding a second contact portion on the second source / drain layer of the second NMOS layer of the right stack; The first contact portion and the second contact portion are respectively connected to a first bit line and a second bit line having opposite signals.

32. An electronic device comprising the storage device according to any one of claims 1 to 16.

33. The electronic device according to claim 32, wherein: The electronic devices include smart phones, computers, tablet computers, wearable smart devices, artificial intelligence devices, and mobile power supplies.

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