A TFT-based analog-to-digital converter circuit

Abstract

The present invention discloses a TFT-based analog-to-digital converter circuit that can meet a certain conversion rate. The analog-to-digital converter circuit includes a comparator circuit and a decoding circuit. The comparator circuit is composed of three AND gates connected in parallel; the input voltage is electrically connected to the input end of the AND gate; the decoding circuit is composed of three NOT gates and four NAND gates electrically connected; the output ends of the AND gates on the comparator circuit are respectively electrically connected to the decoding circuit. The present invention converts the output result of the voltage comparison circuit into a digital signal output by combining NAND gates based on dual-gate thin-film transistors. The present invention uses thin-film transistors with a simple preparation process and higher integration, which not only reduces production costs but also is suitable for large-scale preparation. In addition, the voltage comparison circuit composed of the dual-gate thin-film transistors of the present invention can use the top gate to regulate the bottom threshold voltage to adjust the size of the comparison voltage, making the voltage comparison circuit more flexible and practical.

Description

Technical Field

[0001] The present invention relates to a converter circuit, and in particular to a TFT-based analog-to-digital converter circuit. Background Art

[0002] The rapid development of digital electronics, particularly the widespread application of digital computing and signal processing in medical imaging, instrumentation, communications, and other fields, has made it increasingly common to process analog signals using digital circuits. Therefore, the digitization of analog signals is a growing trend in information technology, and analog-to-digital converters (ADCs) play a key role in this process.

[0003] Generally, an analog-to-digital converter (ADC) has three basic functions: sampling, quantization, and encoding. How these three functions are implemented determines the ADC's circuit structure and performance. There are many types of ADCs, and several commonly used ones are described below.

[0004] (1) Integrating analog-to-digital converter

[0005] Integrating ADCs are widely used in low-speed, high-precision measurement applications, particularly in digital instrumentation. Integrating ADCs offer two conversion modes: single-integration and dual-integration. However, integrating ADCs operate by converting electrical signals into time signals and then counting time intervals, indirectly converting analog quantities into digital quantities. Their primary drawback is low conversion accuracy, which is primarily affected by the accuracy of the ramp voltage generator and comparator, as well as the stability of the clock pulse.

[0006] However, in order to improve the conversion accuracy of the integral analog-to-digital converter under the same conditions, a dual-integral analog-to-digital converter can be used, such as Figure 1 As shown in Figure 1, a dual-integration ADC integrates the analog input twice, partially offsetting the error introduced by the ramp generator and improving conversion accuracy to 22 bits. This provides enhanced noise immunity, but this increased accuracy comes at the expense of a lower conversion rate, making it primarily used in low-speed conversion applications, such as measurement.

[0007] (2) Successive approximation analog-to-digital converter

[0008] The successive approximation analog-to-digital converter is widely used in the field of analog-to-digital conversion today. It is an analog-to-digital converter based on the principle of binary search, similar to a scale weighing objects. That is, the analog signal to be converted is compared with different known reference voltages multiple times, so that the converted digital value approaches the corresponding value of the analog value in numerical value. The characteristics are high conversion speed; when the resolution is lower than 12 bits, the circuit is cheaper to implement than other converters; the conversion time is fixed. However, this kind of digital-to-analog conversion circuit requires a high-precision resistor or capacitor matching network to form a high-precision circuit, so the accuracy will not be too high. For example Figure 2 Shown is the block diagram of a successive approximation analog-to-digital converter.

[0009] (3) Parallel analog-to-digital converter

[0010] The parallel converter has the fastest conversion speed among all analog-to-digital converters and is the standard method for realizing ultra-high-speed converters. It is also a direct analog-to-digital conversion method. Figure 3 The input signal is divided by a resistor string and fed into 2N parallel comparators. The comparator outputs are fed into an encoder and encoded to produce the corresponding digital output. This significantly reduces the number of intermediate steps in the conversion process, as each digital code is generated almost simultaneously. Therefore, its main advantage is its fast conversion speed, making it particularly suitable for high-speed conversion applications. However, its disadvantage is that it compromises both resolution and power consumption. Resolution is generally below 10 bits, and when accuracy is high, power consumption is high. This is primarily due to the influence of circuit implementation.

[0011] The above three types of CMOS-based analog-to-digital conversion circuits are relatively common, and existing technologies all utilize CMOS-based ADCs. However, their silicon substrates exhibit poor ductility and bendability, and their output interfaces are complex. Currently, ADCs based on thin-film transistors are relatively rare, and limited by the performance of thin-film transistors, these ADCs are primarily designed for functional purposes, resulting in lower conversion speeds and accuracy than CMOS circuits.

[0012] In summary, it is necessary to study a TFT-based analog-to-digital converter circuit. Summary of the Invention

[0013] To address these shortcomings, the present invention proposes a TFT-based analog-to-digital converter circuit that incorporates dual-gate thin-film transistors (TFTs). This improves design adaptability and makes the circuit more concise and efficient. The additional top gate can adjust the operating state of the TFT, allowing for a wider range of designs compared to single-gate TFTs. It also features strong anti-interference capabilities, flexibility, integration, simple production processes, and low cost.

[0014] The technical solution of the present invention is achieved as follows:

[0015] A TFT-based analog-to-digital converter circuit includes a comparator circuit and a decoding circuit: the comparator circuit is composed of three AND gates connected in parallel; the input voltage is electrically connected to the input end of the AND gate; the decoding circuit is composed of three NOT gates and four NAND gates electrically connected; the output ends of the AND gates on the comparator circuit are respectively electrically connected to the decoding circuit.

[0016] The three AND gates of the present invention are respectively a first AND gate, a second AND gate and a third AND gate, and the circuit structures of the three AND gates are exactly the same.

[0017] The three NOT gates of the present invention are respectively a first NOT gate, a second NOT gate and a third NOT gate, and the circuit structures of the three NOT gates are exactly the same.

[0018] The four NAND gates of the present invention are respectively a first NAND gate, a second NAND gate, a third NAND gate and a fourth NAND gate, and the circuit structures of the four NAND gates are exactly the same.

[0019] The second AND gate of the present invention includes a first-stage load thin film transistor, a first-stage drive thin film transistor, a second-stage load thin film transistor and a second-stage drive thin film transistor; the top gates of the first-stage load thin film transistor and the second-stage load thin film transistor are respectively connected to their back gates; the drains of the first-stage load thin film transistor and the second-stage load thin film transistor are both connected to the power supply voltage.

[0020] The source of the first-stage load thin film transistor of the present invention is respectively connected to the drain of the first-stage drive thin film transistor and the top gate of the second-stage drive thin film transistor; the source of the second-stage load thin film transistor is respectively connected to the drain of the second-stage drive thin film transistor and the output voltage signal.

[0021] The top gate of the first-level driving thin film transistor of the present invention is connected to the input voltage signal, and its back gate is connected to the first external bias; the back gate of the second-level driving thin film transistor is connected to the second external bias; the source of the first-level driving thin film transistor and the source of the second-level driving thin film transistor are both grounded.

[0022] The third NAND gate of the present invention includes a third-stage load thin film transistor, a first input thin film transistor and a second input thin film transistor electrically connected in sequence; the top gate of the first input thin film transistor is connected to the first input voltage signal, and the top gate of the second input thin film transistor is connected to the second input voltage signal; the back gate of the first input thin film transistor is connected to the back gate of the second input transistor, and both are connected to a third external bias.

[0023] In the present invention, the source electrode of the first input thin film transistor is connected to the drain electrode of the second input thin film transistor; the source electrode of the second input thin film transistor is grounded.

[0024] The drain of the first input thin film transistor of the present invention is respectively connected to the source and output voltage signal of the third load thin film transistor; the top gate of the third load thin film transistor is connected to its back gate; the drain of the third load thin film transistor is connected to the power supply voltage.

[0025] The thin film transistors in the first-stage load thin film transistor, the second-stage load thin film transistor, the third-stage load thin film transistor, the first-stage drive thin film transistor, the second-stage drive thin film transistor, the first input thin film transistor and the second input thin film transistor of the present invention adopt a single-gate or double-gate structure, and the material of the thin film transistor is amorphous silicon, polycrystalline silicon or amorphous indium gallium zinc oxide.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] The present invention utilizes an integrated analog-to-digital conversion circuit composed of thin film transistors, and the preparation process is fully compatible with the CMOS process, thereby reducing production costs and improving integration.

[0028] The present invention uses a dual-gate thin film transistor as an input transistor of a voltage comparison circuit, which can compare the input voltage with the threshold voltage of the transistor. The ingenious design reduces the number of devices, lowers the overall circuit area and manufacturing cost.

[0029] The present invention adjusts the threshold voltage of the thin film transistor by dividing the reference voltage, thereby adjusting the comparison voltage of the voltage comparison circuit, reducing excessive external bias voltage, and also quantifying the relationship between the reference voltage and the comparison voltage.

[0030] The thin-film transistors of the present invention use different aspect ratios. The thin-film transistors acting as load transistors have a smaller aspect ratio, while the driver thin-film transistors, which primarily receive signals, have a larger aspect ratio. By increasing the aspect ratio of the driver thin-film transistors in the comparator circuit, a higher comparison accuracy can be achieved.

[0031] In the decoding circuit of the present invention, some of the dual-gate thin-film transistors in the NAND gate and the NOT gate have an external bias voltage for top gate power supply, which can prevent the threshold voltage of some thin-film transistors from drifting negatively due to process reasons by adjusting the threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A schematic diagram of a dual-integral analog-to-digital converter in the background art.

[0034] Figure 2 for Figure 1 Schematic diagram of Vin measurement.

[0035] Figure 3 FIG. 4 is a structural diagram of a successive approximation analog-to-digital converter in the background art.

[0036] Figure 4 2 is a structural diagram of a parallel analog-to-digital converter in the background technology.

[0037] Figure 5 FIG. 4 is a complete schematic diagram of the analog-to-digital converter circuit of the present invention.

[0038] Figure 6 FIG. 4 is a static voltage output curve of a single comparator circuit of the present invention.

[0039] Figure 7 This is a timing voltage output curve of a single comparator circuit of the present invention.

[0040] Figure 8 A schematic diagram of a reference voltage circuit in which a bias voltage is used as a reference voltage is provided for the present invention.

[0041] Figure 9 This is a circuit structure diagram of the NAND gate of the present invention.

[0042] Figure 10 This is a circuit simulation result diagram of the NAND gate of the present invention.

[0043] Figure 11 It is a diode-connected amplifier circuit of the NOT gate circuit of the present invention.

[0044] Figure 12 It is a zero-Vgs amplifier circuit of the NOT gate circuit of the present invention.

[0045] Figure 13 for Figure 11 The static output voltage curve.

[0046] Figure 14 for Figure 12 The static output voltage curve.

[0047] Figure 15 FIG. 4 is a schematic structural diagram of another embodiment of a comparator circuit of the present invention.

[0048] Figure 16 、 17 For the present invention Figure 15 Static input and output voltage diagram when the width-to-length ratio of the driving tubes TFT2 and TFT4 is 100um / 10um.

[0049] Figure 18 、 19 For the present invention Figure 15 Static input and output voltage diagram when the width-to-length ratio of the driving tubes TFT2 and TFT4 is 200um / 10um. DETAILED DESCRIPTION

[0050] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0051] In order to facilitate and clarify the description of the following embodiments, some terms are explained before the specific embodiments of the present invention are described in detail. The following explanations are applied to this specification and the claims.

[0052] The TFT in the present invention stands for Thin Film Transistor, which means thin film field effect transistor in Chinese. It means that each liquid crystal pixel on the liquid crystal display is driven by the thin film transistor integrated therein, so that the screen information can be displayed at high speed, high brightness and high contrast. TFT belongs to active matrix liquid crystal display.

[0053] The English terms VDD, Output, Input, V_bias, V_bias1, V_bias2, etc. that appear in the present invention are codes and do not represent any other meanings.

[0054] Reference Figure 5-19 The present invention discloses a TFT-based analog-to-digital converter circuit, comprising a comparator circuit and a decoding circuit. The comparator circuit comprises three AND gates connected in parallel, the three AND gates being a first AND gate, a second AND gate, and a third AND gate, and having identical circuit structures. An input voltage is electrically connected to the input terminals of the AND gates. The decoding circuit comprises three NOT gates and four NAND gates electrically connected. The three NOT gates are a first NOT gate, a second NOT gate, and a third NOT gate, and having identical circuit structures. The four NAND gates are a first NAND gate, a second NAND gate, a third NAND gate, and a fourth NAND gate, and having identical circuit structures. The output terminals of the AND gates on the comparator circuit are electrically connected to the decoding circuit. The present invention employs a dual-gate thin-film transistor as the input transistor of the comparator circuit, which can compare the input voltage with the threshold voltage of the transistor. This ingenious design reduces the number of components, lowering the overall circuit area and manufacturing cost.

[0055] Preferably, the second AND gate includes a first-stage load thin film transistor T1, a first-stage drive thin film transistor T2, a second-stage load thin film transistor T3 and a second-stage drive thin film transistor T4; the top gates of the first-stage load thin film transistor T1 and the second-stage load thin film transistor T3 are respectively connected to their back gates; the drains of the first-stage load thin film transistor T1 and the second-stage load thin film transistor T3 are both connected to the power supply voltage VDD.

[0056] Preferably, the source of the first-stage load thin film transistor T1 is respectively connected to the drain of the first-stage drive thin film transistor T2 and the top gate of the second-stage drive thin film transistor T4; the source of the second-stage load thin film transistor T3 is respectively connected to the drain of the second-stage drive thin film transistor T4 and the output voltage signal Output.

[0057] Preferably, the top gate of the first-stage driving thin film transistor T2 is connected to the input voltage signal Input, and its back gate is connected to the first external bias V_bias1; the back gate of the second-stage driving thin film transistor is connected to the second external bias V_bias2; the source of the first-stage driving thin film transistor T2 and the source of the second-stage driving thin film transistor T4 are both grounded.

[0058] Preferably, the third NAND gate includes a third-stage load thin film transistor T1, a first input thin film transistor T2, and a second input thin film transistor T3 electrically connected in sequence; the top gate of the first input thin film transistor T2 is connected to the first input voltage signal Input1, and the top gate of the second input thin film transistor T3 is connected to the second input voltage signal Input2; the back gate of the first input thin film transistor T2 is connected to the back gate of the second input transistor T3, and both are connected to a third external bias voltage V_bias.

[0059] Preferably, the source of the first input thin film transistor T2 is connected to the drain of the second input thin film transistor T3 ; and the source of the second input thin film transistor T3 is grounded.

[0060] Preferably, the drain of the first input thin film transistor T2 is respectively connected to the source of the third-stage load thin film transistor T1 and the output voltage signal Output; the top gate of the third-stage load thin film transistor T1 is connected to its back gate; and the drain of the third-stage load thin film transistor T1 is connected to the power supply voltage VDD.

[0061] In the load thin film transistor, the driving thin film transistor and the input thin film transistor of the present invention, the thin film transistor structure can adopt single gate and double gate, the thin film transistor material can be amorphous silicon, polycrystalline silicon and amorphous indium gallium zinc oxide (IGZO) and other materials, and the channel shape of the double gate thin film transistor can be a planar channel, a π-type channel and a 3D fin-type channel and other shapes.

[0062] like Figure 5As shown, the input voltage is compared with the reference voltage, which is adjusted according to the bias voltage of the comparator, and then the comparison result is obtained. The comparison result enters the decoding circuit part, and through the cooperation of the NOT gate and the NAND gate, the output of the comparator circuit is converted into a two-digital signal for output. In the comparator circuit, the reference voltage compared with the input signal is changed by changing the top gate voltage V_bias1 of the first-stage driving thin-film transistor T2. In fact, the voltage compared with the input signal is close to the threshold voltage of the first-stage driving thin-film transistor T2. At the same time, the top gate and the threshold voltage have the following relationship:

[0063] The change of the top gate voltage will affect the threshold voltage of the first-stage driving thin film transistor T2. When the active layer material is amorphous silicon, the following equation exists:

[0064] V T =V T0 -βV GT

[0065] Where V T is the threshold voltage of the back TFT, V T0 is the threshold voltage of the back TFT when the top gate voltage is 0V, V GT To actually load the top gate voltage, the value of β can be measured by different V GT Get, or

[0066] Among them C ib and C it are the insulation layer capacitances of the back gate and top gate, respectively, C S is the capacitance of the a-Si:H active layer, C SST is the effective capacitance at the top a-Si:H / a-SiNx:H interface.

[0067] When other active layer materials are used, the top gate's effect on regulating the threshold voltage is similar to that of an amorphous silicon active layer.

[0068] From the above, it can be seen that the top gate of the first-stage driving thin-film transistor T2 can regulate the threshold voltage, and the change in the threshold voltage causes the region where the first-stage driving thin-film transistor T2 is turned on to change, which leads to a change in the region where the source-drain current of the first-stage driving thin-film transistor T2 changes sharply. During operation, the first-stage load thin-film transistor T1 is equivalent to a resistor. The opening of the back gate of the first-stage driving thin-film transistor T2 causes the source-drain current of the first-stage driving thin-film transistor T2 to increase sharply, causing the output voltage to drop sharply. This sharp change process can be used to compare the size of the input signal. The top gate changes the threshold voltage of the first-stage driving thin-film transistor T2, thereby changing the region where the source-drain current of the first-stage driving thin-film transistor T2 changes sharply, thereby changing the reference voltage for comparison. The present invention adjusts the threshold voltage of the thin-film transistor through reference voltage division, thereby adjusting the comparison voltage of the voltage comparison circuit, reducing excessive external bias, and also quantifying the relationship between the reference voltage and the comparison voltage.

[0069] V_bias2 is a fixed value that makes the reference voltage of the second-level comparison at VDD / 2, that is, half of the power supply voltage. Its function is to make the output value after the first-level comparison closer to the "full value" output (the output value smaller than the reference value is closer to 0, and the output value larger than the reference value is closer to the power supply voltage), thereby improving the comparison accuracy. Figure 6 and Figure 7 As shown in the figure, it is a schematic diagram of the simulation results of the comparator circuit, where Figure 6 is the static voltage output curve of a single comparator circuit, Figure 7 The following is a timing voltage output curve for a single comparator circuit; the theoretical comparison accuracy can reach 0.15V, and the delay time is approximately 20µs. As can be seen, the reference voltage for comparison can range from -2.3V to 1.7V, and in practice, it can operate normally with a reference voltage range of -5V to 5V. If a wider reference voltage range is required, the power supply voltage must be increased. Adjusting the bias voltage V_bias1 to a larger positive voltage or a smaller negative voltage will prevent distortion of the output voltage curve.

[0070] The problem of setting the reference voltage of the comparator can be reasonably adjusted by confirming the input voltage range. However, the setting of the comparison voltage value is divided by the specified value. The total voltage range is set to X = Vh-V1. Then the reference voltage of the first comparator should be set to X / 4 + V1, the second comparator to X / 2 + V1, and the third comparator to 3*X / 4 + V1. In this design, the bias voltage for reference voltage adjustment is provided by a resistor divider, and the resistor is a thin film transistor with the source and drain short-circuited, such as Figure 8 shown. Figure 8The four thin film transistors have the same aspect ratio and the same process, so the on-resistance is approximately equal after the source and drain are short-circuited. The voltages generated by the first V_bias1, the second V_bias1 and the third V_bias1 are also approximately similar to the reference voltage interval.

[0071] like Figure 9 As shown, there are two input signals. The external bias voltage V_bias controls the top gate voltage to adjust the working state of the thin film transistor. The top gate and bottom gate of the third-stage load thin film transistor T1 are short-circuited to the source of the third-stage load thin film transistor T1, and form a feedback effect with the output. When the output voltage is high, it will act on the top gate and bottom gate of the third-stage load thin film transistor T1 to make the third-stage load thin film transistor T1 open more thoroughly, so that the output voltage is pulled closer to the power supply voltage; when the output voltage is low, it will act on the top gate and bottom gate of the third-stage load thin film transistor T1 to make the third-stage load thin film transistor T1 closed more thoroughly, which is equivalent to the third-stage load thin film transistor T1 becoming a large resistor to disconnect the output and the power supply voltage, so that the output voltage is pulled closer to the ground. Figure 10 ,Observe the simulation diagram, the changes in input level and output level are consistent with the logic table of the NAND gate.

[0072] Figure 11 and Figure 12 Figure 2 shows two different designs of the NOT gate in the decoding circuit. Both NOT gate designs can be used in the present invention. Figure 11 The static output voltage change curve of the designed circuit is smoother. Figure 12 The static output voltage change curve of the designed circuit is steeper. Figure 11 , the top gate and bottom gate of T1 are shorted to the drain, making T1 in a normally open state. When the output voltage decreases, the non-closed T1 will increase the opening degree requirement of T2, and the power consumption is also large. Figure 12 The top and bottom gates of T1 are both short-circuited to the source, so that T1 is regulated by the feedback of the output voltage. When the output voltage decreases, T1 will be closed to reduce the current flowing through it. In this way, the requirement for the opening degree of T2 will be reduced, and the circuit power consumption will also be reduced due to the reduction of the current flowing through T1.

[0073] In the decoding circuit of the present invention, some of the dual-gate thin-film transistors in the NAND gate and the NOT gate have an external bias voltage for top gate power supply, which can prevent the threshold voltage of some thin-film transistors from drifting negatively due to process reasons by adjusting the threshold voltage.

[0074] The thin film transistors of the present invention use different width-to-length ratios. The thin film transistors that act as load tubes use a smaller width-to-length ratio, while the driving thin film transistors that mainly receive signals use a larger width-to-length ratio. The width-to-length ratio of the thin film transistors that act as load tubes is less than W / L=10um / 10um, and the minimum experimental value is 10um / 200um. The width-to-length ratio of the thin film transistors that act as drive thin film transistors is greater than 100um / 10um, and the maximum experimental value is 1000um / 10um. The reason why smaller and larger width-to-length ratios cannot be achieved is because of the area occupied by the transistors. The optimal width-to-length ratio is about 10um / 10um for the load tube and 200um / 10um for the drive tube, which is more suitable for amplifying the input signal without occupying too much area. Therefore, the present invention can obtain lower comparison accuracy by increasing the width-to-length ratio of the driving thin film transistor in the comparator circuit. Reference Figure 15-19 , Figure 15 FIG. 1 is a schematic structural diagram of another embodiment of a single comparator circuit. Figure 5 T1 and T3 in the figure are dual-gate TFTs. Figure 15 TFT1 and TFT3 are single-gate TFTs, and both circuits can realize the function of comparator circuits. Figure 16 、 17 The static input and output voltage diagram of a single comparator circuit when the width-to-length ratio of the driving tubes TFT2 and TFT4 is 100um / 10um can be obtained from Figure 17 It can be seen that under this aspect ratio, the comparison accuracy is between -0.06V and 0.05V, that is, if the difference between the two values ​​is between 0.11V, the comparison result of the two values ​​cannot be output by adjusting the comparison range of the comparator. The result will be in an uncertain state between high and low levels. Generally, the high level range and the low level range are set, and the remaining unset potential range cannot be determined.

[0075] like Figure 18 、 19 The figure shows the static input and output voltage of a single comparator circuit when the aspect ratio of the driving tubes TFT2 and TFT4 is 200um / 10um. At this time, the aspect ratio of the driving tubes TFT2 and TFT4 is changed from the original 100um / 10um to 200um / 10um. It can be seen that the range of the uncertain state is about 0.035V. The range of the uncertain state of the comparator circuit with the previous smaller aspect ratio driving tube is 0.11V. It can be clearly seen that as the aspect ratio of the driving tube increases, the range of the uncertain state becomes smaller, the distinguishable voltage value becomes smaller, the comparison accuracy of the comparator becomes smaller, and the effect is better.

[0076] The present invention utilizes an integrated analog-to-digital conversion circuit composed of thin film transistors, and the preparation process is fully compatible with the CMOS process, thereby reducing production costs and improving integration.

[0077] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A TFT-based analog-to-digital converter circuit, characterized in that: It includes: The comparator circuit is composed of three AND gates connected in parallel; the input voltage is electrically connected to the first input terminal of the AND gate, and the second input terminal is externally connected to the bias voltage; The decoding circuit is composed of three NOT gates and four NAND gates electrically connected; the output ends of the AND gates on the comparator circuit are electrically connected to the decoding circuit, The three AND gates are the first AND gate, the second AND gate and the third AND gate, the three NOT gates are the first NOT gate, the second NOT gate and the third NOT gate, and the four NAND gates are the first NAND gate, the second NAND gate, the third NAND gate and the fourth NAND gate. The input terminal of the first NOT gate is connected to the output terminal of the second AND gate, and the output terminal of the first NOT gate is connected to the first input terminal of the second NAND gate; The input terminal of the second NOT gate is connected to the output terminal of the third AND gate, and the output terminal of the second NOT gate is connected to the second input terminal of the second NAND gate; The first input terminal of the first NAND gate is connected to the output terminal of the second AND gate, the second input terminal of the first NAND gate is connected to the output terminal of the third AND gate, the output terminal of the first NAND gate is connected to the first input terminal of the third NAND gate, and the output terminal of the second NAND gate is connected to the second input terminal of the third NAND gate; The first input terminal of the fourth NAND gate is connected to the output terminal of the first AND gate, the second input terminal is connected to the output terminal of the third NAND gate, the output terminal of the fourth NAND gate is connected to the input terminal of the third NOT gate, and the output terminal of the third NOT gate outputs the converted signal.

2. The TFT-based analog-to-digital converter circuit according to claim 1, wherein: The circuit structures of the three AND gates are exactly the same.

3. The TFT-based analog-to-digital converter circuit according to claim 2, wherein: The circuit structures of the three NOT gates are exactly the same.

4. The TFT-based analog-to-digital converter circuit according to claim 3, wherein: The circuit structures of the four NAND gates are exactly the same.

5. The TFT-based analog-to-digital converter circuit according to claim 4, wherein: The second AND gate includes a first-stage load thin film transistor, a first-stage drive thin film transistor, a second-stage load thin film transistor, and a second-stage drive thin film transistor; the top gates of the first-stage load thin film transistor and the second-stage load thin film transistor are respectively connected to their back gates; The drain of the first-stage load thin film transistor and the drain of the second-stage load thin film transistor are both connected to the power supply voltage. The source of the first-stage load thin film transistor is connected to the drain of the first-stage drive thin film transistor and the top gate of the second-stage drive thin film transistor respectively; the source of the second-stage load thin film transistor is connected to the drain of the second-stage drive thin film transistor and the output voltage signal respectively. The top gate of the first-stage driving thin film transistor is connected to the input voltage signal, and the back gate thereof is connected to the first external bias voltage; The back gate of the second-stage driving thin film transistor is connected to the second external bias voltage; the source of the first-stage driving thin film transistor and the source of the second-stage driving thin film transistor are both grounded.

6. The TFT-based analog-to-digital converter circuit according to claim 5, wherein: The third NAND gate includes a third-stage load thin film transistor, a first input thin film transistor, and a second input thin film transistor electrically connected in sequence; the top gate of the first input thin film transistor is connected to the first input voltage signal, and the top gate of the second input thin film transistor is connected to the second input voltage signal; the back gate of the first input thin film transistor is connected to the back gate of the second input transistor, and both are connected to a third external bias voltage. The source of the first input thin film transistor is connected to the drain of the second input thin film transistor; the source of the second input thin film transistor is grounded; the drain of the first input thin film transistor is respectively connected to the source of the third-stage load thin film transistor and the output voltage signal; The top gate of the third-stage load thin film transistor is connected to the back gate thereof; The drain of the third-stage load thin film transistor is connected to the power supply voltage.

7. The TFT-based analog-to-digital converter circuit according to claim 5 or 6, wherein: The thin film transistors in the first-stage load thin film transistor, the second-stage load thin film transistor, the third-stage load thin film transistor, the first-stage drive thin film transistor, the second-stage drive thin film transistor, the first input thin film transistor and the second input thin film transistor have a single-gate or double-gate structure, and the material of the thin film transistor is amorphous silicon, polycrystalline silicon or amorphous indium gallium zinc oxide.

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