A JTAG control device
By designing a JTAG control device that includes master TAP and slave TAP controllers, it supports multiple mode switching connection methods, solving the problem of redundancy and long time in SoC testing of traditional JTAG connection methods, and achieving efficient and flexible testing methods. Reduced testing costs.
Patent Information
- Application Number
- CN202111432123.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-11-29
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2041-11-29
AI Technical Summary
The traditional JTAG connection method is difficult to meet the testing needs when the SoC scale and complexity are increasing, resulting in the redundancy and long time of the test input vector and high cost.
Design a JTAG control device, including a master TAP controller and multiple slave TAP controllers, and through the selection unit configuration, the test clock signal, data signal and output signal is supported, and the single master TAP mode, master-slave TAP hybrid mode, and multi-slave TAP series connection is supported. Mode and parallel mode, flexible switching of connection mode to reduce test vectors and shorten test time.
It realizes flexibility in different design and testing scenarios in SoC, improves testing efficiency, significantly reduces testing costs, and has better versatility and reusability.
Smart Images
Figure CN114253184B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic control technology, and in particular to a JTAG control device. Background Art
[0002] In the design of ultra-large-scale digital integrated circuits, especially SoC (System on Chip), because of the complex functions and complete performance, the entire chip design is generally divided into different functional modules. The overall design process is to complete the design and verification of a single functional module first, and then form a large chip. In chip-level testing, the most commonly used communication between modules and between modules and the outside is based on the JTAG (Joint Test Action Group) protocol and its extension. Therefore, in the ATE (Automatic Test Equipment) test vector, design engineers and DFT (Design For Test, circuits designed for chip testing) engineers usually need to provide ATE test vectors based on JTAG instructions, and hand over the ATE test vectors to ATE test engineers for ATE testing. A complete JTAG TAP (Test Access Port) consists of a 16-bit state machine, and all test instructions are developed around JTAG.
[0003] The traditional JTAG connection method has redundant test vectors and a single fixed mode. As the scale and complexity of SoCs continue to increase, the traditional JTAG connection method has been difficult to meet the current SoC test requirements. Therefore, how to implement an efficient and flexible JTAG connection method to reduce test input vectors, shorten test time and save test costs has become increasingly important. Summary of the invention
[0004] In view of this, it is necessary to provide a JTAG control device for the above technical problems, the device comprising:
[0005] A master TAP controller and multiple slave TAP controllers;
[0006] a first selection unit, the first selection unit being connected to the test clock signal of the master TAP controller and each slave TAP controller, and being configured to select the test clock signal between the master TAP controller and any slave TAP controller according to a first register in the master TAP controller;
[0007] a second selection unit, the second selection unit being connected to the test data input signals of the master TAP controller and each slave TAP controller and configured to select the test data signal between the master TAP controller and any slave TAP controller according to a second register in the master TAP controller;
[0008] A third selection unit is connected to the output data signals of the master TAP controller and each TAP controller, and is configured to use one of the outputs of the master TAP controller and multiple slave TAP controllers as a test data output port of JTAG according to a third register in the master TAP controller.
[0009] In some embodiments, the master TAP controller and each slave TAP controller include a test clock port, a test reset port, a test data input port, a test mode selection port, and a test data output port;
[0010] The test clock port of each slave TAP controller is connected to the test clock port of the master TAP controller, and the test reset port of each slave TAP controller is connected to the test reset port of the master TAP controller.
[0011] In some embodiments, the test clock port, test reset port, test data input port, and test mode selection port of JTAG correspond to the test clock port, test reset port, test data input port, and test mode selection port of the main TAP controller, respectively.
[0012] In some embodiments, the master TAP controller further includes a first chip select port corresponding to each slave TAP controller, and the first selection unit includes a switch corresponding to each slave TAP controller;
[0013] One end of the switch is connected to a test mode selection port corresponding to the slave TAP controller, and the other end of the switch is connected to a first chip selection port corresponding to the slave TAP controller.
[0014] In some embodiments, the switch is an AND gate.
[0015] In some embodiments, the master TAP controller further comprises a second chip select port, and the second selection unit comprises a first selector corresponding to each slave TAP controller;
[0016] The output port of each first selector is connected to the test data input port of the corresponding slave TAP controller, the first input port of each first selector is connected to the test data output port of the master TAP controller, the second input end of the first selector corresponding to the first slave TAP controller is connected to the preset reference end, and among the two first selectors corresponding to any two adjacent slave TAP controllers, the second input end of the rear first selector is connected to the test data output port of the slave TAP controller corresponding to the front first selector, and the control port of each first selector is connected to the second chip select port.
[0017] In some embodiments, the preset reference terminal is grounded.
[0018] In some embodiments, the first selector is a two-to-one selector.
[0019] In some embodiments, the master TAP controller further comprises a third chip select port, and the third selection unit comprises a second selector;
[0020] The second selector has an input port, a control port and an output port corresponding to each slave TAP controller, each input end of the second selector is connected to the test data output port of the corresponding slave TAP controller, and the control port of the second selector is connected to the third chip select port.
[0021] In some embodiments, the device includes a single master TAP controller mode and a master-slave TAP controller mixed mode, wherein the master-slave TAP controller includes a single TAP controller and a single slave TAP controller series mode, a plurality of slave TAP controllers series mode and a plurality of slave TAP controllers parallel mode.
[0022] The above-mentioned JTAG control device of the present invention can meet the needs of different designs and test scenarios in SoC, such as hierarchical design of a single module or subsystem, test system control of multiple instances of a single module or subsystem, and a top-level connection method with good versatility and strong reusability. By switching between different modes to change the connection method of the circuit, the purpose of reducing test vectors and shortening test time can be achieved, thereby improving test efficiency and significantly reducing test costs. It has good versatility and flexibility. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.
[0024] Figure 1 A schematic diagram of the structure of a JTAG control device provided by one embodiment of the present invention;
[0025] Figure 2 A schematic diagram of a test flow of a JTAG control device is provided for one embodiment of the present invention;
[0026] Figure 3A A schematic diagram of a single-master TAP controller mode provided by an embodiment of the present invention;
[0027] Figure 3B A schematic diagram of a single TAP controller and a single slave TAP controller in series connection mode provided by an embodiment of the present invention;
[0028] Figure 3C A schematic diagram of a serial connection mode of multiple slave TAP controllers provided by an embodiment of the present invention;
[0029] Figure 3D A schematic diagram of a parallel mode of multiple slave TAP controllers provided by an embodiment of the present invention.
[0030] [Description of Reference Numerals]
[0031] 10: Main TAP controller;
[0032] 20: from TAP controller;
[0033] 30: first selection unit; 31: switch;
[0034] 40: second selection unit; 41: first selector; 411: first input port; 412: second input port;
[0035] 50: third selection unit; 51: second selector;
[0036] TCK: test clock port; TRST: test reset port; TDI: test data input port; TMS: test mode selection port; TDO: test data output port;
[0037] tms_en: first chip select port; tdi_sel: second chip select port; tdo_sel: third chip select port. DETAILED DESCRIPTION
[0038] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.
[0039] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two non-identical entities with the same name or non-identical parameters. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. The subsequent embodiments will not explain this one by one.
[0040] In one embodiment, please refer to Figure 1 As shown, the present invention provides a JTAG control device, the device comprising:
[0041] A master TAP controller 10 and a plurality of slave TAP controllers 20;
[0042] A first selection unit 30, the first selection unit 30 is connected to the test clock signal of the master TAP controller 10 and each slave TAP controller 20, and is configured to select the test clock signal between the master TAP controller 10 and any slave TAP controller 20 according to a first register (not shown in the figure) in the master TAP controller;
[0043] A second selection unit 40, the second selection unit 40 is connected to the test data input signal of the master TAP controller 10 and each slave TAP controller 20, and is configured to select the test data signal between the master TAP controller 10 and any slave TAP controller 20 according to a second register (not shown in the figure) in the master TAP controller;
[0044] A third selection unit 50 is connected to the output data signal of the main TAP controller 10 and each TAP controller, and is configured to use one of the outputs of the main TAP controller 10 and multiple slave TAP controllers 20 as a test data output port TDO of JTAG according to a third register (not shown in the figure) in the main TAP controller.
[0045] The above-mentioned JTAG control device can meet the needs of different design and test scenarios in SoC, such as hierarchical design of single module or subsystem, multi-instance test system control of single module or subsystem, top-level versatility, strong reusability of connection mode, and change the connection mode of circuit by switching between different modes to achieve the purpose of reducing test vectors and shortening test time, thereby improving test efficiency and significantly reducing test costs. It has good versatility and flexibility.
[0046] In some embodiments, please refer to Figure 1 As shown, the master TAP controller 10 and each slave TAP controller 20 include a test clock port TCK, a test reset port TRST, a test data input port TDI, a test mode selection port TMS and a test data output port TDO;
[0047] The test clock port TCK of each slave TAP controller 20 is connected to the test clock port TCK of the master TAP controller 10 , and the test reset port TRST of each slave TAP controller 20 is connected to the test reset port TRST of the master TAP controller 10 .
[0048] In some embodiments, the test clock port TCK, test reset port TRST, test data input port TDI, and test mode selection port TMS of JTAG correspond to the test clock port TCK, test reset port TRST, test data input port TDI, and test mode selection port TMS of the main TAP controller 10, respectively.
[0049] In some embodiments, please refer again to Figure 1 As shown, the master TAP controller 10 further includes a first chip selection port tms_en corresponding to each slave TAP controller 20, and the first selection unit 30 includes a switch 31 corresponding to each slave TAP controller 20;
[0050] One end of the switch 31 is connected to the test mode selection port TMS corresponding to the slave TAP controller 20 , and the other end of the switch 31 is connected to the first chip selection port tms_en corresponding to the slave TAP controller 20 .
[0051] In some embodiments, the switch 31 is an AND gate.
[0052] In some embodiments, please refer to Figure 1 As shown, the master TAP controller 10 further includes a second chip selection port tdi_sel, and the second selection unit 40 includes a first selector 41 corresponding to each slave TAP controller 20;
[0053] The output port of each first selector 41 is connected to the test data input port TDI of the corresponding slave TAP controller 20, the first input terminal 411 of each first selector 41 is connected to the test data output port TDO of the master TAP controller 10, the second input terminal 412 of the first selector 41 corresponding to the first slave TAP controller 20 is connected to the preset reference terminal, and among the two first selectors 41 corresponding to any two adjacent slave TAP controllers 20, the second input terminal 412 of the rear first selector 41 is connected to the test data output port TDO of the slave TAP controller 20 corresponding to the front first selector 41, and the control port of each first selector 41 is connected to the second chip select port tdi_sel.
[0054] Preferably, the preset reference terminal is grounded.
[0055] Preferably, the first selector 41 is a one-out-of-two selector.
[0056] In some embodiments, please refer to Figure 1 As shown, the main TAP controller 10 further includes a third chip selection port tdo_sel, and the third selection unit 50 includes a first selector 51;
[0057] The first selector 51 has an input port, a control port and an output port corresponding to each slave TAP controller 20, each input end of the first selector 51 is connected to the test data output port TDO of the corresponding slave TAP controller 20, and the control port of the first selector 51 is connected to the third chip select port tdo_sel.
[0058] In some embodiments, the device includes a single master TAP controller mode and a master-slave TAP controller mixed mode, wherein the master-slave TAP controller includes a single TAP controller and a single slave TAP controller series mode, a plurality of slave TAP controllers series mode and a plurality of slave TAP controllers parallel mode.
[0059] In another embodiment, in order to facilitate understanding of the technical solution of the present invention, the following takes n (n is a positive integer greater than or equal to 2) TAP controllers as an example, combined with Figure 1 The structure of the JTAG control device is shown to illustrate the implementation principle of the device of the present invention:
[0060] The main TAP controller controls the jump of the state machine according to the input sequence of the test clock port TMS, thereby completing the update of the instruction register and different data registers, and then completing the control of the working state of the functional module. The mode state switching control of the present invention corresponds to an instruction control of the instruction register in the main TAP controller; all the switch control bits of the slave TAP controller, the output control bits of the first selector and the second selector correspond to a data register in the main TAP controller. The test control process is completed by the main TAP controller, please refer to Figure 2 As shown, the test control flow is as follows:
[0061] Step 1: Instruction register update, i.e. mode control instruction;
[0062] Step 2, updating the mode control data register;
[0063] Step 3: Update the instruction register and test the working instruction.
[0064] Step 4: Update other data registers, test data, and return to step 2.
[0065] The connection modes supported by the JTAG control device of the present invention mainly include:
[0066] 1. Single-master TAP controller mode
[0067] Please refer to Figure 3A As shown in the figure, in the single master TAP controller mode, only the master TAP controller is enabled and all slave TAP controllers are turned off. When switching this mode, the slave TAP switch in the master TAP controller must be turned off and the control of the second selector is selected to the TDO output of the master TAP controller.
[0068] In this mode, the length of the instruction register and data control register is only the length of the corresponding register in the main TAP controller. There is no need to introduce additional instruction registers and data registers in the slave TAP controller by bypassing the slave TAP controller. The input vector is the shortest. This mode can be used for test control and vector input in some test modes at the top level of the chip.
[0069] 2. Master-Slave TAP Controller Hybrid Mode
[0070] (1) Single TAP controller and single slave TAP controller series mode
[0071] Please refer to Figure 3B As shown in the figure, in the single TAP controller and single slave TAP controller series mode, only the master TAP controller and any slave TAP controller are enabled, and other TAP controllers are turned off. When switching this mode, it is necessary to turn on a slave TAP switch and turn off other switches through the switch register in the master TAP controller, and select the second input port of the first selector of the slave TAP controller, and select the second selector to the TDO output of the turned-on slave TAP controller.
[0072] In this mode, the length of the instruction register and the data control register is the sum of the lengths of the corresponding registers in the master TAP and the enabled slave TAP controller. In this test mode, the test vector can accurately control a slave TAP control register for testing a module or subsystem.
[0073] (2) Multiple slave TAP controllers in series mode
[0074] Please refer to Figure 3C As shown, in the multiple slave TAP controller series mode, the master and slave TAP controllers will be connected in a traditional daisy chain manner. To enter this mode, it is necessary to turn on specific consecutive slave TAP switches and turn off the others. The TDI input of the first-stage slave TAP controller is selected to the TDO output port of the master TAP, and the TDI input of other slave TAP controllers is selected to the TDO output port of the previous-stage slave TAP, and the output second selector is selected to the TDO output of the last-stage enabled slave TAP controller.
[0075] In this mode, the length of the test control vector is longer, which is the sum of the test vectors of the master TAP and all enabled slave TAP controllers. This mode can be used for complex test scenarios where multiple modules or subsystems interact with each other.
[0076] (3) Multiple slave TAP controllers in parallel mode
[0077] Please refer to Figure 3D As shown, in the parallel mode of multiple slave TAP controllers, the master TAP can control the enabled slave TAP controllers by broadcasting. To enter this mode, the slave TAP switches to be enabled must be turned on, the others must be turned off, and the TDI first selector input of the slave TAP must be selected to the first input port.
[0078] In this mode, the length of the test control vector is the sum of the lengths of the master TAP and one slave TAP vector. This connection structure is used in test scenarios where the same functional module or subsystem is instantiated multiple times in the chip. It can complete parallel testing of the same functional modules, improve test efficiency, and save test costs.
[0079] The above-mentioned JTAG control device is of a universal structure, suitable for different module designs, has multiple working modes, and flexible switching of each mode to meet the needs of different test scenarios. The series-parallel application method improves the control flexibility and shortens the test vector.
[0080] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0081] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A JTAG control device, characterized in that: The device comprises: A master TAP controller and multiple slave TAP controllers; a first selection unit, the first selection unit being connected to the test clock signal of the master TAP controller and each slave TAP controller, and being configured to select the test clock signal between the master TAP controller and any slave TAP controller according to a first register in the master TAP controller; a second selection unit, the second selection unit being connected to the test data input signals of the master TAP controller and each slave TAP controller and configured to select the test data signal between the master TAP controller and any slave TAP controller according to a second register in the master TAP controller; a third selection unit connected to the output data signals of the master TAP controller and each TAP controller, and configured to use one of the outputs of the master TAP controller and the plurality of slave TAP controllers as a test data output port of the JTAG according to a third register in the master TAP controller; The master TAP controller and each slave TAP controller include: a test mode selection terminal; The master TAP controller further includes a first chip select port corresponding to each slave TAP controller, and the first selection unit includes a switch corresponding to each slave TAP controller; One end of the switch is connected to the test mode selection port corresponding to the slave TAP controller, and the other end is connected to the first chip selection port corresponding to the slave TAP controller; The master TAP controller further comprises a second chip select port, wherein the second selection unit comprises a first selector corresponding to each slave TAP controller; The output port of each first selector is connected to the test data input port of the corresponding slave TAP controller, the first input port of each first selector is connected to the test data output port of the master TAP controller, the second input end of the first selector corresponding to the first slave TAP controller is connected to the preset reference end, and the second input end of the second first selector corresponding to any two adjacent slave TAP controllers is connected to the test data output port of the slave TAP controller corresponding to the first selector, and the control port of each first selector is connected to the second chip select port; The main TAP controller further includes a third chip select port, and the third selection unit includes a second selector; The second selector has an input port, a control port and an output port corresponding to each slave TAP controller, each input end of the second selector is connected to the test data output port of the corresponding slave TAP controller, and the control port of the second selector is connected to the third chip select port; The device includes a single master TAP controller mode and a master-slave TAP controller mixed mode, wherein the master-slave TAP controller includes a single TAP controller and a single slave TAP controller series mode, a plurality of slave TAP controllers series mode and a plurality of slave TAP controllers parallel mode; Among them, in the single master TAP controller mode, the length of the instruction register and the data control register is the length of the corresponding register in the master TAP controller; in the single TAP controller and single slave TAP controller series mode, the length of the instruction register and the data control register is the sum of the lengths of the corresponding registers in the master TAP and the enabled slave TAP controllers; in the multiple slave TAP controller series mode, the length of the instruction register and the data control register is the sum of the test vectors of the master TAP and all enabled slave TAP controllers; in the multiple slave TAP controller parallel mode, the length of the instruction register and the data control register is the sum of the vector lengths of the master TAP and one slave TAP.
2. The JTAG control device according to claim 1, characterized in that: The master TAP controller and each slave TAP controller include a test clock port, a test reset port, a test data input port and a test data output port; The test clock port of each slave TAP controller is connected to the test clock port of the master TAP controller, and the test reset port of each slave TAP controller is connected to the test reset port of the master TAP controller.
3. The JTAG control device according to claim 2, characterized in that: The test clock port, test reset port, test data input port, and test mode selection port of JTAG correspond to the test clock port, test reset port, test data input port, and test mode selection port of the main TAP controller respectively.
4. The JTAG control device according to claim 1, characterized in that: The switch is an AND gate.
5. The JTAG control device according to claim 1, characterized in that: The preset reference terminal is grounded.
6. The JTAG control device according to claim 1, characterized in that: The first selector is a two-to-one selector.