Chip packaging component and chip function execution method thereof

Abstract

The present application proposes a chip packaging component and a chip function execution method thereof, wherein the chip packaging component comprises a plurality of pins, wherein a pin among the plurality of pins is used to receive a voltage signal. A processing circuit is used to receive the voltage signal, and the processing circuit determines whether the voltage level of the voltage signal is a first level or a second level, so as to generate a first control signal according to the first level, and generate a second control signal according to the second level. A first function circuit among the plurality of function circuits executes a first function according to the first control signal, and a second function circuit among the plurality of function circuits executes a second function according to the second control signal.

Description

Technical Field

[0001] The present application relates to a chip packaging component and a chip function execution method thereof. Background Art

[0002] Process technology is becoming more and more advanced. In order to match the current mainstream small-size electronic products, the chip size is also shrinking. However, people's requirements for the functions of electronic devices are getting higher and higher. Since the functions of the chip must be realized through the output / input signals of the pins, the number of chip pins is particularly important. The more pins, the more functions can be supported.

[0003] For the currently commonly used wafer-level chip packaging or quad flat leadless packaging, the chip must perform a large number of specific functions, and the number of pins required is therefore also huge. If the chip size is reduced by reducing the number of pins in order to match small-sized electronic devices, the functions to be performed must be compromised, resulting in some functions being unable to be performed; if all functions are retained, a lot of cost will be spent on the process, and it cannot be used in small-sized electronic devices. Therefore, finding a way to have the best of both worlds is an important issue today. Summary of the invention

[0004] In some embodiments, a chip package component includes a plurality of pins, wherein a pin among the plurality of pins is used to receive a voltage signal. A processing circuit is used to receive the voltage signal, and the processing circuit determines whether the voltage level of the voltage signal is a first level or a second level, so as to generate a first control signal according to the first level, and generate a second control signal according to the second level. A first functional circuit among the plurality of functional circuits performs a first function according to the first control signal, and a second functional circuit among the plurality of functional circuits performs a second function according to the second control signal.

[0005] In summary, according to one embodiment of the chip packaging component and its chip function execution method of the present application, the chip packaging component receives a voltage signal through a pin within a preset time after power-on, and executes a first function or a second function according to the voltage level of the voltage signal. In addition, after a preset time after power-on, the voltage signal is received through the same pin, and a third function or a fourth function is executed according to the voltage level of the voltage signal. It can be seen that by judging the voltage level switching function and the technology of time-sharing multitasking, the chip packaging component does not need a pin to correspond to only one function. The chip packaging component can support at least four functions based on one pin. The chip packaging component reduces the number of pins while maintaining the function unchanged, thereby achieving multifunctionality and saving process costs due to reducing the chip packaging area. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] [ Figure 1 ] is a schematic diagram of an embodiment of a chip packaging component according to the present application.

[0007] [ Figure 2 ]for Figure 1 A schematic diagram of another embodiment of a chip packaging component.

[0008] [ Figure 3 ] is a flowchart of one embodiment of the chip function execution method according to the present application.

[0009] [ Figure 4 ]for Figure 1 A circuit diagram of one embodiment of the chip package component pins, processing circuit and single-chip system.

[0010] [ Figure 5 ]for Figure 1 A circuit diagram of another embodiment of the chip package component pins, processing circuit and single-chip system.

[0011] [ Figure 6 ]for Figure 1 A circuit diagram of another embodiment of the chip package component pins, processing circuit and single-chip system.

[0012] [ Figure 7 ] is a schematic diagram of another embodiment of the chip packaging component according to the present application. DETAILED DESCRIPTION

[0013] Please refer to Figure 1 , Figure 1 Schematic diagram of an embodiment of a chip package component 1 according to the present application. The chip package component 1 includes a plurality of pins, a plurality of functional circuits and a processing circuit 13. The plurality of pins are arranged around the side of the chip package component 1. The plurality of pins are respectively coupled to the processing circuit 13, and the processing circuit 13 is coupled to the plurality of functional circuits, that is, the processing circuit 13 is coupled between the plurality of pins and the plurality of functional circuits. Figure 1 Example 40 pins and mark pin 11 as an example, in addition, Figure 1 Take four functional circuits 121-124 (hereinafter referred to as the first functional circuit 121, the second functional circuit 122, the third functional circuit 123, and the fourth functional circuit 124 for convenience of description) among the multiple functional circuits as an example. The processing circuit 13 is coupled to the pin 11, and the first functional circuit 121, the second functional circuit 122, the third functional circuit 123, and the fourth functional circuit 124 are respectively coupled to the processing circuit 13, that is, the processing circuit 13 is coupled between the pin 11 and the first functional circuit 121, the second functional circuit 122, the third functional circuit 123, and the fourth functional circuit 124.

[0014] To simplify the description, the following uses pin 11 as an example. Figure 3 , Figure 3This is a flow chart of an embodiment of a chip function execution method according to the present application. The chip package component 1 receives a voltage signal S1 from the outside through the pin 11 (step S01), and transmits the voltage signal S1 to the processing circuit 13 through the pin 11, and the processing circuit 13 receives the voltage signal S1 (step S02). The voltage signal S1 has a voltage level. After receiving the voltage signal S1, the processing circuit 13 determines whether the voltage level of the voltage signal S1 is the first level or the second level (step S03).

[0015] When the processing circuit 13 determines that the voltage level of the voltage signal S1 is the first level, the processing circuit 13 generates a control signal S2 as a first control signal according to the first level (step S04), and the processing circuit 13 transmits the control signal S2 as the first control signal to a first functional circuit 121 among the plurality of functional circuits. After the first functional circuit 121 receives the control signal S2 as the first control signal, the first functional circuit 121 performs a first function according to the first control signal (step S05); on the other hand, when the processing circuit 13 determines that the voltage level of the voltage signal S1 is the second level, the processing circuit 13 generates a control signal S2 as a second control signal according to the second level (step S06), and the processing circuit 13 transmits the control signal S2 as the second control signal to a second functional circuit 122 among the plurality of functional circuits. After the second functional circuit 122 receives the control signal S2 as the second control signal, the second functional circuit 122 performs a second function according to the second control signal (step S07), wherein the second function is different from the first function.

[0016] Based on this, the voltage signal S1 is received through the pin 11 and the processing circuit 13 switches the first function circuit 121 and the second function circuit 122 to perform different functions according to the voltage level of the voltage signal S1, that is, the first function circuit 121 performs the first function or the second function circuit 122 performs the second function. Therefore, one pin of the chip package component 1 not only corresponds to one function, but the chip package component 1 can support multiple different functions according to one pin. The chip package component 1 reduces the number of pins while maintaining the function, thereby achieving multifunctionality and reducing the process cost by reducing the chip package size.

[0017] In some embodiments, Figure 3As shown, the chip package component 1 can perform steps S01-S07 within a preset time after power-on (the judgment result of step S08 is "yes"), that is, the pin 11 can receive the voltage signal S1 within the default time after power-on and transmit it to the processing circuit 13. The processing circuit 13 can also determine whether the voltage level of the voltage signal S1 is the first level or the second level within the default time to generate a control signal S2 that is a first control signal or a second control signal, so that the first function circuit 121 performs the first function according to the first control signal within the default time, or the second function circuit 122 performs the second function according to the second control signal within the default time. The preset time is adjustable.

[0018] Next, please merge the reference Figure 2 , the pin 11 executing step S01 can receive the voltage signal S6 from the outside after a preset time after power-on (step S09), and the pin 11 transmits the voltage signal S6 to the processing circuit 13, and the processing circuit 13 receives the voltage signal S6 after a preset time (step S10). After the processing circuit 13 receives the voltage signal S6, the processing circuit 13 determines whether the voltage level of the voltage signal S6 is the first level or the second level after a preset time (step S11).

[0019] When the processing circuit 13 determines that the voltage level of the voltage signal S6 is the first level, the processing circuit 13 generates a control signal S2 as a third control signal according to the first level (step S12), and the third control signal is different from the first control signal. The processing circuit 13 transmits the control signal S2 as the third control signal to a third functional circuit 123 among the plurality of functional circuits. After the third functional circuit 123 receives the control signal S2 as the third control signal, the third functional circuit 123 performs a third function according to the third control signal (step S13). On the other hand, when the processing circuit 13 determines that the voltage level of the voltage signal S6 is the second level, the processing circuit 13 generates a control signal S2 according to the second level, and the control signal S2 is a fourth control signal different from the second control signal (step S14). The processing circuit 13 transmits the control signal S2 as the fourth control signal to a fourth functional circuit 124 among the plurality of functional circuits. After the fourth functional circuit 124 receives the control signal S2 as the fourth control signal, the fourth functional circuit 124 performs a fourth function according to the fourth control signal (step S15).

[0020] The fourth function is different from the third function, and according to the processing circuit 13 executing steps S01-S07 within the default time or executing steps S01-S15 after the preset time, the third function is different from the first function, and the fourth function is different from the second function. For example, as mentioned above, when the first function and the second function within the corresponding preset time can be functions of controlling volume increase and decrease, respectively, the third function and the fourth function after the default time can be functions of controlling sound effect mute off and mute on, respectively. Based on this, two time intervals are divided by the preset time after power-on. Only by receiving the voltage signals S1 and S6 through a pin 11, the chip packaging component 1 can execute steps S01-S07 within the preset time, and execute steps S09-S15 after the preset time. That is, the chip packaging component 1 can execute the first function, the second function, or both the first function and the second function within the preset time, and the chip packaging component 1 can execute the third function, the fourth function, or both the third function and the fourth function after the preset time. By receiving the voltage signals S1 and S6 respectively in different time intervals through a pin 11, the chip packaging component 1 can execute four different functions in different time intervals.

[0021] In some embodiments, in step S03 and step S11, the processing circuit 13 can adjust the number of determination levels according to the number of multiple functional circuits, and the processing circuit 13 can determine at least two voltage levels. In other words, the processing circuit 13 can determine whether the voltage level of the voltage signals S1 and S6 is the first level, the second level, or other levels different from the aforementioned levels, and can generate another control signal different from the first control signal and the second control signal, or another control signal different from the third control signal and the fourth control signal when the processing circuit 13 determines that the voltage level is other levels. The first functional circuit 121 performs another function different from the first function and the second function according to the another control signal, or performs another function different from the third function and the fourth function.

[0022] In some embodiments, a pull-up / pull-down resistor 2 and a single chip system 3 are respectively coupled to a plurality of pins of the chip package component 1 outside the chip package component 1, that is, a plurality of pins are coupled between the processing circuit 13 and the pull-up / pull-down resistor 2 and the single chip system 3. Figure 1 and Figure 2Taking the pull-up / pull-down resistor 2 and a single-chip system 3 coupled to the pin 11 as an example, when the chip package component 1 is within the preset time after power-on, the pull-up / pull-down resistor 2 transmits a voltage signal S1 to the pin 11 of the chip package component 1, and the voltage signal S1 in step S01 within the preset time comes from the pull-up / pull-down resistor 2. The chip package component 1 executes steps S02-S07 according to the voltage signal S1 transmitted by the pull-up / pull-down resistor 2 received at the pin 11; when the chip package component 1 is after the preset time after power-on, the single-chip system 3 transmits a voltage signal S6 to the pin 11 of the chip package component 1, and the voltage signal S6 in step S09 within the preset time comes from the single-chip system 3. The chip package component 1 executes steps S10-S15 according to the voltage signal S6 transmitted by the single-chip system 3 received at the pin 11.

[0023] In some embodiments, the default time may be the time after the chip package 1 is powered on and before entering the operating system (OS). For example, the first function circuit 121 is used to perform a first function of increasing the system volume, the second function circuit 122 is used to perform a second function of decreasing the system volume, the third function circuit 123 is used to perform a third function of muting the system sound effect, and the fourth function circuit 124 is used to perform a fourth function of muting the system sound effect. When the pin 11 of the chip package 1 receives the voltage signal S1 transmitted from the pull-up / pull-down resistor 2 in step S01 before entering the operating system, the processing circuit 13 determines that the voltage level of the voltage signal S1 is the first level, that is, in steps S04-S05, the processing circuit 13 generates a first control signal, and the first function circuit 121 for controlling the system volume enhancement receives the first control signal and performs the first function of enhancing the system volume according to the first control signal. Therefore, the chip package 1 has completed the setting of the system volume enhancement before entering the operating system.

[0024] Furthermore, after the system of the chip package component 1 enters the operating system, in step S09, the voltage signal S6 transmitted from the single chip system 3 is received. When the processing circuit 13 determines that the voltage level of the voltage signal S6 is the second level, that is, in steps S06-S07, the processing circuit 13 generates a fourth control signal, and the fourth function circuit 124 for controlling the system sound effect to start muting receives the fourth control signal and executes the fourth function of muting the system sound effect according to the fourth control signal. Therefore, after entering the operating system, the chip package component 1 switches the previously volume-enhanced setting to the setting of muting the system sound effect. In some embodiments, the preset time may be 1 millisecond (ms).

[0025] In some embodiments, the processing circuit 13 includes a plurality of comparators and a processor 134. Figure 4 , Figure 5 and Figure 6 The circuit diagram of the three embodiments, the pin 11 is coupled between the processing circuit 13 and the single chip system 3, the single chip system 3 includes a voltage source VDD and a plurality of transistors connected in parallel, the processing circuit 13 includes a plurality of comparators and a processor 134 connected in parallel, and Figure 4 , Figure 5 and Figure 6 The difference between Figure 4 The processing circuit 13 further includes a variable resistor coupled between the pin 11 and a plurality of comparators. Figure 6 The single chip system 3 further includes a resistor coupled between the plurality of transistors and the plurality of pins 11 .

[0026] Figure 4 , Figure 5 and Figure 6 Taking three transistors M1, M2, M3 and three comparators 131, 132, 133 and a voltage signal S1 as an example, the transistors M1, M2, M3 are coupled between the voltage source VDD and the pin 11, and the comparators 131, 132, 133 are coupled between the pin 11 and the processor 134. In detail, the transistors M1, M2, M3 can be used as a switch that is turned on or off, and the single chip system 3 can combine a variety of different voltage levels according to the operating states (on and off) of the voltage source VDD and the multiple transistors to generate the voltage signal S1 having the voltage level.

[0027] Furthermore, the comparators 131, 132, 133 in the processing circuit 13 can receive preset levels ref1, ref2, ref3 respectively, wherein the preset levels ref1, ref2, ref3 are adjustable. In step S11, the comparator 131 compares the voltage level of the voltage signal S1 with the default level ref1, and outputs the comparison result S3 to the processor 134 when the voltage level is greater than the default level ref1, and does not perform the output when the voltage level is less than the default level ref1; the comparator 132 compares the voltage level of the voltage signal S1 with the default level ref2, and outputs the comparison result S4 to the processor 134 when the voltage level is greater than the default level ref2, and does not perform the output when it is less than the preset level ref2; and the comparator 133 compares the voltage level of the voltage signal S1 with the default level ref3, and outputs the comparison result S5 to the processor 134 when the voltage level is greater than the default level ref3, and does not perform the output when it is less than the preset level ref3. Therefore, the processor 134 can determine whether the voltage level of the voltage signal S1 is the first level, the second level, or other levels according to the comparison results S3, S4, and S5. When the determination result is the first level, the processor 134 proceeds to step S12; when the determination result is the second level, the processor 134 proceeds to step S14.

[0028] For example, the preset level ref1 may be 1 volt (V), the preset level ref2 may be 2V, the preset level ref3 may be 3V, and the comparison results S3, S4, and S5 may all be 1, wherein when the processor 134 receives the comparison result S3, it determines that the voltage level is the first level, when the processor 134 receives the comparison result S4, it determines that the voltage level is the second level, and when the processor 134 receives the comparison result S5, it determines that the voltage level is another level. When the single-chip system 3 generates a voltage signal S1 with a voltage level of 2.5V according to the voltage source VDD and the transistors M1, M2, and M3 are turned on or off respectively, the single-chip system 3 transmits the voltage signal S1 with a voltage level of 2.5V to the processing circuit 13 via the pin 11. When the comparator 131 determines that the voltage level of 2.5V is greater than the preset level ref1 of 1V, the comparison result S3 of "1" is output to the processor 134; further, when the comparator 132 determines that the voltage level of 2.5V is greater than the preset level ref2 of 2V, the comparator 132 outputs the comparison result S4 of "1" to the processor 134; in addition, when the comparator 133 determines that the voltage level of 2.5V of the voltage signal S1 is less than the preset level ref3 of 3V, the comparator 132 does not output the comparison result S5 to the processor 134, and the processor 134 can determine that the voltage level of the voltage signal S1 is the second level based on the received comparison result S4 of 1.

[0029] In some embodiments, Figure 1 As shown, the chip package component 1 can be a quad flat no-lead package (QuadFlat No-lead; QFN). In addition, please refer to Figure 7 The chip package component 1 may also be another packaging form, that is, a wafer level chip package (Wafer Level Chip Scale Package; WLCSP). Regardless of the packaging form of the chip package component 1, the number of required pins can be reduced according to one embodiment of the present application. Figure 7 For example, when the chip package component 1 is provided with 25 pins, including pin 11 and pins 12-19, 10, the chip package component 1 must be provided using a 180nm process; when the chip package component 1 needs to reduce the process to 110nm to reduce costs but must retain all the original functions at the same time, the chip package component 1 enables one pin to support multiple functions according to one embodiment described in the present application, so that the number of pins can be reduced while maintaining the functions unchanged, for example, only 20 pins are needed, that is, the chip package component 1 can remove pins 12, 14-19, 10, 20 to save the process cost of the chip package component 1.

[0030] In summary, according to one embodiment of the chip packaging component and its chip function execution method of the present application, the chip packaging component receives a voltage signal through a pin within a preset time after power-on, and executes a first function or a second function according to the voltage level of the voltage signal. In addition, after a preset time after power-on, the voltage signal is received through the same pin, and a third function or a fourth function is executed according to the voltage level of the voltage signal. It can be seen that by judging the voltage level switching function and the technology of time-sharing multitasking, the chip packaging component does not need a pin to correspond to only one function. The chip packaging component can support at least four functions based on one pin. The chip packaging component reduces the number of pins while maintaining the function unchanged, thereby achieving multifunctionality and saving process costs due to reducing the chip packaging area.

[0031] Although the present application has been disclosed as above with the embodiments, it is not intended to limit the present application. Any ordinary technician in the technical field can make some changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope of the attached claims.

[0032]

Explanation of symbols

[0033] 1: Chip packaging components

[0034] 11: Pin

[0035] 12: Pin

[0036] 14: Pin

[0037] 15: Pin

[0038] 16: Pin

[0039] 17: Pin

[0040] 18: Pin

[0041] 19: Pin

[0042] 10: Pin

[0043] 20: Pin

[0044] 121: First functional circuit

[0045] 122: Second functional circuit

[0046] 123: The third functional circuit

[0047] 124: Fourth functional circuit

[0048] 13: Processing circuit

[0049] 131: Comparator

[0050] 132: Comparator

[0051] 133: Comparator

[0052] 134: Processor

[0053] 2: Pull-up / pull-down resistor

[0054] 3: Single chip system

[0055] S1: voltage signal

[0056] S2: Control signal

[0057] S3: Comparison results

[0058] S4: Comparison results

[0059] S5: Comparison results

[0060] S6: Voltage signal

[0061] M1: Transistor

[0062] M2: Transistor

[0063] M3: Transistor

[0064] ref1: preset level

[0065] ref2: preset level

[0066] ref3: preset level

[0067] S01~S15: steps.

Claims

1. A chip packaging component, comprising: A plurality of pins, one of the plurality of pins is used to receive a voltage signal; a processing circuit coupled between the plurality of pins and the plurality of functional circuits, for receiving the voltage signal, the processing circuit determining whether a voltage level of the voltage signal is a first level or a second level, generating a first control signal according to the first level, and generating a second control signal according to the second level; and a plurality of functional circuits, wherein a first functional circuit among the plurality of functional circuits performs a first function according to the first control signal, and a second functional circuit among the plurality of functional circuits performs a second function according to the second control signal, and in, The chip package component receives a voltage signal through a pin within a preset time after power-on, and performs a first function or a second function according to the voltage level of the voltage signal. In addition, the chip package component receives a voltage signal through the same pin after a preset time after power-on, and performs a third function or a fourth function according to the voltage level of the voltage signal. Wherein, if the processing circuit determines that the voltage level is the first level within a preset time after power-on, the first control signal is generated; if the processing circuit determines that the voltage level is the first level after the preset time, a third control signal is generated to control a third functional circuit among the multiple functional circuits to perform a third function according to the third control signal.

2. The chip package component according to claim 1, wherein: The processing circuit generates the second control signal when it is determined that the voltage level is the second level within the preset time, and generates a fourth control signal when it is determined that the voltage level is the second level after the preset time, so as to control a fourth functional circuit among the multiple functional circuits to perform a fourth function according to the fourth control signal.

3. The chip package component according to claim 1, wherein: The voltage signal comes from a pull-up / pull-down resistor within the preset time and the voltage signal comes from a single chip system after the preset time.

4. The chip package component according to claim 1, wherein: The processing circuit includes a comparator and a processor. The comparator compares the voltage level with a default level to generate a comparison result. The processor determines whether the voltage level is the first level or the second level according to the comparison result.

5. A chip function execution method suitable for a chip packaging component, comprising: A pin of the chip package component receives a voltage signal; A processing circuit of the chip package component determines that a voltage level of the voltage signal is a first level or a second level; When the voltage level is the first level, the processing circuit generates a first control signal according to the first level; When the voltage level is the second level, the processing circuit generates a second control signal according to the second level; A first functional circuit of the chip package component performs a first function according to the first control signal; and A second functional circuit of the chip package component performs a second function according to the second control signal, and in, The chip package component receives a voltage signal through a pin within a preset time after power-on, and performs a first function or a second function according to the voltage level of the voltage signal. In addition, the chip package component receives a voltage signal through the same pin after a preset time after power-on, and performs a third function or a fourth function according to the voltage level of the voltage signal. Wherein, in the step of determining the voltage level of the voltage signal, the processing circuit determines that the voltage level is the first level within a preset time after power-on; the chip function execution method further includes: After the preset time, the pin of the chip package component receives another voltage signal; The processing circuit determines whether a voltage level of the other voltage signal is the first level or the second level; When the voltage level of the other voltage signal is the first level, the processing circuit generates a third control signal according to the first level; and A third functional circuit of the chip package component performs a third function according to the third control signal.

6. The chip function execution method according to claim 5, wherein: In the step of determining the voltage level of the voltage signal, the processing circuit determines that the voltage level is the second level within the preset time after power-on; the chip function execution method further includes: After the preset time, when the processing circuit determines that the voltage level of the other voltage signal is the second level, the processing circuit generates a fourth control signal according to the second level; and A fourth functional circuit of the chip package component performs a fourth function according to the fourth control signal.

7. The chip function execution method according to claim 5, wherein: The voltage signal comes from a pull-up / pull-down resistor within the preset time and the other voltage signal comes from a single chip system after the preset time.

8. The chip function execution method according to claim 5, wherein: In the step of determining the voltage level of the voltage signal, a comparator of the processing circuit compares the voltage level with a default level to generate a comparison result, and a processor of the processing circuit determines whether the voltage level is the first level or the second level according to the comparison result.

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