Power-on reset circuit and method for improving output stability thereof

Abstract

The present invention provides a power-on reset circuit and a method for improving output stability thereof. The power-on reset circuit comprises a charging module, a charging and discharging capacitor, a Schmitt trigger and a delay shaping module, and the charging module comprises a current generating unit and a shunt mirror unit. The current generating unit generates and outputs a first current, and the shunt mirror unit receives the first current and shunts the first current to obtain a second current and outputs it in a mirror image. The second current is then used to charge and transform the charging and discharging capacitor, trigger shaping, and then output a reset signal. The second current is shunted on the basis of the first current. Compared with the first current, the second current is affected by temperature and voltage fluctuations and is weakened. The temperature stability and voltage stability of the second current are higher, thereby improving the temperature stability and voltage stability of a subsequent reset signal based on the second current. The corresponding reset time is less affected by temperature and voltage, and the normal operation of the circuit or other devices is effectively guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a power-on reset circuit and a method for improving output stability thereof. Background Art

[0002] Power-on reset (POR) circuits are widely used in analog, digital and radio frequency chips. Their function is to ensure that after power is applied, each part of the circuit is initialized to a known state to ensure that the chip can work normally. The traditional power-on reset circuit consists of three parts: a charging circuit composed of MOS tubes, a charging and discharging capacitor, and a Schmitt trigger. Its reset time is greatly affected by temperature and voltage, which makes it impossible for the host computer that controls the chip to control the chip at a precise time point, and cannot meet the application scenarios of the whole machine that have requirements for the power-on reset time point.

[0003] Therefore, it is very necessary to design a power-on reset circuit whose reset time is less affected by temperature and voltage. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a power-on reset circuit technical solution for solving the technical problem that the reset time of the traditional power-on reset circuit is greatly affected by temperature and voltage, so as to improve the stability of the circuit startup operation.

[0005] To achieve the above-mentioned purpose and other related purposes, the technical solution provided by the present invention is as follows.

[0006] A power-on reset circuit, comprising:

[0007] A charging module, comprising a current generating unit and a shunt mirror unit, wherein the current generating unit generates and outputs a first current, and the shunt mirror unit receives the first current and shunts the first current to obtain a second current and outputs the second current in a mirrored manner;

[0008] A charging and discharging capacitor, connected to the charging module, storing energy and charging under the action of the second current;

[0009] A Schmitt trigger is connected to the charging and discharging capacitor and outputs a trigger signal according to the energy storage voltage on the charging and discharging capacitor;

[0010] The delay shaping module receives the trigger signal, performs delay shaping on the trigger signal, and then outputs a reset signal.

[0011] Optionally, the second current is smaller than the first current, the temperature stability of the second current is higher than the temperature stability of the first current, and the voltage stability of the second current is higher than the voltage stability of the first current.

[0012] Optionally, the current generating unit includes a first resistor, a first NMOS tube, a second NMOS tube and a third NMOS tube, the drain of the first NMOS tube is connected to the power supply voltage after being connected in series with the first resistor, the gate of the first NMOS tube is connected to the drain of the first NMOS tube, the drain of the second NMOS tube is connected to the source of the first NMOS tube, the gate of the second NMOS tube is connected to the drain of the second NMOS tube, the source of the second NMOS tube is grounded, the source of the third NMOS is grounded, the gate of the third NMOS tube is connected to the gate of the second NMOS tube, and the drain of the third NMOS tube outputs the first current.

[0013] Optionally, the shunt mirror unit includes a first PMOS tube, a second PMOS tube and a third PMOS tube, the source of the first PMOS tube is connected to the power supply voltage, the gate of the first PMOS tube is connected to the drain of the first PMOS tube, the drain of the first PMOS tube is connected to the drain of the third NMOS tube, the source of the second PMOS tube is connected to the power supply voltage, the gate of the second PMOS tube is connected to the drain of the second PMOS tube, the drain of the second PMOS tube is connected to the drain of the third NMOS tube, the source of the third PMOS tube is connected to the power supply voltage, the gate of the third PMOS tube is connected to the gate of the second PMOS tube, and the drain of the third PMOS tube outputs the second current.

[0014] Optionally, the width-to-length ratio of the first PMOS tube is greater than that of the second PMOS tube, the width-to-length ratio of the second PMOS tube is equal to that of the third PMOS tube, and the width-to-length ratio of the second NMOS tube is equal to that of the third NMOS tube.

[0015] Optionally, one end of the charging and discharging capacitor is connected to the drain of the third PMOS tube, and the other end of the charging and discharging capacitor is grounded.

[0016] Optionally, the Schmitt trigger includes a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, the source of the fourth PMOS tube is connected to the power supply voltage, the gate of the fourth PMOS tube is connected to the non-grounded end of the charging and discharging capacitor, the drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube, the gate of the fifth PMOS tube is connected to the gate of the fourth PMOS tube, the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the gate of the fourth PMOS tube, and the fourth NMOS tube is connected to the gate of the fourth PMOS tube. The source of the S tube is connected to the drain of the fifth NMOS tube, the gate of the fifth NMOS tube is connected to the gate of the fourth NMOS tube, the source of the fifth NMOS tube is grounded, the source of the sixth PMOS tube is connected to the source of the fifth PMOS tube, the gate of the sixth PMOS tube is connected to the drain of the fifth PMOS tube, the drain of the sixth PMOS tube is grounded, the source of the sixth NMOS tube is connected to the source of the fourth NMOS tube, the gate of the sixth NMOS tube is connected to the drain of the fourth NMOS tube, the drain of the sixth NMOS tube is connected to the power supply voltage, and the drain of the fourth NMOS tube outputs the trigger signal.

[0017] Optionally, the delay shaping module includes a seventh PMOS tube, a first inverter, a second inverter and an XOR gate, the source of the seventh PMOS tube is connected to the power supply voltage, the gate of the seventh PMOS tube is grounded, the drain of the seventh PMOS tube is connected to the first input of the XOR gate, the input of the first inverter receives the drain of the fourth NMOS tube, the output of the first inverter is connected to the second input of the XOR gate, the output of the XOR gate is connected to the input of the second inverter, and the output of the second inverter outputs the reset signal.

[0018] A method for improving output stability of a power-on reset circuit, comprising:

[0019] providing a first current;

[0020] Dividing the first current to obtain a second current, so that the temperature stability and voltage stability of the second current are higher than those of the first current;

[0021] charging the charging and discharging capacitor using the second current;

[0022] A reset signal is output according to the energy storage voltage on the charging and discharging capacitor.

[0023] Optionally, the step of shunting the first current to obtain the second current includes:

[0024] mirroring the first current to output;

[0025] Two MOS tubes are connected in series at the mirror output end of the first current, and the two MOS tubes are arranged in parallel;

[0026] A current flowing through the MOS tube is mirrored and outputted to obtain the second current.

[0027] As described above, the power-on reset circuit and the method for improving output stability thereof of the present invention have at least the following beneficial effects:

[0028] The charging module of the power-on reset circuit includes a current generating unit and a shunt mirror unit. The current generating unit generates and outputs a first current. The shunt mirror unit receives the first current and shunts the first current to obtain a second current and outputs it in a mirror image. The second current is then used to charge and transform the charging and discharging capacitors, trigger shaping, and then output a final reset signal. The second current is obtained by shunting the first current. Compared with the first current, the second current is affected by temperature and voltage fluctuations and is weakened. The temperature stability and voltage stability of the second current are higher, thereby improving the temperature stability and voltage stability of the subsequent reset signal obtained based on the second current. The reset operation using the reset signal is more stable, and the corresponding reset time is less affected by temperature and voltage, which effectively ensures the normal operation of the circuit or other devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Shown is a circuit diagram of a power-on reset circuit in the present invention.

[0030] Figure 2 It shows the simulation test curve of the reset time of the power-on reset circuit in the present invention changing with temperature.

[0031] Figure 3 The simulation test curve showing the reset time of the traditional power-on reset circuit varies with temperature.

[0032] Figure 4 It shows the simulation test curve of the reset time of the power-on reset circuit in the present invention changing with the power supply voltage.

[0033] Figure 5 The simulation test curve showing the reset time of the traditional power-on reset circuit varies with the power supply voltage.

[0034] Description of Reference Numerals

[0035] R1—first resistor, N1—first NMOS tube, N2—second NMOS tube, N3—third NMOS tube, N4—fourth NMOS tube, N5—fifth NMOS tube, N6—sixth NMOS tube, P1—first PMOS tube, P2—second PMOS tube, P3—third PMOS tube, P4—fourth PMOS tube, P5—fifth PMOS tube, P6—sixth PMOS tube, P7—seventh PMOS tube, C1—charging and discharging capacitor, IV1—first inverter, IV2—second inverter, XOR—exclusive OR gate, I1—first current, I2—second current, VCC—power supply voltage, VSS—ground, V1—trigger signal, V2—reset signal. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] See also Figures 1 to 5 . It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complicated. The structure, proportion, size, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, it has no technical substantive significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effect and purpose that can be achieved by the present invention.

[0038] like Figure 1 As shown, the present invention provides a power-on reset circuit, which includes:

[0039] A charging module, comprising a current generating unit and a shunt mirror unit, wherein the current generating unit generates and outputs a first current I1, and the shunt mirror unit receives the first current I1 and shunts the first current I1 to obtain a second current I2 and outputs the second current I2 in a mirrored manner;

[0040] The charging and discharging capacitor C1 is connected to the charging module and is charged and stored under the action of the second current I2;

[0041] The Schmitt trigger is connected to the charging and discharging capacitor C1 and outputs a trigger signal V1 according to the energy storage voltage on the charging and discharging capacitor C1;

[0042] The delay shaping module contacts the trigger signal V1, performs delay shaping on the trigger signal V1, and then outputs a reset signal V2.

[0043] The second current I2 is smaller than the first current I1 , the temperature stability of the second current I2 is higher than the temperature stability of the first current I1 , and the voltage stability of the second current I2 is higher than the voltage stability of the first current I1 .

[0044] In detail, Figure 1 As shown, the current generating unit includes a first resistor R1, a first NMOS transistor N1, a second NMOS transistor N2 and a third NMOS transistor N3. The drain of the first NMOS transistor N1 is connected to the power supply voltage VCC via the first resistor R1 connected in series, the gate of the first NMOS transistor N1 is connected to the drain of the first NMOS transistor N1, the drain of the second NMOS transistor N2 is connected to the source of the first NMOS transistor N1, the gate of the second NMOS transistor N2 is connected to the drain of the second NMOS transistor N2, the source of the second NMOS transistor N2 is grounded VSS, the source of the third NMOS transistor N3 is grounded, the gate of the third NMOS transistor N3 is connected to the gate of the second NMOS transistor N2, and the drain of the third NMOS transistor N3 outputs the first current I1.

[0045] In detail, Figure 1 As shown, the current shunt mirror unit includes a first PMOS tube P1, a second PMOS tube P2 and a third PMOS tube P3, the source of the first PMOS tube P1 is connected to the power supply voltage VCC, the gate of the first PMOS tube P1 is connected to the drain of the first PMOS tube P1, the drain of the first PMOS tube P1 is connected to the drain of the third NMOS tube N3, the source of the second PMOS tube P2 is connected to the power supply voltage VCC, the gate of the second PMOS tube P2 is connected to the drain of the second PMOS tube P2, the drain of the second PMOS tube P2 is connected to the drain of the third NMOS tube N3, the source of the third PMOS tube P3 is connected to the power supply voltage VCC, the gate of the third PMOS tube P3 is connected to the gate of the second PMOS tube P2, and the drain of the third PMOS tube P3 outputs the second current I2.

[0046] The width-to-length ratio of the first PMOS tube P1 is greater than that of the second PMOS tube P2, the width-to-length ratio of the second PMOS tube P2 is equal to that of the third PMOS tube P3, and the width-to-length ratio of the second NMOS tube N2 is equal to that of the third NMOS tube N3.

[0047] In an optional embodiment of the present invention, the size of the first PMOS tube P1 is selected as W / L=2μm / 1μm, the size of the second PMOS tube P2 is selected as W / L=500nm / 50μm, the size of the third PMOS tube P3 is selected as W / L=500nm / 50μm, and the sizes of the first NMOS tube N1, the second NMOS tube N2 and the third NMOS tube N3 are all selected as W / L=400nm / 40μm.

[0048] In detail, Figure 1 As shown, one end of the charge-discharge capacitor C1 is connected to the drain of the third PMOS transistor P3, and the other end of the charge-discharge capacitor C1 is grounded to VSS.

[0049] In detail, Figure 1 As shown, the Schmitt trigger includes a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a fourth NMOS tube N4, a fifth NMOS tube N5 and a sixth NMOS tube N6, the source of the fourth PMOS tube P4 is connected to the power supply voltage VCC, the gate of the fourth PMOS tube P4 is connected to the non-grounded end of the charge and discharge capacitor C1, the drain of the fourth PMOS tube P4 is connected to the source of the fifth PMOS tube P5, the gate of the fifth PMOS tube P5 is connected to the gate of the fourth PMOS tube P4, the drain of the fifth PMOS tube P5 is connected to the drain of the fourth NMOS tube N4, the gate of the fourth NMOS tube N4 is connected to the gate of the fourth PMOS tube P4, and the fourth NMOS The source of the transistor N4 is connected to the drain of the fifth NMOS transistor N5, the gate of the fifth NMOS transistor N5 is connected to the gate of the fourth NMOS transistor N4, the source of the fifth NMOS transistor N5 is grounded to VSS, the source of the sixth PMOS transistor P6 is connected to the source of the fifth PMOS transistor P5, the gate of the sixth PMOS transistor P6 is connected to the drain of the fifth PMOS transistor P5, the drain of the sixth PMOS tube P6 is grounded to VSS, the source of the sixth NMOS transistor N6 is connected to the source of the fourth NMOS transistor N4, the gate of the sixth NMOS tube N6 is connected to the drain of the fourth NMOS tube N4, the drain of the sixth NMOS tube N6 is connected to the power supply voltage VCC, and the drain of the fourth NMOS tube N4 outputs the trigger signal V1.

[0050] In detail, Figure 1 As shown, the delay shaping module includes a seventh PMOS tube P7, a first inverter IV1, a second inverter IV2 and an XOR gate XOR, the source of the seventh PMOS tube P7 is connected to the power supply voltage VCC, the gate of the seventh PMOS tube P7 is grounded VSS, the drain of the seventh PMOS tube P7 is connected to the first input end of the XOR gate XOR, the input end of the first inverter IV1 receives the drain of the fourth NMOS tube N4, the output end of the first inverter IV1 is connected to the second input end of the XOR gate XOR, the output end of the XOR gate XOR is connected to the input end of the second inverter IV2, and the output end of the second inverter IV2 outputs a reset signal V2.

[0051] In more detail, Figure 1 As shown, in the current generating unit of the charging module, the first current I1 flowing through the first resistor R1, the first NMOS tube N1 and the second NMOS tube N2 branch is mirrored to the third NMOS tube N3 by the current mirror formed by the second NMOS tube N2 and the third NMOS tube N3, the first PMOS tube P1 and the second PMOS tube P2 are connected to the drain of the third NMOS tube N3 after being arranged in parallel, and the first current I1 flowing through the third NMOS tube N3 is mirrored by the first PMOS tube P1 and the second PMOS tube P2. The first PMOS tube P1 has a width-to-length ratio greater than that of the second PMOS tube P2, and the current flowing through the first PMOS tube P1 is greater than the current flowing through the second PMOS tube P2. The current flowing through the second PMOS tube P2 is the second current I2. The second current I2 is mirrored to the third PMOS tube P3 by a current mirror formed by the second PMOS tube P2 and the third PMOS tube P3. The second current I2 outputted from the drain of the third PMOS tube P3 charges the charge-discharge capacitor C1.

[0052] Among them, the second current I2 is obtained by shunting the first current I1. Since the width-to-length ratio of the first PMOS tube P1 is greater than (or much greater than) the width-to-length ratio of the second PMOS tube P2, the current flowing through the first PMOS tube P1 is greater than (or much greater than) the current flowing through the second PMOS tube P2, thereby making the first current I1 greater than (or much greater than) the second current I2. Compared with the first current I1, the second current I2 is affected by the fluctuation of temperature and voltage and is shared and weakened. The temperature stability and voltage stability of the second current I2 are higher, thereby improving the temperature stability and voltage stability of the reset signal V2 subsequently obtained based on the second current I2. The reset operation using the reset signal V2 is more stable, and the corresponding reset time is less affected by temperature and voltage, which effectively ensures the normal operation of the circuit or other devices.

[0053] For example Figure 1 The power-on reset circuit shown in the figure is subjected to a temperature simulation experiment, and the simulation test curve of its reset time changing with temperature is obtained as shown in the figure below: Figure 2 As shown by Figure 2 It can be seen that the change of reset time with temperature is controlled within 33.63%; Figure 3 As shown in FIG. 1 , a simulation experiment is performed on a traditional power-on reset circuit, and the obtained simulation test curve of the reset time varying with temperature is obtained. Figure 3 It can be seen that the reset time of the traditional power-on reset circuit varies with temperature by as much as 140.59%. Figure 3 and Figure 2It can be seen that the power-on reset circuit provided by the present invention has good temperature stability.

[0054] For example Figure 1 The power-on reset circuit shown in the figure is subjected to voltage simulation experiment, and the simulation test curve of its reset time changing with power supply voltage is obtained as shown in the figure below: Figure 4 As shown by Figure 4 It can be seen that the reset time is controlled within 12.17% with the change of power supply voltage; Figure 5 As shown in FIG. 1 , a simulation experiment is performed on a traditional power-on reset circuit, and the obtained simulation test curve of the reset time varying with the power supply voltage is obtained. Figure 5 It can be seen that the reset time of the traditional power-on reset circuit varies with the power supply voltage by as much as 122.22%. Figure 5 and Figure 4 It can be seen that the power-on reset circuit provided by the present invention has good voltage stability.

[0055] The above simulation experiment results show that the reset time of the power-on reset circuit provided by the present invention is less affected by temperature and voltage, and can be applied to circuit systems that require integration.

[0056] In addition, based on the design concept of the above power-on reset circuit, the present invention also provides a method for improving the output stability of the power-on reset circuit, which includes the steps of:

[0057] S1, providing a first current;

[0058] S2. Dividing the first current to obtain a second current, so that the temperature stability and voltage stability of the second current are higher than those of the first current;

[0059] S3, charging the charging and discharging capacitor using the second current;

[0060] S4. Output a reset signal according to the energy storage voltage on the charging and discharging capacitor.

[0061] In detail, the step S2 of dividing the first current to obtain the second current further includes:

[0062] S21, mirroring the first current and outputting it;

[0063] S22, connecting two MOS tubes in series at the mirror output end of the first current, and the two MOS tubes are arranged in parallel;

[0064] S23, mirroring the current flowing through a MOS tube to obtain a second current.

[0065] In step S22, the width-to-length ratio of the two MOS tubes can be flexibly adjusted according to actual needs, the relative magnitudes of the first current I1 and the second current I2 can be adjusted, and the temperature stability and voltage stability of the second current I2 can be adjusted, which is not limited here.

[0066] To sum up, in the power-on reset circuit and the method for improving its output stability provided by the present invention, the charging module of the power-on reset circuit includes a current generating unit and a shunt mirror unit. The current generating unit generates and outputs a first current. The shunt mirror unit receives the first current and shunts the first current to obtain a second current and outputs it in a mirror image. The second current is then used to charge and transform the charging and discharging capacitors, trigger shaping, and then output a final reset signal. The second current is shunted on the basis of the first current. Compared with the first current, the second current is affected by temperature and voltage fluctuations and is weakened. The temperature stability and voltage stability of the second current are higher, thereby improving the temperature stability and voltage stability of the reset signal subsequently obtained based on the second current. The reset operation using the reset signal is more stable, and the corresponding reset time is less affected by temperature and voltage, effectively ensuring the normal operation of the circuit or other devices.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A power-on reset circuit, characterized in that: include: A charging module, comprising a current generating unit and a shunt mirror unit, wherein the current generating unit generates and outputs a first current, and the shunt mirror unit receives the first current and shunts the first current to obtain a second current and outputs the second current in a mirror image; the current generating unit comprises a first resistor, a first NMOS tube, a second NMOS tube and a third NMOS tube, wherein the drain of the first NMOS tube is connected to a power supply voltage after being connected in series with the first resistor, the gate of the first NMOS tube is connected to the drain of the first NMOS tube, the drain of the second NMOS tube is connected to the source of the first NMOS tube, the gate of the second NMOS tube is connected to the drain of the second NMOS tube, the source of the second NMOS tube is grounded, the source of the third NMOS tube is grounded, and the gate of the third NMOS tube is connected to the second NMOS tube. The gate of the MOS tube, the drain of the third NMOS tube outputs the first current; the shunt mirror unit includes a first PMOS tube, a second PMOS tube and a third PMOS tube, the source of the first PMOS tube is connected to the power supply voltage, the gate of the first PMOS tube is connected to the drain of the first PMOS tube, the drain of the first PMOS tube is connected to the drain of the third NMOS tube, the source of the second PMOS tube is connected to the power supply voltage, the gate of the second PMOS tube is connected to the drain of the second PMOS tube, the drain of the second PMOS tube is connected to the drain of the third NMOS tube, the source of the third PMOS tube is connected to the power supply voltage, the gate of the third PMOS tube is connected to the gate of the second PMOS tube, and the drain of the third PMOS tube outputs the second current; A charging and discharging capacitor, connected to the charging module, storing energy and charging under the action of the second current; A Schmitt trigger is connected to the charging and discharging capacitor and outputs a trigger signal according to the energy storage voltage on the charging and discharging capacitor; The delay shaping module receives the trigger signal, performs delay shaping on the trigger signal, and then outputs a reset signal.

2. The power-on reset circuit according to claim 1, characterized in that: The second current is smaller than the first current, the temperature stability of the second current is higher than the temperature stability of the first current, and the voltage stability of the second current is higher than the voltage stability of the first current.

3. The power-on reset circuit according to claim 1, characterized in that: The width-to-length ratio of the first PMOS tube is greater than that of the second PMOS tube, the width-to-length ratio of the second PMOS tube is equal to that of the third PMOS tube, and the width-to-length ratio of the second NMOS tube is equal to that of the third NMOS tube.

4. The power-on reset circuit according to claim 1 or 3, characterized in that: One end of the charging and discharging capacitor is connected to the drain of the third PMOS tube, and the other end of the charging and discharging capacitor is grounded.

5. The power-on reset circuit according to claim 4, characterized in that: The Schmitt trigger includes a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, the source of the fourth PMOS tube is connected to the power supply voltage, the gate of the fourth PMOS tube is connected to the non-grounded end of the charging and discharging capacitor, the drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube, the gate of the fifth PMOS tube is connected to the gate of the fourth PMOS tube, the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the gate of the fourth PMOS tube, and the fourth NMOS tube The source of the fifth NMOS tube is connected to the drain of the fifth NMOS tube, the gate of the fifth NMOS tube is connected to the gate of the fourth NMOS tube, the source of the fifth NMOS tube is grounded, the source of the sixth PMOS tube is connected to the source of the fifth PMOS tube, the gate of the sixth PMOS tube is connected to the drain of the fifth PMOS tube, the drain of the sixth PMOS tube is grounded, the source of the sixth NMOS tube is connected to the source of the fourth NMOS tube, the gate of the sixth NMOS tube is connected to the drain of the fourth NMOS tube, the drain of the sixth NMOS tube is connected to the power supply voltage, and the drain of the fourth NMOS tube outputs the trigger signal.

6. The power-on reset circuit according to claim 5, characterized in that: The delay shaping module includes a seventh PMOS tube, a first inverter, a second inverter and an XOR gate, the source of the seventh PMOS tube is connected to the power supply voltage, the gate of the seventh PMOS tube is grounded, the drain of the seventh PMOS tube is connected to the first input end of the XOR gate, the input end of the first inverter receives the drain of the fourth NMOS tube, the output end of the first inverter is connected to the second input end of the XOR gate, the output end of the XOR gate is connected to the input end of the second inverter, and the output end of the second inverter outputs the reset signal.

7. A method for improving the output stability of the power-on reset circuit according to any one of claims 1 to 6, characterized in that: include: providing a first current; Dividing the first current to obtain a second current, so that the temperature stability and voltage stability of the second current are higher than those of the first current; The step of shunting the first current to obtain the second current includes: mirroring the first current and outputting it; connecting a first PMOS tube and a second PMOS tube in series at the mirror output end of the first current, wherein the first PMOS tube and the second PMOS tube are arranged in parallel, and the width-to-length ratio of the first PMOS tube is greater than the width-to-length ratio of the second PMOS tube; mirroring the current flowing through the second PMOS tube and outputting it to obtain the second current; charging the charging and discharging capacitor using the second current; A reset signal is output according to the energy storage voltage on the charging and discharging capacitor.

Images