Polar code decoding method, device, storage medium and processor

Abstract

This application provides a polar code decoding method, apparatus, storage medium, and processor. The method includes: dividing the nodes on the SSC decoding tree into Rate-0 nodes, Rate-1 nodes, SPC nodes, and REP nodes; processing the Rate-0 nodes, Rate-1 nodes, SPC nodes, and REP nodes respectively using the SCL algorithm to obtain the optimal decoding path; and decoding the polar code using the optimal decoding path. A classification processing approach is adopted, replacing bit-level computation with node-level computation, improving decoding parallelism. Furthermore, this paper optimizes the sorting algorithm, shortening the critical path of the sorting module in the SCL algorithm, thus improving decoding speed while maintaining decoding accuracy.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to a polar code decoding method, device, storage medium and processor. Background Art

[0002] The Polar code proposed by Professor Arikan is derived from the channel polarization phenomenon. In his paper, he introduced in detail the coding scheme applied to the binary-input discrete memoryless channel (B-DMC), and strictly proved that the coding scheme can achieve the channel capacity. Channel polarization is to transform multiple independent and identical channels into independent and different channels through the operations of channel combination and channel splitting. After the transformation, the channel capacity of each channel tends to polarization, with one part of the channel capacity close to 1 and the other part close to 0. That is, in an ideal situation, after channel polarization, one part of the channel can be used as a noiseless channel for transmitting information, while the other part becomes a full noise channel that can be used to transmit fixed bits, and is directly decoded as known information at the decoding end. Although the channel capacity has changed after the channel polarization, it has not changed substantially.

[0003] The introduction of polar codes quickly attracted widespread attention and research in the academic community, and Polar codes were identified as the channel coding of the control channel in the eMBB scenario in 5G communications. Since then, Polar codes have entered the stage of commercial application in the international communications industry from the stage of theoretical exploration and research in the laboratory.

[0004] Research on Polar code decoding algorithms mainly focuses on the following two aspects: one is to increase the decoding performance as much as possible, and the second is to reduce the algorithm complexity as much as possible while maintaining the decoding performance. When Professor Arikan proposed the polar code encoding scheme, he also gave a decoding scheme for Polar codes, namely the serial cancellation (SC) decoding algorithm, which has low computational complexity and is easy to implement. Then the researchers began to improve the SC decoding algorithm and proposed a series of algorithms based on the SC decoding algorithm, such as the simplified serial cancellation (SSC) decoding algorithm, the stack serial cancellation (SCS) decoding algorithm, the hybrid serial cancellation (SCH) decoding algorithm, the list serial cancellation (SCL) decoding algorithm and the CRC-aided SCL (CA-SCL) decoding algorithm. The introduction of these algorithms has greatly improved the decoding performance and reduced the decoding complexity of Polar under medium and short code lengths.

[0005] However, the above decoding algorithm still has the problem of large Polar decoding delay and too long critical path of the sorting module. Summary of the invention

[0006] The main purpose of the present application is to provide a polar code decoding method, device, storage medium and processor to solve the problem of too long critical path of the sorting module of the Polar code decoding algorithm in the prior art.

[0007] To achieve the above-mentioned purpose, according to one aspect of the present application, a polar code decoding method is provided, including: dividing the nodes on the SSC decoding tree into Rate-0 nodes, Rate-1 nodes, SPC nodes and REP nodes; using an SCL algorithm to process the Rate-0 nodes, the Rate-1 nodes, the SPC nodes and the REP nodes respectively to obtain an optimal decoding path; and using the optimal decoding path to decode the polar code.

[0008] Furthermore, the SCL algorithm is used to process the Rate-0 node, the Rate-1 node, the SPC node and the REP node respectively to obtain the optimal decoding path, including: optimizing the sorting algorithms corresponding to the Rate-0 node, the Rate-1 node, the SPC node and the REP node respectively to obtain the optimal decoding path.

[0009] Furthermore, the sorting algorithm corresponding to the Rate-0 node is optimized, including: adding the LLR values ​​in the Rate-0 node to obtain the addition result; if the number of paths is less than 8, directly writing the addition result into the PM register, otherwise, sorting the path metric values ​​of each path.

[0010] Furthermore, the sorting algorithm corresponding to the Rate-1 node is optimized, including: when the number of paths is equal to 8, updating the two least reliable nodes in the Rate-1 node, wherein the least reliable refers to the Rate-1 node corresponding to the smallest LLR absolute value.

[0011] Furthermore, the sorting algorithm corresponding to the SPC node is optimized, including: determining the node with the smallest LLR absolute value among the SPC nodes, and at the same time, performing a parity check to obtain a check value. If the check value is 1, it indicates that the current node check has failed, and the path metric value is initialized; according to the size of the LLR absolute value of each path, starting from the 2nd bit, the paths are split and sorted in sequence to the Lth bit, where L refers to the number of paths; and updating the decision bit value of the least reliable LLR.

[0012] Furthermore, the sorting algorithm corresponding to the REP node is optimized, including: simultaneously saving two estimates of the information baud in the REP node, the two estimates referring to bit 0 and bit 1.

[0013] According to another aspect of the present application, a polar code decoding device is provided, including: a first processing unit, configured to divide nodes on an SSC decoding tree into Rate-0 nodes, Rate-1 nodes, SPC nodes, and REP nodes; a second processing unit, configured to use an SCL algorithm to process the Rate-0 nodes, the Rate-1 nodes, the SPC nodes, and the REP nodes, respectively, to obtain an optimal decoding path; and a decoding unit, configured to use the optimal decoding path to decode the polar code.

[0014] Furthermore, the second processing unit is also used to optimize the sorting algorithms corresponding to the Rate-0 node, the Rate-1 node, the SPC node and the REP node respectively to obtain the optimal decoding path.

[0015] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute any one of the methods described.

[0016] According to another aspect of the present application, a processor is provided, wherein the processor is used to run a program, wherein any one of the methods is executed when the program is run.

[0017] By applying the technical solution of the present application, the nodes on the SSC decoding tree are divided into four types of nodes, namely Rate-0 nodes, Rate-1 nodes, SPC nodes and REP nodes, and then the SCL algorithm is used to process the Rate-0 nodes, Rate-1 nodes, SPC nodes and REP nodes respectively. That is, a classification processing idea is adopted, and the calculation processing of nodes replaces the calculation processing of bits to improve the decoding parallelism. At the same time, this article also optimizes the sorting algorithm and shortens the length of the critical path, thereby ensuring the decoding accuracy while improving the decoding speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1 A flow chart of a polar code decoding method according to an embodiment of the present application is shown;

[0020] Figure 2 A schematic diagram of a polar code decoding device according to an embodiment of the present application is shown;

[0021] Figure 3 A schematic diagram of an SSC decoding tree according to an embodiment of the present application is shown;

[0022] Figure 4 The prior art sorting method is shown;

[0023] Figure 5 The following shows the sorting method according to the embodiment of the present application;

[0024] Figure 6 shows a flow chart of sorting Rep nodes according to the present application;

[0025] Figure 7 A schematic diagram of a path corresponding to a Rate-1 node according to the present application is shown;

[0026] Figure 8 shows a sorting flow chart of Rate-1 nodes according to the present application;

[0027] Fig. 9 A flowchart of sorting SPC nodes according to the present application is shown. DETAILED DESCRIPTION

[0028] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0029] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0032] As introduced in the background technology, the critical path of the Polar code decoding algorithm sorting module in the prior art is too long. In order to solve the problem of the critical path of the Polar code decoding algorithm sorting module being too long as mentioned above, the embodiments of the present application provide a polar code decoding method, device, storage medium and processor.

[0033] According to an embodiment of the present application, a polar code decoding method is provided.

[0034] Figure 1 is a flow chart of a polar code decoding method according to an embodiment of the present application. Figure 1 As shown, the method comprises the following steps:

[0035] Step S101, dividing the nodes on the SSC decoding tree into Rate-0 nodes, Rate-1 nodes, SPC nodes and REP nodes;

[0036] Step S102, using the SCL algorithm to process the Rate-0 node, the Rate-1 node, the SPC node and the REP node respectively to obtain an optimal decoding path;

[0037] Step S103: Decoding the polar code using the optimal decoding path.

[0038] Specifically, the SCL algorithm is obtained by updating L paths of the SC algorithm.

[0039] In the above scheme, the nodes on the SSC decoding tree are divided into four types of nodes: Rate-0 nodes, Rate-1 nodes, SPC nodes and REP nodes, and then the SCL algorithm is used to process the Rate-0 nodes, Rate-1 nodes, SPC nodes and REP nodes respectively. That is, a classification processing idea is adopted, and the calculation processing of nodes replaces the calculation processing of bits to improve the decoding parallelism. At the same time, this paper also optimizes the sorting algorithm and shortens the length of the critical path. While improving the decoding speed, the decoding accuracy is guaranteed.

[0040] In one embodiment of the present application, the SCL algorithm is used to process the above-mentioned Rate-0 node, the above-mentioned Rate-1 node, the above-mentioned SPC node and the above-mentioned REP node respectively to obtain the optimal decoding path, including: optimizing the sorting algorithms corresponding to the above-mentioned Rate-0 node, the above-mentioned Rate-1 node, the above-mentioned SPC node and the above-mentioned REP node respectively to obtain the above-mentioned optimal decoding path. By optimizing the sorting algorithms corresponding to the Rate-0 node, the above-mentioned Rate-1 node, the above-mentioned SPC node and the above-mentioned REP node, the length of the critical path of the sorting module can be shortened, thereby obtaining the optimal decoding path.

[0041] In one embodiment of the present application, the above sorting algorithm corresponding to the above Rate-0 node is optimized, including: adding the LLR values ​​in the above Rate-0 node to obtain the addition result; if the number of paths is less than 8, directly writing the above addition result into the PM register, otherwise, sorting the path metric values ​​of each path. The above sorting algorithm corresponding to the Rate-0 node is optimized.

[0042] In one embodiment of the present application, the above-mentioned sorting algorithm corresponding to the above-mentioned Rate-1 node is optimized, including: when the number of paths is equal to 8, updating two to at most L-1 least reliable nodes in the above-mentioned Rate-1 node, wherein L represents the number of paths, and the most unreliable means that the absolute value of the LLR corresponding to the above-mentioned Rate-1 node is the smallest. In addition, the above-mentioned sorting algorithm corresponding to the Rate-1 node is optimized.

[0043] In one embodiment of the present application, the above-mentioned sorting algorithm corresponding to the above-mentioned SPC node is optimized, including: determining the node with the smallest LLR absolute value among the above-mentioned SPC nodes, and at the same time, performing a parity check to obtain a check value. If the above-mentioned check value is 1, it means that the current node check fails, and the path metric value is initialized; according to the size of the above-mentioned LLR absolute value of each path, starting from the second bit and sorting the path to the Lth bit in sequence, L refers to the number of paths; updating the judgment bit value of the least reliable LLR. The above-mentioned sorting algorithm corresponding to the SPC node is optimized.

[0044] In one embodiment of the present application, the sorting algorithm corresponding to the REP node is optimized, including: simultaneously saving two estimates of the information baud in the REP node, the two estimates being bit 0 and bit 1. The sorting algorithm corresponding to the REP node is optimized.

[0045] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0046] The embodiment of the present application also provides a polar code decoding device. It should be noted that the polar code decoding device of the embodiment of the present application can be used to execute the polar code decoding method provided in the embodiment of the present application. The polar code decoding device provided in the embodiment of the present application is introduced below.

[0047] Figure 2 is a schematic diagram of a polar code decoding device according to an embodiment of the present application. Figure 2 As shown, the device comprises:

[0048] A first processing unit 10 is used to divide the nodes on the SSC decoding tree into Rate-0 nodes, Rate-1 nodes, SPC nodes and REP nodes;

[0049] The second processing unit 20 is used to respectively process the Rate-0 node, the Rate-1 node, the SPC node and the REP node using an SCL algorithm to obtain an optimal decoding path;

[0050] The decoding unit 30 is configured to decode the polar code by using the optimal decoding path.

[0051] In the above scheme, the first processing unit divides the nodes on the SSC decoding tree into four types of nodes, namely, Rate-0 nodes, Rate-1 nodes, SPC nodes and REP nodes. The second processing unit uses the SCL algorithm to process the Rate-0 nodes, Rate-1 nodes, SPC nodes and REP nodes respectively. That is, a classification processing idea is adopted to replace the bit calculation processing with the node calculation processing to improve the decoding parallelism. At the same time, this paper also optimizes the sorting algorithm and shortens the length of the critical path, thereby ensuring the decoding accuracy while improving the decoding speed.

[0052] In one embodiment of the present application, the second processing unit is further used to optimize the sorting algorithms corresponding to the Rate-0 node, the Rate-1 node, the SPC node and the REP node, respectively, to obtain the optimal decoding path.

[0053] In one embodiment of the present application, the second processing unit includes an addition module and a processing module. The addition module is used to add the LLR values ​​in the above-mentioned Rate-0 node to obtain an addition result; the processing module is used to directly write the above-mentioned addition result into the PM register if the number of paths is less than 8, otherwise, sort the path metric values ​​of each path.

[0054] In one embodiment of the present application, the second processing unit also includes a first update module, which is used to update two to a maximum of L-1 most unreliable nodes among the above-mentioned Rate-1 nodes when the number of paths is equal to 8, wherein L represents the number of paths, and the above-mentioned most unreliable means that the absolute value of the LLR corresponding to the above-mentioned Rate-1 node is the smallest.

[0055] In one embodiment of the present application, the second processing unit includes a determination module, a splitting module and a second updating module. The determination module is used to determine the node with the smallest LLR absolute value among the above-mentioned SPC nodes, and at the same time, perform a parity check to obtain a check value. If the above-mentioned check value is 1, it means that the current node check has failed, and the path metric value is initialized; the splitting module is used to split and sort the paths in sequence from the 2nd bit to the Lth bit according to the size of the above-mentioned LLR absolute value of each path, where L refers to the number of paths; the second updating module is used to update the decision bit value of the least reliable LLR.

[0056] In one embodiment of the present application, the second processing unit includes a storage module, which is used to simultaneously store two estimates of the information baud in the above-mentioned REP node, and the above-mentioned two estimates refer to bit 0 and bit 1.

[0057] The polar code decoding device includes a processor and a memory. The first processing unit, the second processing unit, the decoding unit, etc. are all stored in the memory as program units, and the processor executes the program units stored in the memory to implement corresponding functions.

[0058] The processor includes a kernel, which calls the corresponding program unit from the memory. One or more kernels can be set, and the critical path of the sorting module can be shortened by adjusting the kernel parameters.

[0059] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0060] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, a device where the computer-readable storage medium is located is controlled to execute the polar code decoding method.

[0061] An embodiment of the present invention provides a processor, which is used to run a program, wherein the polar code decoding method is executed when the program is run.

[0062] An embodiment of the present invention provides a device, the device including a processor, a memory, and a program stored in the memory and executable on the processor, and when the processor executes the program, at least the following steps are implemented:

[0063] Step S101, dividing the nodes on the SSC decoding tree into Rate-0 nodes, Rate-1 nodes, SPC nodes and REP nodes;

[0064] Step S102, using the SCL algorithm to process the Rate-0 node, the Rate-1 node, the SPC node and the REP node respectively to obtain an optimal decoding path;

[0065] Step S103: Decoding the polar code using the optimal decoding path.

[0066] The devices in this article can be servers, PCs, PADs, mobile phones, etc.

[0067] The present application also provides a computer program product, which, when executed on a data processing device, is suitable for executing a program for initializing at least the following method steps:

[0068] Step S101, dividing the nodes on the SSC decoding tree into Rate-0 nodes, Rate-1 nodes, SPC nodes and REP nodes;

[0069] Step S102, using the SCL algorithm to process the Rate-0 node, the Rate-1 node, the SPC node and the REP node respectively to obtain an optimal decoding path;

[0070] Step S103: Decoding the polar code using the optimal decoding path.

[0071] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0072] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0073] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0074] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0075] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0076] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0077] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0078] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0079] Example

[0080] This embodiment relates to a specific polar code decoding method.

[0081] like Figure 3 As shown, Figure 3 The α in represents the transmission of soft information LLR from the parent node to the child node, and β represents the transmission of the partial sum from the child node to the parent node.

[0082] If 8-bit decoding is performed, the path metric (PM) sorting requires at most 16 to 8. The standard two-tone sorting method is as follows Figure 4As shown, 10 levels of comparison are required.

[0083] In the Polar decoding algorithm, there is a certain data relationship when PM is generated, and the PM sorting algorithm can be optimized based on the inherent data relationship.

[0084] Data relationship 1: When the path is extended in the path calculation module, the new path metric values ​​obtained after the extension are placed in the former output if they have not increased, and placed in the latter if they have increased. Then they are sent to the path sorting unit to obtain the following relationship:

[0085] m 2i ≤m 2i+1 ,i=0,1,2,...,7;

[0086] Data relationship 2: Assuming that the first four PM values ​​of the original 8 PM values ​​strictly follow the principle of small to large, when selecting 8 from 16, the four smallest PM values ​​of the original PM values ​​will definitely be used as the output result. That is, the input of the 16-select-8 algorithm must satisfy m0<m2<m4<m6.

[0087] The sorting algorithm can be optimized based on two data relations. The first step is to delete the pairwise comparisons in the first state based on data relation 1. The first state refers to the comparison of the data of the odd and even index bits. The second step is to continue to delete the comparisons about m0, m2, m4, and m6 based on data relation 2. The third step is to delete all the comparisons about the largest 8 data relations because we only need the smallest 8 outputs. After deletion, only 6 levels of comparison are needed, such as Figure 5 As shown, under the current process, one cycle is achievable.

[0088] The classification calculations about nodes include:

[0089] 1) About Rate-0 Node

[0090] like Figure 3 As shown, the Rate-0 node is represented by a white circle. All bits below this node are frozen bits, and the calculation of the leaf node (stage 0) is no longer performed during decoding, and all estimated bits are set to 0.

[0091] When the Rate-0 node is updated, no path expansion or deletion is performed, and the number of paths remains unchanged after the update. The path metric is calculated as follows:

[0092]

[0093] in, represents the path metric value of the Ns-1th bit on the lth path, α ilIt represents the LLR value of the i-th bit on the l-th path. Exact means the result derived from the actual mathematical formula. HWF means hardwarefriendly, which is an approximate formula that is convenient for hardware calculation.

[0094] The implementation scheme of Rate0 node is:

[0095] The Rate0 node needs to do two things. First, add the LLR information in the node. The rule for addition is that if the LLR symbol value is 1 (beta is 1 after hard decision, which is opposite to the frozen bit), the absolute value of the LLR is added. A node has a maximum of 32 LLR values, so 5 levels of addition are required. Second, when the number of paths L is equal to 8, sorting is required, otherwise the addition result is directly written into the PM register. The number of paths is constantly split, which is a process from 1 to 2, from 2 to 4, from 4 to 8, and from 8 to 16. The maximum number of paths set in the current decoding scheme is 8. When the number of paths is equal to 16, the path metric values ​​need to be sorted. Select the 8 paths with the smallest path metric values. The 16-in-8 sorting algorithm used in this article is an optimized version. In order to meet the optimization requirements, sorting is required when L=8 of the Rate0 node.

[0096] Since there are only frozen bits in the rate0 node, the hard decision bits (hardbit) do not need to be updated, but some modules need to be updated.

[0097] 2) About REP Node

[0098] like Figure 3 As shown, REP nodes are represented by white triangles.

[0099] In this node, only the rightmost leaf node is an information bit, and the others are frozen bits. When updating the REP node, it is necessary to save two estimates of the information bit, namely bits 0 and 1. Therefore, after the REP node is updated, the number of paths will change from L to 2L. The calculation formula for the path metric value corresponding to this node is:

[0100]

[0101] in, represents the path metric value of the Ns-1th bit on the lth path, α il It represents the LLR value of the i-th bit on the l-th path. Exact means the result derived from the actual mathematical formula. HWF means hardwarefriendly, which is an approximate formula convenient for hardware calculation. η represents the XOR value of all bits in the current node.

[0102] The implementation scheme of the Rep node is as follows Figure 6As shown,

[0103] When the current number of paths (l_cnt) is 8, the Rep node needs to go through 6 states.

[0104] State 1: Path metric calculation state (PM_calc). In this state, the double (8→16) of the path is completed, including the update of the path PM and beta.

[0105] State 2: The first path metric value sorting state, with a total of 8 values ​​(pm_sort8to8), is to update the first 8 of the 16 PM values;

[0106] State 3: The second pm_sort8to8 updates the last 8 of the 16 PM values;

[0107] State 4: The third pm_sort8to8 sorts the first four of the first two sorting results.

[0108] State 5: pm_sort16to8 sorts the results of three 8 sorts.

[0109] State 6: Node beta value update state (node ​​beta update).

[0110] The significance of state 2, state 3, and state 4 is to satisfy the input data rule of the 16-choose-8 module.

[0111] 3) About Rate-1 Node

[0112] like Figure 3 As shown, the Rate-1 node is represented by a black circle.

[0113] When updating a rate-1 node, it is not necessary to expand all the 2s-th power leaf nodes (s, i.e., stage) under the node like in SCL. When the path L=8, for a rate-1 node, only the two least reliable nodes (with the smallest LLR absolute value) need to be updated to achieve no loss in decoding correctness, greatly speeding up the decoding speed.

[0114] The calculation formula for the path metric of a rate-1 node is:

[0115]

[0116] in, represents the path metric value of the Ns-1th bit on the lth path, α ilIt represents the LLR value of the i-th bit on the l-th path. Exact means the result derived from the actual mathematical formula. HWF means hardwarefriendly, which is an approximate formula convenient for hardware calculation. η represents the XOR value of all bits in the current node.

[0117] Figure 7 This is the path diagram corresponding to the Rate-1 node.

[0118] The sorting steps include:

[0119] Step 0: Sort the absolute values ​​of each LLR of each path from small to large (only the smallest L-1 are needed).

[0120] Step 1: Split the first LLR value of each path, then sort the PM values ​​of the obtained 2L paths and select the smallest L paths.

[0121] The PM value of the new path after splitting is:

[0122] PM10=PM00

[0123] PM11=PM00+a0(such as Figure 7 (shown)

[0124] PM12=PM01

[0125] PM13=PM01+b0(such as Figure 7 (shown)

[0126] PM14=PM02

[0127] PM15=PM02+c0(such as Figure 7 (shown)

[0128] PM16=PM03

[0129] PM17=PM03+d0(such as Figure 7 (shown)

[0130] Assuming PM12>PM11, it means that the new path after path 1 splits has a higher probability than the original path PM01 and can survive. At this time, the path PM03 with the largest PM value can be directly deleted.

[0131] In addition, suppose the selected bit α il The maximum PM path value greater than the previous bit, i.e., bit i-1, minus the minimum PM path value, i.e.:

[0132]

[0133] In this case, no splitting would be required.

[0134] Step 2-(L-1): Split the second LLR value. The operation is similar to Step 1.

[0135] It should be noted that Figure 7 The LLR indices 0, 1, 2, 3, ... in are the order of their magnitudes, not the corresponding bit positions.

[0136] The implementation scheme of Rate1 node is as follows Figure 8 As shown:

[0137] Rate1 nodes require three states:

[0138] State 1: LLR absolute value sorting (llr_abs_sort). In this state, the LLR absolute values ​​of the nodes are sorted from small to large, with a maximum of 32 data.

[0139] State 2: pm_calc&pm_sort. There are two forms in this state. If the current number of paths l_cnt is less than 8, only the path metric value calculation state (pm_calc) is performed, that is, the pm_only_calc state in the code. Otherwise, when l_cnt is equal to 8, this state needs to complete two operations: pm_calc and path metric value sorting state (pm_sort).

[0140] pm_calc needs to complete the calculation of the PM value, and at this time the path is doubled and split. The path double includes two contents, the first is the PM value, and the second is the decision bit beta result, as follows:

[0141] new_PM 2i =PM i

[0142] new_PM 2i+1 =PM i +llr_abs i

[0143] new_beta 2i =beta i

[0144] new_beta 2i+1 =~beta i

[0145] Among them, llr_abs i represents the absolute value of the LLR of the i-th bit.

[0146] pm_sort needs to sort the PM values. When the path changes from 4 to 8 (4→8), the pm_sort8to8 module needs to be used. When the path starts with 8, that is, the operation of 8→16→8 needs to be completed, the pm_sort16to8 module is needed.

[0147] State 3: node_beta_up, when the beta value in the path is updated, two operations need to be completed in one cycle.

[0148] First: exchange the original beta values ​​of each path according to the path node_pointer_mem;

[0149] Second: write the beta value of the current decoded bit into the path beta value.

[0150] 4) About SPC nodes

[0151] SPC nodes, Figure 3 The SPC node utilizes the parity check feature, which is not used in the traditional SCL decoding algorithm.

[0152] Theoretically, it is proved that at most min(L,Nv) nodes need to be updated in the SPC node, where L represents the maximum number of paths and Nv represents the number of bits in the current node.

[0153] The calculation of the SPC node is divided into three steps:

[0154] STEP0: Find the point with the smallest absolute value of LLR in the node. At the same time, calculate lamda (using parity). If lamda=1, it means that the parity check of the current node fails. Directly invert the most unreliable LLR (inversion means taking the opposite value, positive to negative, negative to positive), and initialize the PM value.

[0155] Find the LLR with the minimum absolute value:

[0156]

[0157] Among them, α i represents the LLR of the i-th bit, N S Indicates the bit combing within the current node.

[0158] Calculate the lamda value:

[0159]

[0160] Initialize PM value:

[0161]

[0162] STEP 1: Based on the absolute value of each path LLR, split (update the path metric value) and sort the paths from the second bit to the Lth bit. The steps are similar to STEP 1 of the Rate-1 node.

[0163] Update the path metrics:

[0164]

[0165] STEP 2: After each path is updated, update the beta value of the least reliable LLR to meet the parity check.

[0166]

[0167] The implementation scheme of SPC node is as follows Fig. 9 shown.

[0168] SPC nodes have five states:

[0169] State 1: llr_abs_sort&lamda_calc. llr_abs_sort has the same function as rate1 node, sorting up to 32 LLR absolute values ​​in the node.

[0170] lamda_calc is used to check the parity of the node. The XOR result of all beta values ​​in the SPC node is 0, and lamda is the XOR result of all beta values ​​in the node.

[0171] State 2: This state updates and sorts PMs based on the lamda value.

[0172] If lamda=1, that is, the parity is not satisfied, then it is necessary to add the llr_abs with the smallest absolute value on the path to the PM value of the path. (In fact, according to the process, it is also necessary to invert the beta at the position with the smallest LLR absolute value, but there is a parity check step at the end of the SPC node, so this operation can be omitted).

[0173] If lamda=0, the path does not update the PM value.

[0174] After the PM values ​​of the eight paths are updated, the new values ​​are sorted (the significance of this step is to meet the input requirements of the 16→8 module).

[0175] State 3: This state has two operations, pm_calc and pm_sort16to8. Same as rate1 node.

[0176] State 4: node_beta_up.

[0177] State 5: PC check. This state completes the parity check of the SPC node, that is, all beta values ​​under the path are XORed. If the result is 1, the beta at the position with the smallest absolute value is reversed.

[0178] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0179] 1) The polar code decoding method of the present application divides the nodes on the SSC decoding tree into four types of nodes: Rate-0 nodes, Rate-1 nodes, SPC nodes, and REP nodes, and then uses the SCL algorithm to process the Rate-0 nodes, Rate-1 nodes, SPC nodes, and REP nodes respectively. That is, a classification processing idea is adopted, which shortens the critical path of the sorting module in the SCL algorithm, thereby improving the decoding speed and ensuring the decoding accuracy.

[0180] 2) In the polar code decoding device of the present application, the first processing unit divides the nodes on the SSC decoding tree into four types of nodes: Rate-0 nodes, Rate-1 nodes, SPC nodes, and REP nodes. The second processing unit uses the SCL algorithm to process the Rate-0 nodes, Rate-1 nodes, SPC nodes, and REP nodes respectively, that is, a classification processing idea is adopted, so that the critical path of the sorting module in the SCL algorithm is shortened, while the decoding speed is improved, the decoding accuracy is guaranteed.

[0181] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A polar code decoding method, characterized in that: include: The nodes on the SSC decoding tree are divided into Rate-0 nodes, Rate-1 nodes, SPC nodes and REP nodes; The Rate-0 node, the Rate-1 node, the SPC node and the REP node are processed respectively using an SCL algorithm to obtain an optimal decoding path; Decoding the polar code using the optimal decoding path; The Rate-0 node, the Rate-1 node, the SPC node, and the REP node are processed respectively using the SCL algorithm to obtain an optimal decoding path, including: Optimizing the sorting algorithms corresponding to the Rate-0 node, the Rate-1 node, the SPC node, and the REP node respectively to obtain the optimal decoding path; Optimizing the sorting algorithm corresponding to the SPC node includes: Determine the node with the smallest LLR absolute value among the SPC nodes, and at the same time, perform a parity check to obtain a check value. If the check value is 1, it indicates that the current node check fails, and initialize the path metric value; According to the LLR absolute value of each path, split and sort the paths in sequence starting from the second bit to the Lth bit, where L refers to the number of paths; Update the decision bit value of the least reliable LLR.

2. The method according to claim 1, characterized in that: Optimizing the sorting algorithm corresponding to the Rate-0 node includes: Adding the LLR values ​​in the Rate-0 node to obtain an addition result; If the number of paths is less than 8, the addition result is directly written into the PM register; otherwise, the path metric values ​​of each path are sorted.

3. The method according to claim 1, characterized in that Optimizing the sorting algorithm corresponding to the Rate-1 node includes: When the number of paths is equal to 8, the two least reliable nodes among the Rate-1 nodes are updated, where the least reliable refers to the Rate-1 node having the smallest LLR absolute value.

4. The method according to claim 1, characterized in that: Optimizing the sorting algorithm corresponding to the REP node, including: At the same time, two estimates of the information baud in the REP node are saved, the two estimates being bit 0 and bit 1.

5. A polar code decoding device, characterized in that: include: A first processing unit, configured to divide the nodes on the SSC decoding tree into Rate-0 nodes, Rate-1 nodes, SPC nodes, and REP nodes; A second processing unit, configured to respectively process the Rate-0 node, the Rate-1 node, the SPC node, and the REP node using an SCL algorithm to obtain an optimal decoding path; A decoding unit, configured to decode the polar code using the optimal decoding path; The second processing unit is further used to optimize the sorting algorithms corresponding to the Rate-0 node, the Rate-1 node, the SPC node and the REP node respectively to obtain the optimal decoding path; The second processing unit includes a determination module, a splitting module and a second updating module. The determination module is used to determine the node with the smallest LLR absolute value among the SPC nodes, and at the same time, perform a parity check to obtain a check value. If the check value is 1, it means that the current node check fails, and the path metric value is initialized; the splitting module is used to split and sort the paths in sequence from the 2nd bit to the Lth bit according to the size of the LLR absolute value of each path, where L refers to the number of paths; the second updating module is used to update the decision bit value of the least reliable LLR.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the method according to any one of claims 1 to 4.

7. A processor, characterized in that: The processor is used to run a program, wherein the program executes the method according to any one of claims 1 to 4 when running.

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