Time-of-flight measurement circuit and control method thereof and electronic device

Abstract

A time-of-flight measurement circuit (100, 400, 600) and a related control method and electronic device. The time-of-flight measurement circuit (100, 400, 600) comprises a pixel array (102, 602), a first controller (104) and a time-to-digital converter (106, 406, 606). The pixel array (102, 602) comprises m rows×n columns of pixel units (P11-P1n, P21-P2n, ... Pm1-Pmn, P11'-P1n', P21'-P2n', ... Pm1'-Pmn'). The first controller (104) is coupled to the input end of the first buffer of each of the first column pixel units (P11-Pm1, P11'-Pm1'), and the input end of the first buffer of the pixel unit Pxy is coupled to the output end of the first buffer of the pixel unit Px(y-1), x is an integer from 1 to m, and y is an integer from 2 to n, wherein in a test mode, the first controller (104) transmits a first trigger signal sequentially through the first buffers Ba1-Ban in the pixel units Pa1-Pan, wherein a is any integer from 1 to m, and when a is less than m, the first trigger signal reaches the pixel units Pm1-Pmn from the output ends of the pixel units Pa1-Pan.

Description

Technical Field

[0001] The present application relates to a time-of-flight measurement circuit, and more particularly to a time-of-flight measurement circuit capable of obtaining internal delay information in a test mode, and a related control method and electronic device. Background Art

[0002] Time-of-flight measurement technology includes direct time-of-flight measurement technology and indirect time-of-flight measurement technology (also called indirect time-of-flight measurement technology). Direct time-of-flight measurement technology uses a light pulse to be emitted, and then measures the time interval between the reflected light pulse and the emitted light pulse to obtain the light flight time, and then uses the measured flight time to calculate the depth information. The difficulty of direct time-of-flight measurement technology is that it needs to be able to distinguish very fine time differences. For example, if you need to achieve a ranging accuracy of 1.5 cm, the resolution needs to reach 10 picoseconds.

[0003] However, in reality, when implementing direct time-of-flight measurement technology, various non-ideal errors may contribute to errors in the measured flight time. Therefore, how to improve accuracy has become one of the problems that need to be solved urgently in this field. Summary of the invention

[0004] One of the purposes of the present application is to disclose a time-of-flight measurement circuit and a related control method and electronic device to solve the above-mentioned problem.

[0005] An embodiment of the present application discloses a time-of-flight measurement circuit, comprising: a pixel array, comprising m rows×n columns of pixel units, wherein m and n are positive integers, and each of the pixel units comprises: a photosensitive sensor; and a first buffer, wherein the first buffer delays the time of the signal passing therethrough as a first buffer delay; wherein the pixel unit outputs the sensing result of the photosensitive sensor in a normal mode, and the pixel unit outputs the buffer result output by the first buffer in a test mode; a first controller, coupled to the input end of the first buffer of each of the pixel units in the 1st column, and the input end of the first buffer of the pixel unit in the xth row and the yth column is coupled to the output end of the first buffer of the pixel unit in the xth row and the y-1st column, x is an integer from 1 to m, and y is an integer from 2 to n, wherein in the test mode, the first controller transmits a first trigger signal, so that the first trigger signal passes through the first buffers of the pixel units in the 1st to the yth columns of the xth row in sequence, when When x is less than m, the first trigger signal is further outputted from the output end of the first buffer of the pixel unit of the xth row and yth column through the output end of the pixel unit of the xth row and yth column to the pixel unit of the (x+1)th row and yth column, until reaching the pixel unit of the mth row and yth column; and a time-to-digital converter, comprising: a counter, coupled to the first controller, and counting according to a reference clock; n registers, including the 1st register to the nth register, correspondingly coupled to the n output ends of the pixel units of the 1st to the nth columns of the mth row, wherein the yth register temporarily stores a first count value of the counter based on the first trigger signal received from the output end of the pixel unit of the mth row and yth column; and a first start time register, coupled to the input ends of the m first buffers of the m pixel units of the 1st column, for receiving the first trigger signal, wherein the first start time register temporarily stores a first start time count value of the counter according to the received first trigger signal.

[0006] An embodiment of the present application discloses a control method for a time-of-flight measurement circuit, comprising: controlling the time-of-flight measurement circuit to enter the test mode; using the first controller to transmit the first trigger signal at a first time point, so that the first trigger signal sequentially passes through the first buffer of each pixel unit in the pixel units of the xth row and the 1st column to the xth row and the nth column, so as to obtain: the first starting time count value; the first count value of the yth register, which corresponds to the sum of y first buffer delays and the pixel path delay from the pixel unit of the xth row and the yth column to the yth register; and the reference The reference count value of the register corresponds to m first buffer delays; the first buffer delay is obtained according to the first start time count value and the reference count value; the total path delay of the first trigger signal after passing through the first buffers in the pixel units of the xth row, the 1st column to the yth column, and then passing through the pixel units of the yth column, the xth column to the mth row to the yth register is obtained according to the first start time count value and the first count value; and the pixel path delay from the pixel unit of the xth row, the yth column to the yth register is obtained according to the first buffer delay and the total path delay.

[0007] An embodiment of the present application discloses a control method for a time-of-flight measurement circuit, comprising: controlling the time-of-flight measurement circuit to enter the test mode; using the first controller to transmit the first trigger signal at a first time point, so that the first trigger signal sequentially passes through the first buffer of each pixel unit in the pixel units in the x-th row and the 1st column to the x-th row and the nth column, so as to obtain: the first starting time count value; the first count value of the y-th register, which corresponds to the sum of y first buffer delays and the pixel path delay from the pixel unit in the x-th row and the y-th column to the y-th register; and the first count value of the z-th register, which corresponds to the z-th the sum of the first buffer delay and the pixel path delay from the pixel unit in the xth row and the zth column to the zth register, wherein z is an integer from 1 to n, and y and z are different integers; using the second controller to transmit the second trigger signal at a second time point, so that the second trigger signal sequentially passes through the second buffer of each pixel unit from the pixel unit in the xth row and the nth column to the xth row and the 1st column, so as to obtain: the second start time count value; the second count value of the yth register, which corresponds to the sum of (n-y+1) second buffer delays and the pixel path delay from the pixel unit in the xth row and the yth column to the yth register; and the zth register the second count value of the register, which corresponds to the sum of (n-y+1) second buffer delays and the pixel path delay from the pixel unit in the xth row and the zth column to the zth register; according to the first start time count value, the first count value of the yth register and the first count value of the zth register, the first total path delay of the first trigger signal after passing through the first buffers in the pixel units in the xth row and the 1st column to the yth column and then passing through the pixel units in the yth column and the xth to the mth row to the yth register is obtained, and the first trigger signal after passing through the first buffers in the pixel units in the xth row and the 1st column to the zth column and then passing through the zth register is obtained. a second total path delay of the pixel units in the xth to mth rows in the xth row being transmitted to the zth register; a third total path delay of the second trigger signal passing through the pixel units in the xth to nth rows in the yth row and then being transmitted to the yth register through the pixel units in the yth to xth rows in the mth row according to the second start time count value, the second count value of the yth register and the second count value of the zth register, and a fourth total path delay of the second trigger signal passing through the pixel units in the xth to nth rows in the xth row and then being transmitted to the zth register through the pixel units in the zth to xth rows in the mth row;and obtaining the first buffer delay, the second buffer delay, the pixel path delay from the pixel unit in the xth row and yth column to the yth register, and the pixel path delay from the pixel unit in the xth row and zth column to the zth register according to the first total path delay, the second total path delay, the third total path delay, and the fourth total path delay. ;

[0008] An embodiment of the present application discloses an electronic device, including the above-mentioned time-of-flight measurement circuit.

[0009] An embodiment of the present application discloses an electronic device, including a time-of-flight measurement circuit, including: a pixel array, including m rows×n columns of pixel units, wherein m and n are positive integers, and each of the pixel units includes: a photosensitive sensor; and a first buffer, wherein the first buffer delays the time of the signal passing therethrough as a first buffer delay; wherein the pixel unit outputs the sensing result of the photosensitive sensor in a normal mode, and the pixel unit outputs the buffered result output by the first buffer in a test mode; and a controller, for: controlling the time-of-flight measurement circuit to enter the normal mode, so that the sensing result of the photosensitive sensor of the pixel unit in the xth row and yth column outputs a corresponding first time-of-flight signal through the yth register, and The sensing result of the photosensor of the pixel unit in the xth row and the zth column is outputted through the zth register as a corresponding second time-of-flight signal; a corrected first time-of-flight signal is obtained according to the first time-of-flight signal and the pixel path delay from the pixel unit in the xth row and the yth column to the yth register; and a corrected second time-of-flight signal is obtained according to the second time-of-flight signal and the pixel path delay from the pixel unit in the xth row and the zth column to the zth register, wherein the pixel path delay from the pixel unit in the xth row and the yth column to the yth register and the pixel path delay from the pixel unit in the xth row and the zth column to the zth register are measured by the controller controlling the time-of-flight measurement circuit to be in the test mode.

[0010] The flight time measurement circuit of the present application can obtain internal delay information in a test mode, which can be used to calibrate the measured flight time to improve accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 FIG. 1 is a schematic diagram of a first embodiment of a time-of-flight measurement circuit of the present application.

[0012] Figure 2 for Figure 1 Circuit diagram of a pixel unit in a pixel array.

[0013] Figure 3 To illustrate the first trigger signal Figure 1 Schematic diagram of the transfer method in the time-of-flight measurement circuit.

[0014] Figure 4 FIG. 1 is a schematic diagram of a second embodiment of a time-of-flight measurement circuit of the present application.

[0015] Figure 5 To illustrate the first trigger signal Figure 4 Schematic diagram of the transfer method in the time-of-flight measurement circuit.

[0016] Figure 6 FIG. 1 is a schematic diagram of a third embodiment of a time-of-flight measurement circuit of the present application.

[0017] Figure 7 for Figure 6 Circuit diagram of a pixel unit in a pixel array.

[0018] Figure 8 To illustrate the second trigger signal Figure 6 Schematic diagram of the transfer method in the time-of-flight measurement circuit.

[0019] Fig. 9 For explaining the use of the first trigger signal and the second trigger signal to measure Figure 6 Schematic diagram of the time-of-flight measurement circuit. DETAILED DESCRIPTION

[0020] The following disclosure provides a variety of implementations or illustrations that can be used to implement different features of the present disclosure. The specific examples of components and configurations described below are used to simplify the present disclosure. As can be imagined, these descriptions are only illustrative and are not intended to limit the present disclosure. For example, in the description below, forming a first feature on or above a second feature may include certain embodiments in which the first and second features are directly in contact with each other; and may also include certain embodiments in which additional components are formed between the above-mentioned first and second features, so that the first and second features may not be in direct contact. In addition, the present disclosure may reuse component symbols and / or labels in multiple embodiments. Such repetition is based on the purpose of simplicity and clarity, and does not itself represent the relationship between the different embodiments and / or configurations discussed.

[0021] Furthermore, spatially relative terms such as "below," "below," "below," "above," and the like may be used herein to facilitate description of the relationship between one component or feature shown in the figure relative to another or more components or features. These spatially relative terms are intended to encompass a variety of different orientations of the device during use or operation in addition to the orientation shown in the figure. The device may be placed in other orientations (e.g., rotated 90 degrees or in other orientations), and these spatially relative descriptive terms should be interpreted accordingly.

[0022] Although the numerical ranges and parameters used to define the broader scope of the present application are approximate values, the relevant numerical values ​​in the specific embodiments have been presented as accurately as possible. However, any numerical value inherently inevitably contains standard deviations due to individual testing methods. Here, "about" generally refers to the actual value within plus or minus 10%, 5%, 1% or 0.5% of a specific value or range. Alternatively, the term "about" means that the actual value falls within the acceptable standard error of the mean value, depending on the consideration of a person with ordinary knowledge in the technical field to which the present application belongs. It should be understood that, except for the experimental examples, or unless otherwise explicitly stated, all ranges, quantities, values ​​and percentages used herein (for example, to describe the amount of material used, the length of time, temperature, operating conditions, quantitative ratios and the like) are modified by "about". Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in this specification and the attached patent scope are all approximate values ​​and can be changed as needed. At least these numerical parameters should be understood as the number of significant digits indicated and the values ​​obtained by applying the general rounding method. Herein, numerical ranges are expressed from one endpoint to another endpoint or between two endpoints; unless otherwise stated, the numerical ranges described herein include the endpoints.

[0023] In reality, when implementing direct flight time measurement technology, various non-ideal errors may contribute errors to the measured flight time, especially the delay of the transmission path inside the chip, which will directly affect the measured flight time. The flight time measurement circuit and control method of the present application can estimate the delay of the transmission path inside the chip in the test mode, and use the delay of the transmission path calculated in the test mode to correct the flight time in the normal mode. The details are as follows.

[0024] Figure 11 is a schematic diagram of a first embodiment of a time-of-flight measurement circuit of the present application, wherein the time-of-flight measurement circuit 100 includes a pixel array 102, a first controller 104, and a time-to-digital converter 106. Specifically, the pixel array 102 includes m rows×n columns of pixel units, where m and n are positive integers. For example, the pixel unit P11 represents the pixel unit in the first row and the first column of the pixel array 102, and the pixel unit Pmn represents the pixel unit in the mth row and the nth column of the pixel array 102.

[0025] Each pixel unit in the pixel array 102 includes a photosensitive sensor and a first buffer. Generally speaking, the photosensitive sensor can be implemented by a single photon avalanche diode, but the present application is not limited thereto. In addition, the first buffer delays the signal passing through by a first buffer delay TB1, and the first buffer delay TB1 of the first buffer of each pixel unit in the pixel array 102 is substantially the same. The time-of-flight measurement circuit 100 has a normal mode and a test mode. In the normal mode, each pixel unit in the pixel array 102 outputs the sensing result of the photosensitive sensor, and in the test mode, outputs the buffer result output by the first buffer.

[0026] Please refer to Figure 1 and Figure 2 , Figure 2 is a circuit diagram of pixel units P22, P23, P32 and P33 in the pixel array 102. It should be noted that each pixel unit in the pixel array 102 is identical, so Figure 2 The illustrated pixel units P22, P23, P32 and P33 can also be used to illustrate other pixel units not illustrated. Taking the pixel unit P22 as an example, it can be seen that it further includes an OR gate O22 and an AND gate A22, wherein the first input end of the OR gate O22 is coupled to the photosensitive sensor D22, and the second input end of the OR gate O22 is used to receive the test mode enable signal TE from the first controller 104, and the test mode enable signal TE is used to indicate that the flight time measurement circuit 100 is currently in the test mode or the normal mode. The first input end of the AND gate A22 is coupled to the output end of the OR gate O22, and the second input end of the AND gate A22 is coupled to the output end of the first buffer B22.

[0027] Therefore, taking the pixel unit P22 as an example, in the general mode, the enable signal TE is 0 (low logic level), and the OR gate O22 will output the sensing result of the photosensor to the first input terminal of the AND gate A22. When RS2 is set to 1 (high logic level), it represents the selection of reading the second row of pixel units P21~P2n. At this time, the high logic level passes through the first buffer B22 to make the second input terminal of the AND gate A22 also a high logic level, so that the AND gate A22 outputs the output of the OR gate O22, that is, outputs the sensing result of the photosensor.

[0028] In the test mode, taking the pixel unit P22 as an example, the enable signal TE is 1 (high logic level), and the OR gate O22 will continue to output 1 (high logic level) to the first input terminal of the AND gate A22, so that the output of the AND gate A22 follows the input of the second input terminal of the AND gate A22, that is, the AND gate A22 outputs the buffer result of the output of the first buffer B22.

[0029] When the time-of-flight measurement circuit 100 is implemented in hardware, for example, when the time-of-flight measurement circuit 100 is implemented in a chip, on the integrated circuit layout, the first controller 104 is located on the side of the adjacent first column pixel unit P11-Pm1, and is correspondingly coupled to the input end of the first buffer B11-Bm1 of the first column pixel unit P11-Pm1 through the paths RS1-RSm, and the input end of the first buffer of the pixel unit in the xth row and yth column is coupled to the output end of the first buffer of the pixel unit in the xth row and y-1th column, where x is an integer from 1 to m, and y is an integer from 2 to n. For example, the input end of the first buffer B12-Bm2 of the second column pixel unit P12-Pm2 is coupled to the output end of the first buffer B11-Bm1 of the first column pixel unit P11-Pm1, and so on.

[0030] In the test mode, the first controller 104 may transmit the first trigger signal S1 to any row of pixel units in the pixel array 102. For example, when the first trigger signal S1 is transmitted to the a-th row of pixel units Pa1-Pan, where a is any integer from 1 to m, the first controller 104 transmits the first trigger signal S1 through the path RSa, and the first trigger signal S1 passes through the first buffers Ba1-Ban in the a-th row of pixel units Pa1-Pan in sequence, that is, Figure 1 After entering each pixel unit Pa1-Pan, the first trigger signal S1 is output from the output end of each pixel unit Pa1-Pan to the input end of the next row of pixel units through the AND gates Aa1-Aan. Figure 1 For example, it presents a downward vertical transmission, that is, when a is less than m, the first trigger signal S1 will be output from the output ends of the pixel units Pa1~Pan in the a-th row, and then pass through the pixel units in the (a+1)-th row to the m-th row in sequence; when a is equal to m, the first trigger signal S1 will be directly output from the output ends of the pixel units Pm1~Pmn in the m-th row to the time-to-digital converter 106 outside the pixel array 102.

[0031] The time-to-digital converter 106 includes a counter 108, n registers L1-Ln, and a first start time register LS1. The counter 108 counts according to a reference clock. The n registers L1-Ln include registers L1 to Ln. When the time-of-flight measurement circuit 100 is implemented in hardware, for example, when the time-of-flight measurement circuit 100 is implemented in a chip, on the integrated circuit layout, the registers L1-Ln are located on the side of the adjacent pixel units Pm1-Pmn, and are correspondingly coupled to the n output terminals of the pixel units Pm1-Pmn. The registers L1-Ln respectively store the first count value of the counter 108 based on the first trigger signal S1 received from the n output terminals of the pixel units Pm1-Pmn. That is, when the pixel unit Pm1 outputs the first trigger signal S1 to the register L1, the register L1 will temporarily store the count result of the counter 108 at this time as the first count value. In this embodiment, the counter 108 is coupled to the first controller 104 , and the first controller 104 can reset the counter 108 , that is, clear the counter 108 to zero.

[0032] Figure 3 is a schematic diagram for explaining the transmission method of the first trigger signal S1 in the time-of-flight measurement circuit 100 . Figure 3 In the example, the first controller 104 transmits the first trigger signal S1 through the path RS1. The first trigger signal S1 passes through all pixel units P11-P1n of the first row in sequence to the left, and then passes through all pixel units of the second to mth rows in sequence from the pixel units P11-P1n of the first row to the bottom and then outputs to the registers L1-Ln. The first trigger signal S1 passes through n different paths, i.e., D11-D1n, from leaving the first controller 104 to entering the registers L1-Ln. The total path delays caused by the n paths D11-D1n are different, resulting in different times for the registers L1-Ln to receive the first trigger signal S1. The corresponding registers L1-Ln respectively temporarily store the first count values ​​output by the counter 108 at different times, that is, the n first count values ​​temporarily stored by the n registers are also different. Generally speaking, the total path delays caused by the n paths D11 -D1n increase in sequence, and therefore, the n first count values ​​temporarily stored in the registers L1 -Ln also increase in sequence.

[0033] The first start time register LS1 is coupled to the input terminals of the m first buffers of the m pixel units P11-Pm1 in the first row. Therefore, when the first controller 104 intends to transmit the first trigger signal S1 to any row of pixel units in the pixel array 102, the first start time register LS1 will receive the first trigger signal S1 and store the first start time count value of the counter 108 according to the received first trigger signal S1. Therefore, the total path delays T11-T1n caused by the n paths D11-D1n can be obtained by deducting the first start time count value of the first start time register LS1 from the n first count values ​​stored in the registers L1-Ln.

[0034] Therefore, for the pixel units in the 1st row to the mth row in the pixel array 102, the first controller 104 transmits the first trigger signal S1 to the registers L1 to Ln through different paths RS1 to RSm, and there are n paths respectively, that is, there are n*m ​​paths D11 to D1n, D21 to D2n, D31 to D3n, ..., Dm1 to Dmn in total. When the flight time measurement circuit 100 is to be tested, the test mode enable signal TE can be used to control the flight time measurement circuit 100 to enter the test mode, and then for the pixel units in the 1st row to the mth row in the pixel array 102, the test mode enable signal TE can be used to control the flight time measurement circuit 100 to enter the test mode. Figure 3 In this way, n*m paths D11~D1n, D21~D2n, D31~D3n, ..., Dm1~Dmn are obtained m times. Figure 3 It can be seen that:

[0035] Total path delay Tab = b*TB1 + Pab to Lb delay (1)

[0036] , where a is any integer from 1 to m, and b is any integer from 1 to n. For example, the total path delay T11 caused by path D11 = 1*first buffer delay TB1 + pixel path delay from pixel unit P11 to register L1, the total path delay T12 caused by path D12 = 2*first buffer delay TB1 + pixel path delay from pixel unit P12 to register L2, and so on. In some embodiments, when the first controller 104 transmits the first trigger signal S1, the counter 108 may be reset at the same time to prevent the counter 108 from overflowing. It should be noted that the pixel path delay from Pab to Lb is Figure 2 From the circuit diagram embodiment of the pixel unit, it includes the sum of the delay of the AND gate Aab and the delay from the output of the AND gate Aab to Lb.

[0037] Figure 41 is a schematic diagram of a second embodiment of a time-of-flight measurement circuit of the present application. The difference between the time-of-flight measurement circuit 400 and the time-of-flight measurement circuit 100 is that the time-to-digital converter 406 of the time-of-flight measurement circuit 400 has a reference register LR compared to the time-to-digital converter 106 of the time-of-flight measurement circuit 100. The reference register LR is coupled to the output ends of the m first buffers of the m pixel units in the nth column of the pixel array 102 and is used to receive the first trigger signal S1. The reference register LR temporarily stores the reference count value of the counter 108 according to the received first trigger signal S1. The purpose of the reference register LR is described as follows.

[0038] Figure 5 is a schematic diagram for explaining the transmission method of the first trigger signal S1 in the time-of-flight measurement circuit 400. Figure 5 In addition to the n*m ​​paths D11~D1n, D21~D2n, D31~D3n, ..., Dm1~Dmn, there are m paths D1R~DmR that do not pass through any pixel unit and directly reach the reference register LR during the downward vertical transmission. Assuming that the paths that do not pass through the pixel unit during the downward vertical transmission will not cause delay, the total path delays T1R~TmR caused by the paths D1R~DmR are all equal and equal to n*first buffer delay TB1. Therefore, the total path delays T1R~TmR caused by the paths D1R~DmR can be obtained by subtracting the first start time count value of the first start time register LS1 from the reference count value temporarily stored in the reference register LR, and then dividing by n to obtain the first buffer delay TB1. Substituting the first buffer delay TB1 into equation (1) can obtain the pixel path delay from Pab to Lb, where a is any integer from 1 to m and b is any integer from 1 to n. Therefore, after the reference register LR is introduced into the flight time measurement circuit 400, the first buffer delay TB1 and the pixel path delay from Pab to Lb can be further obtained.

[0039] Figure 6 Schematic diagram of the third embodiment of the time-of-flight measurement circuit of the present application. The difference between the time-of-flight measurement circuit 600 and the time-of-flight measurement circuit 100 is that each pixel unit in the pixel array 602 of the time-of-flight measurement circuit 600 further includes a second buffer, wherein the second buffer delays the passing signal by a second buffer delay TB2, and each pixel unit outputs the buffer result output by the first buffer or the second buffer in the test mode. In addition, the time-of-flight measurement circuit 600 further adds a second controller 604, and the time-to-digital converter 106 further includes a second start time register LS2.

[0040] Please refer to Figure 6 and Figure 7 , Figure 7is a circuit diagram of pixel units P22', P23', P32' and P33' in the pixel array 602. It should be noted that each pixel unit in the pixel array 602 is the same, so Figure 7 The illustrated pixel units P22', P23', P32' and P33' can also be used to illustrate other pixel units that are not illustrated. Taking the pixel unit P22' as an example, it can be seen that it further includes a first OR gate O22, a second OR gate O22' and an AND gate A22, wherein the first input end of the first OR gate O22 is coupled to the photosensitive sensor D22, and the second input end of the first OR gate O22 is used to receive the test mode enable signal TE from the first controller 104 and the second controller 604, and the test mode enable signal TE is used to indicate that the flight time measurement circuit 100 is currently in the test mode or the general mode. The first input end of the second OR gate O22' is coupled to the output end of the first buffer B22, and the second input end of the second OR gate O22' is coupled to the output end of the second buffer B22'. The first input end of the AND gate A22 is coupled to the output end of the first OR gate O22, and the second input end of the AND gate A22 is coupled to the output end of the second OR gate O22'.

[0041] When the time-of-flight measurement circuit 100 is implemented in hardware, for example, when the time-of-flight measurement circuit 100 is implemented in a chip, on the integrated circuit layout, the second controller 604 is located on the side of the adjacent n-th column pixel unit P1n'-Pmn', and is correspondingly coupled to the input end of the second buffer B11'-Bm1' of the n-th column pixel unit P1n'-Pmn' through the path RS1'-RSm', and the input end of the second buffer of the pixel unit in the x-th row and y-1 column is coupled to the output end of the second buffer of the pixel unit in the x-th row and y-1 column, where x is an integer from 1 to m, and y is an integer from 2 to n. For example, the input end of the second buffer B11'-Bm1' of the 1st column pixel unit P11'-Pm1' is coupled to the output end of the second buffer B12'-Bm2' of the 2nd column pixel unit P12'-Pm2', and so on.

[0042] In the test mode, the second controller 604 can transmit the second trigger signal S2 to any row of pixel units in the pixel array 602. For example, when the second trigger signal S2 is transmitted to the a-th row of pixel units Pan'-Pa1', where a is any integer from 1 to m, the second controller 604 transmits the second trigger signal S2 through the path RSa', and the second trigger signal S2 passes through the second buffers Ban'-Ba1' in the a-th row of pixel units Pan'-Pa1' in sequence, that is, Figure 6After entering each pixel unit Pan'-Pa1', the second trigger signal S2 is output from the output end of each pixel unit Pan'-Pa1' to the input end of the next row of pixel units through the AND gates Aan'-Aa1'. Figure 6 For example, it presents a downward vertical transmission, that is, when a is less than m, the second trigger signal S2 will be output from the output ends of the pixel units Pan'~Pa1' in the a-th row, and then pass through the pixel units in the (a+1)-th row to the m-th row in sequence; when a is equal to m, the second trigger signal S2 will be directly output from the output ends of the pixel units Pmn'~Pm1' in the m-th row to the time-to-digital converter 606 outside the pixel array 102.

[0043] In response to the second trigger signal S2, the registers Ln-L1 respectively store the second count value of the counter 108 based on the second trigger signal S2 received from the n output terminals of the pixel units Pmn-Pm1. That is, when the pixel unit Pmn outputs the second trigger signal S2 to the register Ln, the register Ln will temporarily store the count result of the counter 108 at this time as the second count value. In this embodiment, the counter 108 is also coupled to the second controller 604, and the second controller 604 can reset the counter 108, that is, clear the counter 108 to zero.

[0044] Figure 8 is a schematic diagram for explaining the transmission method of the second trigger signal S2 in the flight time measurement circuit 600. Figure 8 In the example, the second controller 604 transmits the second trigger signal S2 through the path RS1'. The second trigger signal S2 passes through the first row of pixel units P1n'-P11' to the right in sequence, and then passes through the second to mth row of pixel units from the first row of pixel units P1n'-P11' to the bottom in sequence and then outputs to the registers Ln-L1. The second trigger signal S2 passes through n different paths, i.e. D1n'-D11', from leaving the second controller 604 to entering the registers Ln-L1. The total path delays caused by the n paths D1n'-D11' are all different, resulting in different times for the registers Ln-L1 to receive the second trigger signal S2. The corresponding registers Ln-L1 respectively temporarily store the second count values ​​output by the counter 108 at different times, that is, the n second count values ​​temporarily stored by the n registers are also different. Generally speaking, the total path delays caused by the n paths D1n′-D11′ increase in sequence, and therefore, the n second count values ​​temporarily stored in the registers Ln-L1 also increase in sequence.

[0045] The second start time register LS2 is coupled to the input terminals of the m second buffers of the m pixel units P1n'-Pmn' in the nth column. Therefore, when the second controller 604 intends to transmit the second trigger signal S2 to any row of pixel units in the pixel array 602, the second start time register LS2 will be used to receive the second trigger signal S2 and store the second start time count value of the counter 108 according to the received second trigger signal S2. Therefore, the total path delay T1n'-T11' caused by the n paths D1n'-D11' can be obtained by deducting the second start time count value of the second start time register LS2 from the n second count values ​​stored in the registers Ln-L1.

[0046] Therefore, for the pixel units in the 1st row to the mth row in the pixel array 602, the second controller 604 transmits the second trigger signal S2 to the registers Ln~L1 through different paths RS1~RSm, and there are n paths respectively, that is, there are n*m ​​paths D1n'~D11', D2n'~D21', D3n'~D31', ..., Dmn'~Dm1' in total. When the flight time measurement circuit 600 is to be tested, the test mode enable signal TE can be used to control the flight time measurement circuit 600 to enter the test mode, and then for the pixel units in the 1st row to the mth row in the pixel array 602, the second controller 604 transmits the second trigger signal S2 to the registers Ln~L1 through different paths RS1~RSm, and there are n*m ​​paths D1n'~D11', D2n'~D21', D3n'~D31', ..., Dmn'~Dm1' in total. When the flight time measurement circuit 600 is to be tested, the test mode enable signal TE can be used to control the flight time measurement circuit 600 to enter the test mode, and then the flight time measurement circuit 600 can be controlled to enter the test mode. Figure 8 In this way, n*m paths D1n'~D11', D2n'~D21', D3n'~D31', ..., Dmn'~Dm1' are obtained m times. Figure 8 It can be seen that:

[0047] Total path delay Tab' = (n-b+1)*TB2 + delay from Pab' to Lb (2)

[0048] , where a is any integer from 1 to m, and b is any integer from 1 to n. For example, the total path delay T11' caused by the path D11'=n*second buffer delay TB2+pixel path delay from pixel unit P11' to register L1, the total path delay TD12 caused by the path D12'=(n-1)*second buffer delay TB2+pixel path delay from pixel unit P12' to register L2, and so on. In some embodiments, when the second controller 604 transmits the second trigger signal S2, the counter 108 may be reset at the same time to prevent the counter 108 from overflowing.

[0049] In addition, when the first controller 104 is used to transmit the first trigger signal S1, equation (1) can be rewritten as:

[0050] Tab = b*TB1 + pixel path delay from Pab' to Lb (3)

[0051] By using the first controller 104 together with the second controller 604, the flight time measurement circuit 400 can further obtain the first buffer delay TB1, the second buffer delay TB2 and the pixel path delay from Pab' to Lb. Fig. 9 .

[0052] Fig. 9 In, use:

[0053] Total path delay T12 of path D12 = 2*TB1 + pixel path delay from P12' to L2 (4)

[0054] Total path delay T1n of path D1n = n*TB1 + pixel path delay from P1n' to Ln (5)

[0055] Total path delay T12' of path D12' = (n-1)*TB2 + pixel path delay from P12' to L2 (6)

[0056] Total path delay T1n' of path D1n' = 1*TB2 + pixel path delay from P1n' to Ln (7)

[0057] When there are four unknowns in total (first buffer delay TB1, second buffer delay TB2, pixel path delay from P12' to L2, pixel path delay from P1n' to Ln), the four measured total path delays (T12, T1n, T12', T1n') obtained by using four paths (D12, D1n, D12', D1n') are substituted into equations (4) to (7), and the four unknowns can be solved. Therefore, Fig. 9 Examples and Figure 5 The embodiments have the same effect.

[0058] The present application also provides a chip, which includes the time-of-flight measurement circuit 100 / 400 / 600. The present application also provides an electronic device, which includes the time-of-flight measurement circuit 100 / 400 / 600 or the chip. The electronic device can be any electronic device such as a smart phone, a personal digital assistant, a handheld computer system, a tablet computer, or a digital camera.

[0059] The flight time measurement circuit 100 / 400 / 600 of the present application can obtain the pixel path delay of the first control circuit 104 and / or the second control circuit 604 through the pixel array 102 / 602 to the time digital converter 106 / 406 / 606 in the test mode, and can estimate a pixel path delay for each path D11~D1n, D21~D2n, D31~D3n, ..., Dm1~Dmn passing through each pixel unit, which is more accurate than the general practice. When used for the correction of the flight time measurement circuit 100 / 400 / 600 when measuring the flight time in the general mode, the accuracy of the flight time measurement can be improved. Figure 5 For example, when measuring the flight time in the general mode, when RS2 is set to 1 (high logic level), it means that the second row of pixel units P21~P2n are selected for reading. When the photosensor D21 in the pixel unit P21 senses the reflected photons, the sensing result is transmitted vertically downward through the OR gate O21 and the AND gate A23, and reaches the register L1 through the pixel units P31~Pm1. The delay during this period is not the flight time, but an additional delay. The present application can pre-estimate the delay during this period, which is close to Figure 5 and Fig. 9 The pixel path delay from P21 to Lb calculated by the embodiment of Figure 5 and Fig. 9 The pixel path delay from P21 to Lb calculated in the embodiment does not include the delay of the OR gate O21). In this way, the accuracy of the flight time can be further improved by subtracting the pixel path delay from P21 to Lb from the flight time obtained by the time-to-digital converter.

[0060] In addition, each embodiment of the control method of the above-mentioned flight time measurement circuit in the test mode and the general mode can be performed using a controller (not shown in the figure), and the controller can be located inside or outside the flight time measurement circuit, or partially inside the flight time measurement circuit and partially outside the flight time measurement circuit.

[0061] The above description briefly presents the features of certain embodiments of the present application, so that those with ordinary knowledge in the technical field to which the present application belongs can more fully understand the various aspects of the present disclosure. Those with ordinary knowledge in the technical field to which the present application belongs should understand that they can easily use the present disclosure as a basis to design or change other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the present application belongs should understand that these equal embodiments still belong to the spirit and scope of the present disclosure, and they can be variously changed, replaced and modified without departing from the spirit and scope of the present disclosure.

Claims

1. A time-of-flight measurement circuit, characterized in that: include: A pixel array, comprising m rows×n columns of pixel units, wherein m and n are positive integers, and each of the pixel units comprises: Light sensor; and a first buffer, wherein the first buffer delays the passing signal by a time equal to a first buffer delay; wherein the pixel unit outputs the sensing result of the photosensitive sensor in a normal mode, and the pixel unit outputs the buffering result output by the first buffer in a test mode; a first controller coupled to an input terminal of the first buffer of each of the pixel units in the 1st column, and an input terminal of the first buffer of the pixel unit in the xth row and yth column is coupled to an output terminal of the first buffer of the pixel unit in the xth row and y-1th column, x is an integer from 1 to m, and y is an integer from 2 to n, wherein in the test mode, the first controller transmits a first trigger signal, so that the first trigger signal sequentially passes through the first buffers of the pixel units in the 1st to yth columns of the xth row, and when x is less than m, the first trigger signal is further output from the output terminal of the first buffer of the pixel unit in the xth row and yth column through the output terminal of the pixel unit in the xth row and yth column to the pixel unit in the (x+1)th row and yth column, until reaching the pixel unit in the mth row and yth column; and Time to digital converter, including: A counter, coupled to the first controller, and counting according to a reference clock; n registers, including the 1st register to the nth register, correspondingly coupled to the n output terminals of the pixel units in the 1st to the nth columns of the mth row, wherein the yth register temporarily stores the first count value of the counter based on the first trigger signal received from the output terminal of the pixel unit in the mth row and the yth column; and The first start time register is coupled to the input terminals of the m first buffers of the m pixel units in the first column and is used to receive the first trigger signal. The first start time register temporarily stores the first start time count value of the counter according to the received first trigger signal.

2. The time-of-flight measurement circuit as claimed in claim 1, wherein: Each of the pixel units further comprises: an OR gate, wherein a first input terminal of the OR gate is coupled to the photosensor, and a second input terminal of the OR gate is used to receive a test mode enable signal from the first controller, wherein the test mode enable signal is used to indicate that the time-of-flight measurement circuit is currently in the test mode or the normal mode; and An AND gate, wherein a first input terminal of the AND gate is coupled to the output terminal of the OR gate, and a second input terminal of the AND gate is coupled to the output terminal of the first buffer.

3. The time-of-flight measurement circuit according to claim 1 or 2, wherein: The time-to-digital converter further comprises: The reference register is coupled to the output terminals of the m first buffers of the m pixel units in the nth column and is used to receive the first trigger signal. The reference register temporarily stores the reference count value of the counter according to the received first trigger signal.

4. The time-of-flight measurement circuit as claimed in claim 1, wherein: Each of the pixel units further comprises: a second buffer, wherein the second buffer delays the passing signal by a second buffer delay, and the pixel unit outputs a buffer result output by the first buffer or the second buffer in the test mode; The time-of-flight measurement circuit further comprises: a second controller coupled to an input terminal of the second buffer of each of the pixel units in the nth column, and an input terminal of the second buffer of the pixel unit in the xth row and the y-1th column is coupled to an output terminal of the second buffer of the pixel unit in the xth row and the yth column, wherein in the test mode, the second controller transmits a second trigger signal so that the second trigger signal sequentially passes through the second buffers of the pixel units in the xth row and the nth column to the yth column, respectively, and when x is less than m, the second trigger signal is further output from the output terminal of the second buffer of the pixel unit in the xth row and the yth column to the pixel unit in the (x+1)th row and the yth column via the output terminal of the pixel unit in the xth row and the yth column, until reaching the pixel unit in the mth row and the yth column; The counter is further coupled to the second controller, and the time-to-digital converter further comprises: A second start time register is coupled to the input ends of the m second buffers of the m pixel units in the nth column and is used to receive the second trigger signal. The second start time register temporarily stores the second start time count value of the counter according to the received second trigger signal, wherein the n registers temporarily store the second count value of the counter based on the second trigger signal received from the output end of each of the pixel units in the mth row.

5. The time-of-flight measurement circuit as claimed in claim 4, wherein: Each of the pixel units further comprises: a first OR gate, wherein a first input terminal of the first OR gate is coupled to the photosensor, and a second input terminal of the first OR gate is used to receive a test mode enable signal from the first controller, wherein the test mode enable signal is used to indicate that the time-of-flight measurement circuit is currently in the test mode or the normal mode; a second OR gate, wherein a first input terminal of the second OR gate is coupled to the output terminal of the first buffer, and a second input terminal of the second OR gate is coupled to the output terminal of the second buffer; and An AND gate, wherein a first input terminal of the AND gate is coupled to an output terminal of the first OR gate, and a second input terminal of the AND gate is coupled to an output terminal of the second OR gate.

6. A control method for the time-of-flight measurement circuit according to claim 3, characterized in that: include: Controlling the flight time measurement circuit to enter the test mode; The first controller is used to transmit the first trigger signal at a first time point, so that the first trigger signal passes through the first buffer of each pixel unit in the pixel units of the xth row and the first column to the xth row and the nth column in sequence, so as to obtain: The first starting time count value; The first count value of the yth buffer corresponds to the sum of y first buffer delays and the pixel path delay from the pixel unit in the xth row and yth column to the yth buffer; as well as The reference count value of the reference register corresponds to m first buffer delays; Obtaining the first buffer delay according to the first start time count value and the reference count value; Obtaining a total path delay of the first trigger signal after passing through the first buffers in the pixel units in the xth row, 1st to yth column, and then passing through the pixel units in the yth column, xth to mth row to the yth register according to the first start time count value and the first count value; and The pixel path delay from the pixel unit in the xth row and yth column to the yth register is obtained according to the first buffer delay and the total path delay.

7. The control method according to claim 6, characterized in that: Also includes: The counter is reset at the first time point using the first controller.

8. The control method according to claim 6, characterized in that: Also includes: Controlling the time-of-flight measurement circuit to enter the general mode, so that the sensing result of the photosensor of the pixel unit in the xth row and yth column outputs a corresponding time-of-flight signal through the yth register; as well as A corrected time-of-flight signal is obtained according to the time-of-flight signal and a pixel path delay from the pixel unit in the xth row and the yth column to the yth register.

9. A control method for the time-of-flight measurement circuit according to claim 4 or 5, characterized in that: include: Controlling the flight time measurement circuit to enter the test mode; The first controller is used to transmit the first trigger signal at a first time point, so that the first trigger signal passes through the first buffer of each pixel unit in the pixel units of the xth row and the first column to the xth row and the nth column in sequence, so as to obtain: The first starting time count value; The first count value of the yth buffer corresponds to the sum of y first buffer delays and the pixel path delay from the pixel unit in the xth row and yth column to the yth buffer; as well as The first count value of the zth register corresponds to the sum of z first buffer delays and the pixel path delay from the pixel unit in the xth row and zth column to the zth register, wherein z is an integer from 1 to n, and y and z are different integers; The second controller is used to transmit the second trigger signal at a second time point, so that the second trigger signal sequentially passes through the second buffer of each pixel unit in the pixel units of the xth row and the nth column to the xth row and the 1st column, so as to obtain: the second starting time count value; The second count value of the yth register corresponds to the sum of (n-y+1) second buffer delays and the pixel path delay from the pixel unit in the xth row and yth column to the yth register; and The second count value of the zth buffer corresponds to the sum of (n-y+1) second buffer delays and the pixel path delay from the pixel unit in the xth row and the zth column to the zth buffer; Obtaining, according to the first start time count value, the first count value of the yth register, and the first count value of the zth register, a first total path delay of the first trigger signal after passing through the first buffers of the pixel units in the xth row, the first to the yth column, and then passing through the pixel units in the yth column, the xth to the mth row to the yth register, and obtaining a second total path delay of the first trigger signal after passing through the first buffers of the pixel units in the xth row, the first to the zth column, and then passing through the pixel units in the zth column, the xth to the mth row to the zth register; According to the second start time count value, the second count value of the yth register and the second count value of the zth register, a third total path delay of the second trigger signal after passing through the respective second buffers in the pixel units in the xth row, nth column, yth column, and then passing through the pixel units in the yth column, xth row, mth row, to the yth register is obtained, and a fourth total path delay of the second trigger signal after passing through the respective second buffers in the pixel units in the xth row, nth column, yth column, and then passing through the pixel units in the zth column, xth row, mth row, to the zth register is obtained; as well as The first buffer delay, the second buffer delay, the pixel path delay from the pixel unit in the xth row and yth column to the yth register, and the pixel path delay from the pixel unit in the xth row and zth column to the zth register are obtained according to the first total path delay, the second total path delay, the third total path delay, and the fourth total path delay.

10. The control method according to claim 9, characterized in that: Also includes: resetting the counter at the first time point using the first controller; as well as The counter is reset at the second time point using the second controller.

11. The control method according to claim 9, characterized in that: Also includes: Controlling the time-of-flight measurement circuit to enter the general mode, so that the sensing result of the photosensor of the pixel unit in the xth row and yth column outputs a corresponding first time-of-flight signal through the yth register, and the sensing result of the photosensor of the pixel unit in the xth row and zth column outputs a corresponding second time-of-flight signal through the zth register; Obtaining a corrected first time-of-flight signal according to the first time-of-flight signal and a pixel path delay from the pixel unit in the xth row and the yth column to the yth register; as well as A corrected second flight time signal is obtained according to the second flight time signal and a pixel path delay from the pixel unit in the xth row and the zth column to the zth register.

12. An electronic device, characterized in that: include: The time-of-flight measurement circuit as claimed in claim 1.

13. An electronic device, characterized in that: include: Time-of-flight measurement circuit, including: A pixel array, comprising m rows×n columns of pixel units, wherein m and n are positive integers, and each of the pixel units comprises: Light sensor; and a first buffer, wherein the first buffer delays the passing trigger signal by a time equal to a first buffer delay; wherein the pixel unit outputs the sensing result of the photosensor in a normal mode, and the pixel unit outputs the buffering result of the trigger signal output by the first buffer in a test mode; and Controller for: Controlling the time-of-flight measurement circuit to enter the test mode and transmitting the trigger signal to the pixel array; Controlling the time-of-flight measurement circuit to enter the general mode, so that the sensing result of the photosensor of the pixel unit in the xth row and yth column outputs a corresponding first time-of-flight signal through the yth register, and the sensing result of the photosensor of the pixel unit in the xth row and zth column outputs a corresponding second time-of-flight signal through the zth register; Obtaining a corrected first time-of-flight signal according to the first time-of-flight signal and a pixel path delay from the pixel unit in the xth row and yth column to the yth register; and A corrected second flight time signal is obtained based on the second flight time signal and the pixel path delay from the pixel unit in the x-th row and z-th column to the z-th register, wherein the pixel path delay from the pixel unit in the x-th row and y-th column to the y-th register and the pixel path delay from the pixel unit in the x-th row and z-th column to the z-th register are measured by the controller controlling the flight time measurement circuit in the test mode.

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