Module FPGA verification method and system for chip video decoding IP
The module FPGA verification method and system facilitate early detection of errors in multi-channel and multi-standard video decoding IP cores by enabling parallel verification without an operating system, thus reducing verification cycles and improving efficiency.
Patent Information
- Application Number
- CN202111572339.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-21
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2041-12-21
AI Technical Summary
Current FPGA verification methods for video decoding IP cores are inefficient for multi-channel and multi-standard scenarios, leading to increased chip verification cycles due to separate and independent verifications, which do not detect coupling errors until the system-level stage, and require managing multiple sets of codes and firmware, resulting in extended development times.
A module FPGA verification method and system that enables multi-channel and multi-standard parallel verification without an operating system, utilizing a verification synchronization management unit to configure decoding paths and result comparison units for simultaneous decoding and comparison of multiple video streams across different standards and cores.
This approach allows for early detection of coupling errors in the module-level verification stage, significantly shortening the verification cycle and improving efficiency by optimizing the verification process for multiple channels and standards.
Smart Images
Figure CN114282466B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a module FPGA verification method and system for a chip video decoding IP. Background Art
[0002] In modern digital integrated circuit design, chip IP core verification is becoming increasingly important. The verification of the video decoding IP core (also known as IP or IP module) belongs to the front-end verification in the video decoding chip design process. The success or failure of IP core verification directly affects the video decoding core test performance. At present, the video decoding IP core verification process can be mainly divided into three stages: the RTL (Register-Transfer-Level) simulation verification stage of the IP core, the module FPGA (Field-Programmable Gate Array) verification stage of the IP core, and the system driver verification stage of the IP core. The first two stages belong to separate module-level verification (also known as module-level functional verification), and the third stage belongs to the system-level verification of the running operating system (also known as chip-level functional verification).
[0003] For the second stage - the FPGA verification stage of the IP core, the traditional verification method is to verify the decoding capability of a single decoding IP core for a certain video standard separately without an operating system. The verification of different decoding IP cores and different decoding standards is performed separately and independently. The above traditional verification method has the following defects:
[0004] 1) The verification method is based on a single channel and a single standard. A set of PC codes and a set of video decoding firmware only support a single channel and a single standard video. At the same time, only one decoding IP core verifies a single video decoding standard, which makes it difficult to achieve parallel verification of multi-channel and multi-standard video decoding. Since each video decoding standard is verified using an independent verification environment and code, multiple video decoding standard verifications require the maintenance of multiple sets of code for separate verifications. For multi-channel and multi-standard video decoding verification scenarios, the current industry practice is to set up multiple sets of video decoding firmware and multiple sets of PC codes to run multiple times in a time-sharing manner, which significantly increases the chip tape-out cycle and the entire development cycle of the chip product. In addition, since it is necessary to manage multiple sets of video decoding firmware, multiple sets of PC codes, and multiple sets of standard C codes, the management efficiency of components such as standard C code, video decoding firmware, interaction between video decoding firmware and hardware, and PC code is reduced.
[0005] 2) In the verification scenario of multi-channel and multi-standard decoding, a decoding IP core may cause decoding errors due to the front-to-back coupling between different video standard decoding. Moreover, multiple decoding IP cores in the chip may also cause parallel decoding errors due to coupling when decoding simultaneously. The above problems are difficult to be discovered in the second stage based on a single channel and a single standard, and often need to be discovered in the third stage - the system-level verification stage of running the operating system. Since hardware problems found at any stage need to return to the first stage and restart the iterative verification process, the above verification method will undoubtedly increase the iteration time, resulting in an extension of the chip verification cycle, making the project verification cycle difficult to control. Obviously, if the above problems can be discovered in the second stage, it will help shorten the entire verification cycle.
[0006] On the other hand, as people's requirements for chip functions become higher and higher, the complexity of chip design is also increasing. The traditional IP core FPGA verification system that only supports single-channel single-standard is difficult to handle the complex mode of multi-decoding IP core parallel verification and multi-standard parallel verification, and cannot meet the current chip video decoding verification needs. Therefore, the FPGA verification system that can support multi-standard parallel verification of multiple video decoding IP cores has become one of the important research directions.
[0007] In summary, how to provide a FPGA parallel verification solution that supports multiple video decoding IP cores without an operating system so as to detect coupling errors between different video standards and different decoding IP cores as early as possible and effectively shorten the verification cycle is a technical problem that needs to be solved urgently in chip verification. Summary of the invention
[0008] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a module FPGA verification method and system for a chip video decoding IP. The present invention can realize multi-channel and multi-standard parallel FPGA verification of a decoding IP core without an operating system, and further can realize multi-core multi-channel and multi-standard parallel verification, so that problems caused by multi-core coupling and multi-standard coupling can be discovered in advance in the module FPGA verification stage (also called module-level functional verification stage) of the video decoding IP, shortening the verification cycle and improving the verification speed.
[0009] To achieve the above objectives, the present invention provides the following technical solutions:
[0010] A module FPGA verification method for a chip video decoding IP is used for IP core verification without an operating system, and includes the following steps:
[0011] Importing the video decoding firmware of the decoding IP core into the FPGA verification platform, wherein the video decoding firmware is used to initialize decoding-related parameters and configure the initial state of the decoding hardware;
[0012] The verification synchronization management unit configures the number of parallel decoding verification paths of each decoding IP core and the video standard parameter information of each path, and initializes the result comparison unit on the PC according to the above configuration information. The number of paths is an integer greater than or equal to 2, and different video decoding paths correspond to different video standards;
[0013] Initiate multi-channel communication between the result comparison unit and the video decoding firmware, for each multi-channel decoding verification video stream of the decoding IP core, the video decoding firmware interacts with the decoding hardware of each channel to perform multi-channel multi-standard parallel decoding of multiple video streams of different video standards, and during the decoding process, the video decoding firmware transmits the decoded frame data of each video stream to the result comparison unit on the PC;
[0014] The result comparison unit compares the received decoded frame data of each video stream with the standard data corresponding to the decoded frame to verify the decoding result.
[0015] Furthermore, the steps for multi-channel and multi-standard parallel verification of a single decoding IP core are as follows:
[0016] Input multiple video ES streams into multiple ES stream buffers on the FPGA verification platform;
[0017] The video decoding firmware configures the number of decoding firmware channels k and the video standard format type of each channel according to the configuration parameter information transmitted by the result comparison unit to complete initialization; k is an integer greater than or equal to 2;
[0018] The video decoding firmware configures decoding parameters starting from the 0th frame of the 0th ES stream, parses the upper-layer syntax information of the 0th ES stream, configures the relevant syntax information into the corresponding registers of the hardware, and then starts the decoding IP core to start on-chip decoding, and the decoding IP core completes the decoding of all slices of the 0th frame of the 0th ES stream; the decoding firmware transmits the 0th decoded frame data of the 0th ES stream obtained by decoding to the result comparison unit on the PC, and the result comparison unit generates the standard data of the decoded frame through the built-in video standard C code, and then compares the aforementioned 0th decoded frame data of the 0th ES stream with the standard data to verify the decoding result; according to the same method, the video decoding firmware completes the decoding of the 0th frame of the jth ES stream, where j=1, 2, ..., k-1, and transmits the 0th decoded frame of the jth ES stream obtained by decoding to the result comparison unit for comparison, so as to complete the comparison of the 0th decoded frame data of the kth ES stream with the standard data;
[0019] According to the decoding verification method for the 0th decoded frame data of the aforementioned k-way ES stream, the 1st decoded frame data of the j-th ES stream is decoded in sequence and transmitted to the result comparison unit for comparison, wherein j=0, 1..., k-1, so as to complete the comparison between the 1st decoded frame data of the k-way ES stream and the standard data; and so on, according to the same method, the comparison between the n-1th decoded frame data of the k-way ES stream and the standard data is completed in sequence, wherein n represents the number of image frames contained in the video ES stream, and n is an integer greater than or equal to 2.
[0020] Furthermore, for a video decoding chip including multiple decoding IP cores, upon receiving a multi-core parallel verification request of the multiple decoding IP cores, the multi-core parallel verification is performed in the following manner:
[0021] Collect the decoding IP core information and verification task information of each decoding IP core required for parallel verification contained in the request, configure the number m of decoding IP cores to be verified in parallel, the number of parallel decoding verification paths for each decoding IP core and the video standard parameter information of each path, and the synchronization mechanism parameter information of the decoding IP core, where m is an integer greater than or equal to 2, and transmit the above-mentioned configuration information to the video decoding firmware;
[0022] The verification task information of each decoding IP core is transmitted to the video decoding firmware, and the video decoding firmware simultaneously controls the m decoding IP cores to perform multi-core parallel decoding, and controls the multiple video streams of different video standards inside each decoding IP core to perform the aforementioned multi-channel multi-standard parallel decoding; according to the aforementioned synchronization mechanism parameters, the decoding results of each decoding IP core are collected in parallel and sent to the result comparison unit on the PC;
[0023] The result comparison unit compares the decoded frame data of each video stream received by each decoding IP core with the standard data corresponding to the decoded frame to verify the decoding result.
[0024] Furthermore, the specific steps for parallel verification of multiple decoding IP cores are as follows:
[0025] The video decoding firmware configures the decoding verification path number k_i of each decoding IP core vdec_i and the video standard format type of each path according to the internal parameters and synchronization mechanism parameter information of each decoding IP core transmitted by the result comparison unit, and completes the initialization, where i=0, 1, ..., m-1, and there are m decoding IP cores in total;
[0026] According to the synchronization mechanism parameters of the decoding IP core and the verification task information of each decoding IP core, the video decoding firmware controls the m decoding IP cores to simultaneously perform parallel decoding of multiple internal video streams of different video standards; and according to the synchronization mechanism parameters of the decoding IP core, the video decoding firmware transmits the internal k_i channels of each decoded frame data of the i-th decoding IP core vdec_i in parallel to the result comparison unit, where i=0, 1, ..., m-1;
[0027] The result comparison unit is used to receive the decoded frame data of each channel from each decoding IP core, and to perform parallel comparison on the decoded frame data of each channel from m decoding IP cores at the same time.
[0028] Further, the steps of controlling m decoding IP cores to simultaneously decode multiple internal video streams of different video standards are as follows:
[0029] The video decoding firmware starts the decoding IP core vdec_0, and decodes the decoded frame data of the k_0 path of the decoding IP core vdec_0 in parallel; at the same time, the video decoding firmware starts the decoding IP core vdec_1, and decodes the decoded frame data of the k_1 path of the decoding IP core vdec_1 in parallel. Similarly, the video decoding firmware starts the decoding IP core vdec_m-1 at the same time, and decodes the decoded frame data of the k_m-1 path of the decoding IP core vdec_m-1 in parallel.
[0030] Further, the steps of performing parallel comparison on the multi-channel decoded frame data of the m decoding IP cores are:
[0031] Compare the k_0-way decoded frame data inside the decoding IP core vdec_0 with the corresponding standard data, and perform k_0-way parallel verification; at the same time, compare the k_1-way decoded frame data inside the decoding IP core vdec_1 with the corresponding standard data, and perform k_1-way parallel verification; and so on, compare the k_m-1-way decoded frame data inside the decoding IP core vdec_m-1 with the corresponding standard data, and perform k_m-1-way parallel verification.
[0032] Further, the result comparison unit has a video decoding hardware submodule verification mode and a decoding frame verification mode;
[0033] In the video decoding hardware submodule verification mode, the result comparison unit generates a test vector of the hardware submodule based on the built-in video standard C code, and the test vector can be used for RTL simulation verification of the decoding IP;
[0034] In the decoding frame verification mode, the result comparison unit communicates with the video decoding firmware and generates standard data for comparison of each decoding frame. According to the synchronization mechanism parameters, the decoding frame data generated by multiple decoding IP cores are compared with the standard data to perform multi-core multi-channel parallel verification. This parallel verification can be used for module FPGA verification of the decoding IP.
[0035] The present invention also provides a module FPGA verification system for chip video decoding IP, which is used for IP core verification without an operating system, and includes an FPGA verification platform, a PC, and a verification synchronization management unit corresponding to the FPGA verification platform and the PC; the FPGA verification platform is provided with a video decoding firmware of the decoding IP core, and the video decoding firmware is used to initialize decoding-related parameters and configure the initial state of the decoding hardware; the PC is provided with a result comparison unit, and the result comparison unit can perform multi-channel communication with the aforementioned video decoding firmware;
[0036] The verification synchronization management unit is configured as follows: for each decoding IP core in the chip, configure the number of parallel decoding verification paths and video standard parameter information of each path of the decoding IP core, initialize the result comparison unit on the PC according to the above-mentioned configured information, and start multi-path communication between the result comparison unit and the video decoding firmware, wherein the number of paths is an integer greater than or equal to 2, and different video decoding paths correspond to different video standards; and for each multi-path decoding verification video stream of the decoding IP core, interact with the decoding hardware of each path through the aforementioned video decoding firmware to perform multi-path multi-standard parallel verification of multiple video streams of different video standards, and in the decoding process, transmit the decoded frame data of each video stream to the result comparison unit on the PC through the video decoding firmware;
[0037] The result comparison unit is used to compare the received decoded frame data of each video stream with the standard data corresponding to the decoded frame to verify the decoding result.
[0038] Further, the verification synchronization management unit is also configured to: upon receiving a multi-core parallel verification request for multiple decoding IP cores, configure the number m of decoding IP cores to be verified in parallel, the number of parallel decoding verification paths for each decoding IP core and the video standard parameter information for each path, and the synchronization mechanism parameter information of the decoding IP core according to the decoding IP core information to be verified in parallel contained in the request, wherein m is an integer greater than or equal to 2, and transmit the aforementioned configured information to the video decoding firmware; and, transmit the verification task information of each decoding IP core to the video decoding firmware, and simultaneously run m decoding IP cores for multi-core parallel decoding through the video decoding firmware, and perform the aforementioned multi-path multi-standard parallel verification through the multiple video streams of different video standards inside each decoding IP core; and, according to the aforementioned synchronization mechanism parameters, collect the decoding results of each decoding IP core in parallel and send them to the result comparison unit on the PC;
[0039] The result comparison unit is used to compare the decoded frame data of each video stream received by each decoding IP core with the standard data corresponding to the decoded frame to verify the decoding result.
[0040] Further, the result comparison unit has a video decoding hardware submodule verification mode and a decoding frame verification mode;
[0041] In the video decoding hardware submodule verification mode, the result comparison unit generates a test vector of the hardware submodule based on the built-in video standard C code, and the test vector can be used for RTL simulation verification of the decoding IP;
[0042] In the decoding frame verification mode, the result comparison unit communicates with the video decoding firmware and generates standard data for comparison of each decoding frame. According to the synchronization mechanism parameters, the decoding frame data generated by multiple decoding IP cores are compared with the standard data to perform multi-core multi-channel parallel verification. This parallel verification can be used for module FPGA verification of the decoding IP.
[0043] Due to the adoption of the above technical scheme, the present invention has the following advantages and positive effects compared with the prior art, as an example: the present invention can realize multi-channel and multi-standard parallel FPGA verification of decoding IP cores without an operating system, and can further realize multi-core multi-channel and multi-standard parallel verification, so that problems caused by multi-core coupling and multi-standard coupling can be discovered in advance in the module FPGA verification stage (also called the module-level functional verification stage) of the video decoding IP, shortening the verification cycle and improving the verification speed. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Figure 1 This is a structural diagram of the connection between the verification synchronization management unit, the FPGA verification platform and the PC provided in an embodiment of the present invention.
[0045] Figure 2 An example diagram of a multi-channel and multi-standard parallel verification process for a decoding IP core without an operating system provided in an embodiment of the present invention.
[0046] Figure 3 An example diagram of a process for parallel verification of multiple decoding IP cores without an operating system provided by an embodiment of the present invention.
[0047] Figure 4 A schematic diagram of multi-mode switching of a PC-side result comparison unit provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0048] The following is a further detailed description of the module FPGA verification method and system of the chip video decoding IP disclosed in the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be considered isolated, and they can be combined with each other to achieve better technical effects. In the drawings of the following embodiments, the same reference numerals appearing in each drawing represent the same features or components, which can be applied to different embodiments. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0049] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the invention. Any modification of the structure, change of the proportion relationship or adjustment of the size should fall within the scope of the technical content disclosed by the invention without affecting the effects and purposes that can be achieved by the invention. The scope of the preferred embodiments of the present invention includes other implementations, in which the functions can be performed in a substantially simultaneous manner or in a reverse order according to the functions involved, which should be understood by those skilled in the art of the technical field to which the embodiments of the present invention belong.
[0050] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.
[0051] Example
[0052] The present invention proposes a module FPGA verification system for a chip video decoding IP, which can realize multi-channel and multi-standard parallel FPGA verification of a decoding IP core without an operating system.
[0053] The module FPGA verification system includes an FPGA verification platform, a PC, and a verification synchronization management unit corresponding to the FPGA verification platform and the PC. Figure 1 As shown. The FPGA verification platform is provided with a video decoding firmware of a decoding IP core. The video decoding firmware is used to initialize decoding-related parameters and configure the initial state of the decoding hardware. The PC is provided with a result comparison unit, which can perform multi-channel communication with the aforementioned video decoding firmware.
[0054] The method for performing multi-channel and multi-standard parallel verification of a decoding IP core using the above system comprises the following steps:
[0055] S100, importing the video decoding firmware of the decoding IP core into the FPGA verification platform.
[0056] S200, configure the number of parallel decoding verification paths and the video standard parameter information of each path of each decoding IP core through the verification synchronization management unit, and initialize the result comparison unit on the PC according to the above configuration information. The number of paths is an integer greater than or equal to 2, and different video decoding paths correspond to different video standards.
[0057] S300, start the multi-channel communication between the result comparison unit and the video decoding firmware. For each multi-channel decoding verification video stream of each decoding IP core, the video decoding firmware interacts with the decoding hardware of each channel to perform multi-channel multi-standard parallel decoding of multiple video streams with different video standards. During the decoding process, the video decoding firmware transmits the decoded frame data of each video stream to the result comparison unit on the PC.
[0058] S400, a result comparison unit compares the received decoded frame data of each video stream with the standard data corresponding to the decoded frame to verify the decoding result.
[0059] In this embodiment, the steps of multi-channel multi-standard parallel verification of a single decoding IP core are as follows:
[0060] On the FPGA verification platform, multiple video ES streams are input into the multiple ES stream buffer; the video decoding firmware configures the number of decoding firmware channels k and the video standard format type of each channel according to the configuration parameter information transmitted by the result comparison unit to complete the initialization; the k is an integer greater than or equal to 2; the video decoding firmware configures the decoding parameters starting from the 0th frame of the 0th ES stream, parses the upper-layer syntax information of the 0th ES stream, configures the relevant syntax information into the corresponding registers of the hardware, and then starts the decoding IP core to start on-chip decoding, and the decoding IP core completes the decoding of all slices of the 0th frame of the 0th ES stream; the decoding firmware transmits the 0th decoded frame data of the 0th ES stream obtained by decoding to the result comparison unit on the PC, and the result comparison unit generates the standard data of the decoded frame through its own video standard C code, and compares the aforementioned 0th decoded frame data of the 0th ES stream and the standard The standard data is compared to verify the decoding result; according to the same method, the video decoding firmware completes the decoding of the 0th frame of the jth ES stream, where j=1, 2, ..., k-1, and transmits the 0th decoded frame of the jth ES stream obtained by decoding to the result comparison unit for comparison, so as to complete the comparison of the 0th decoded frame data of the kth ES stream with the standard data; according to the decoding verification method of the 0th decoded frame data of the kth ES stream, the 1st decoded frame data of the jth ES stream is decoded in sequence and transmitted to the result comparison unit for comparison, where j=0, 1..., k-1, so as to complete the comparison of the 1st decoded frame data of the kth ES stream with the standard data; and so on, according to the same method, the comparison of the n-1th decoded frame data of the kth ES stream with the standard data is completed in sequence, where n represents the number of image frames contained in the video ES stream, and n is an integer greater than or equal to 2.
[0061] Combine the following Figure 2 Taking the total number of channels as k (k is greater than 4) and the specific video standards for the first 4 channels as an example, the multi-channel and multi-standard parallel verification process of a single decoding IP core is described in detail.
[0062] As an example but not a limitation, the first four decoding channels are channel 0, channel 1, channel 2 and channel 3, and the video standards of channel 0, channel 1, channel 2 and channel 3 are AVS, VC1, H.264 and HEVC respectively. At this time, the multi-channel and multi-standard parallel verification method of the single decoding IP core without an operating system is as follows.
[0063] 1) Initialize the FPGA verification platform and import the video decoding firmware into the FPGA verification platform.
[0064] 2) Verify the synchronization management unit configuration parameters such as the number of channels k and the standard format of each video channel (the video standards from 0 to 3 are avs, vc1, h.264, hevc, respectively, initialize the result comparison unit on the PC side, start multi-channel communication between the result comparison unit and the video decoding firmware, and input the multi-channel ES streams into the multi-channel ES stream buffer on the platform.
[0065] 3) The video decoding firmware receives the parameters transmitted by the result comparison unit, automatically configures the video decoding firmware channel number k and the standard format of each channel video, and then initializes. The video decoding firmware configures the decoding parameters starting from the 0th frame of the 0th avs stream, parses the upper-layer syntax information of the avs stream, configures the relevant syntax information to the corresponding registers of the hardware, and then starts the video decoding IP core to start the on-chip decoding. The video decoding IP core completes the decoding of all slices of the 0th frame of the 0th avs stream.
[0066] 4) The video decoding firmware transmits the 0th decoded frame data of the 0th avs stream to the result comparison unit. The result comparison unit comes with a standard C code that can generate decoded frame standard data and compare the 0th decoded frame data with the standard data.
[0067] 5) In the same way, the 0th decoded frame data of the 1st vc1 stream, the 0th decoded frame data of the 2nd h.264 stream, the 0th decoded frame data of the 3rd hevc stream, ..., until the 0th decoded frame data of the k-1th stream is transmitted to the result comparison unit to compare the 0th decoded frame data with the standard data.
[0068] 6) According to the same method, the first decoded frame data of the 0th avs stream, the first decoded frame data of the 1st vc1 stream, the first decoded frame data of the 2nd h.264 stream, the first decoded frame data of the 3rd hevc stream, ..., until the first decoded frame data of the k-1th stream are transmitted to the result comparison unit in sequence to compare the first decoded frame data with the standard data.
[0069] 7) According to the same method, the second decoded frame data of the 0th avs stream, the second decoded frame data of the 1st vc1 stream, the second decoded frame data of the 2nd h.264 stream, the second decoded frame data of the 3rd hevc stream, ..., until the second decoded frame data of the k-1th stream are transmitted to the result comparison unit in sequence to compare the second decoded frame data with the standard data.
[0070] 8) According to the same method, the n-1th decoded frame data of the 0th avs stream, the n-1th decoded frame data of the 1st vc1 stream, the n-1th decoded frame data of the 2nd h.264 stream, the n-1th decoded frame data of the 3rd hevc stream, ..., until the n-1th decoded frame data of the k-1th stream are transmitted to the result comparison unit in sequence to compare the n-1th decoded frame data with the standard data.
[0071] In this way, the comparison between the decoded frame data and the standard data of n frames of k ES streams of a decoding IP core is completed.
[0072] In this embodiment, for a video decoding chip including multiple decoding IP cores, when a multi-core parallel verification request for multiple decoding IP cores is received, multi-core parallel verification can be performed in the following manner: the decoding IP core information that needs to be verified in parallel and the verification task information of each decoding IP core contained in the acquisition request are collected, and the number m of decoding IP cores to be verified in parallel, the number of parallel decoding verification paths of each decoding IP core and the video standard parameter information of each path, and the synchronization mechanism parameter information of the decoding IP core are configured, where m is an integer greater than or equal to 2, and the aforementioned configured information is transmitted to the video decoding firmware; the verification task information of each decoding IP core is transmitted to the video decoding firmware, and the video decoding firmware simultaneously controls the m decoding IP cores to perform multi-core parallel decoding, and controls the multiple video streams of different video standards inside each decoding IP core to perform the aforementioned multi-path multi-standard parallel decoding; according to the aforementioned synchronization mechanism parameters, the decoding results of each decoding IP core are collected in parallel and sent to a result comparison unit on a PC; the result comparison unit compares the decoded frame data of each video stream received by each decoding IP core with the standard data corresponding to the decoded frame to verify the decoding result.
[0073] In this embodiment, the specific steps of performing parallel verification of multiple decoding IP cores are as follows: the video decoding firmware configures the decoding verification path k_i and the video standard format type of each path of each decoding IP core vdec_i according to the internal parameters and synchronization mechanism parameter information of each decoding IP core transmitted by the result comparison unit to complete the initialization, wherein i=0, 1, ..., m-1, and there are m decoding IP cores in total; according to the synchronization mechanism parameters of the decoding IP core and the verification task information of each decoding IP core, the video decoding firmware controls the m decoding IP cores to simultaneously perform internal multi-path parallel decoding of video streams of different video standards; and according to the synchronization mechanism parameters of the decoding IP core, the video decoding firmware transmits the internal k_i paths of the i-th decoding IP core vdec_i to the result comparison unit in parallel, wherein i=0, 1, ..., m-1; the result comparison unit is used to receive the decoding frame data of each path of each decoding IP core, and to perform parallel comparison on the decoding frame data of each path of the m decoding IP cores at the same time.
[0074] At this time, the steps of controlling m decoding IP cores to simultaneously perform parallel decoding of multiple internal video streams of different video standards are as follows: the video decoding firmware starts the decoding IP core vdec_0, and decodes the decoded frame data of the k_0 path of the decoding IP core vdec_0 in parallel; at the same time, the video decoding firmware starts the decoding IP core vdec_1, and decodes the decoded frame data of the k_1 path of the decoding IP core vdec_1 in parallel, and so on, the video decoding firmware simultaneously starts the decoding IP core vdec_m-1, and decodes the decoded frame data of the k_m-1 path of the decoding IP core vdec_m-1 in parallel.
[0075] At this time, the steps of simultaneously performing parallel comparison on the multi-channel decoded frame data of the m decoding IP cores are as follows: compare the k_0 channel decoded frame data inside the decoding IP core vdec_0 with the corresponding standard data, and perform k_0 channel parallel verification; at the same time, compare the k_1 channel decoded frame data inside the decoding IP core vdec_1 with the corresponding standard data, and perform k_1 channel parallel verification; and so on, compare the k_m-1 channel decoded frame data inside the decoding IP core vdec_m-1 with the corresponding standard data, and perform k_m-1 channel parallel verification.
[0076] The following example takes m video decoding IP cores including m decoding verification channels (k_i=m, i=0,1,......m-1), combined with Figure 3 Describes in detail the parallel verification process of video multi-decoding IP cores without an operating system.
[0077] First, verify that the synchronization management unit has configured the parameters, initialize the result comparison unit of the PC, and transmit the internal parameters and synchronization mechanism parameters of different video decoding IP cores to the video decoding firmware. There are m video decoding IP cores in total, and each IP core has k_0, k_1...k_m-1 paths (a total of m paths).
[0078] Then, the video decoding firmware configures m video decoding IP cores vdec_0, vdec_1, ..., vdec_m-1, and according to the video decoding IP core synchronization mechanism, the video decoding firmware simultaneously performs internal k_0, k_1 ..., k_m-1 parallel decoding (m = k_0 = k_1 = ... k_m-1) on the m video decoding IP cores vdec_0, vdec_1, ..., vdec_m-1. Specifically, the video decoding firmware simultaneously starts the decoding IP cores vdec_0, vdec_1, ..., vdec_m-1, and decodes the decoding frame data of each m path in parallel through the decoding IP core vdec_0, and decodes the decoding frame data of each m path in parallel through the decoding IP core vdec_1, and so on, and decodes the decoding frame data of each m path in parallel through the decoding IP core vdec_m-1.
[0079] Subsequently, according to the video decoding IP core synchronization mechanism, the video decoding firmware transmits the decoded frame data of the m video decoding IP cores vdec_0, vdec_1, ... vdec_m-1 in parallel to the result comparison unit, and performs parallel comparison on the internal m-channel decoded frame data at the same time. Specifically, the m-channel decoded frame data inside the decoding IP core vdec_0 is compared with the corresponding standard data to perform m-channel parallel verification; at the same time, the m-channel decoded frame data inside the decoding IP core vdec_1 is compared with the corresponding standard data to perform m-channel parallel verification; and so on, the m-channel decoded frame data inside the decoding IP core vdec_m-1 is compared with the corresponding standard data to perform m-channel parallel verification.
[0080] In this embodiment, the result comparison unit has a video decoding hardware submodule verification mode and a decoding frame verification mode.
[0081] In the video decoding hardware submodule verification mode, the result comparison unit generates a test vector of the hardware submodule based on the built-in video standard C code, and the test vector can be used for RTL simulation verification of the decoding IP.
[0082] In the decoding frame verification mode, the result comparison unit communicates with the video decoding firmware and generates standard data for comparison of each decoding frame. According to the synchronization mechanism parameters, the decoding frame data generated by multiple decoding IP cores are compared with the standard data to perform multi-core multi-channel parallel verification. This parallel verification can be used for module FPGA verification of the decoding IP.
[0083] For details, see Figure 4 As shown, the result comparison unit can switch between the video decoding hardware submodule verification mode and the decoding frame verification mode according to the mode control instruction.
[0084] The video decoding hardware submodule verification mode is applicable to the RTL simulation verification stage of the IP. In the video decoding hardware submodule verification mode, the result comparison unit can be used as a standard C code to generate test vectors for the RTL simulation verification service of the decoding IP core submodule.
[0085] The decoding frame verification mode is applicable to the module FPGA verification stage of the decoding IP. In the decoding frame verification mode, the result comparison unit communicates with the video decoding firmware to generate the comparison data of each decoding frame, and compares it with the decoding frames generated by the video multi-decoding IP core according to the synchronization management mechanism to verify the decoding results of each video channel and realize multi-core multi-standard parallel verification.
[0086] Specifically, first, in the order of the 0th frame of the 0th channel, the 0th frame of the 1st channel, and the 0th frame of the k_ith channel, the verification of the 0th frame of all k_i channels of the decoding IP core vdec_i is completed. Then, in the order of the 1st frame of the 0th channel, the 1st frame of the 1st channel, and the 1st frame of the k_ith channel, the verification of the 1st frame of all k_i channels of the IP core vdec_i is completed. Finally, in the order of the n_i-1th frame of the 0th channel, the n_i-1th frame of the 1st channel, and the n_i-1th frame of the k_ith channel, the verification of the n_i-1th frame of all k_i channels of the IP core vdec_i is completed.
[0087] The above-mentioned technical scheme provided by the present invention optimizes multiple sets of single-channel single-standard video decoding firmware into a set of video decoding firmware supporting multiple channels and multiple standards, and optimizes multiple sets of single-channel single-standard PC codes into a set of PC result comparison units supporting multiple channels and multiple standards. At the beginning of the decoding frame verification, the parameters can be configured by the verification synchronization management unit, which supports both the multi-channel and multi-standard parallel decoding verification of a single video decoding IP core and the multi-core parallel decoding verification of multiple decoding IP cores. In this way, the single-core multi-channel coupling problem and the multi-core multi-channel coupling problem can be discovered in advance in the module FPGA verification stage of the video decoding IP, reducing the probability of restarting the verification iteration at a later stage. On the other hand, the result comparison unit on the PC side of the present invention has multiple modes, which can be applied to the RTL simulation verification stage of the video decoding IP, and can also be applied to the module FPGA verification stage of the video decoding IP.
[0088] Another embodiment of the present invention further provides a module FPGA verification system for chip video decoding IP, which is used for IP core verification without an operating system.
[0089] The system includes an FPGA verification platform, a PC, and a verification synchronization management unit corresponding to the FPGA verification platform and the PC; the FPGA verification platform is provided with a video decoding firmware of a decoding IP core, and the video decoding firmware is used to initialize decoding-related parameters and configure the initial state of the decoding hardware; the PC is provided with a result comparison unit, and the result comparison unit can perform multi-channel communication with the aforementioned video decoding firmware.
[0090] The verification synchronization management unit is configured as follows: for each decoding IP core in the chip, configure the number of parallel decoding verification paths and the video standard parameter information of each path of the decoding IP core, initialize the result comparison unit on the PC according to the above configuration information, and start multi-path communication between the result comparison unit and the video decoding firmware, wherein the number of paths is an integer greater than or equal to 2, and different video decoding paths correspond to different video standards; and, for each multi-path decoding verification video stream of the decoding IP core, interact with the decoding hardware of each path through the aforementioned video decoding firmware to perform multi-path and multi-standard parallel verification of multiple video streams of different video standards, and during the decoding process, transmit the decoded frame data of each video stream to the result comparison unit on the PC through the video decoding firmware.
[0091] The result comparison unit is used to compare the received decoded frame data of each video stream with the standard data corresponding to the decoded frame to verify the decoding result.
[0092] In this embodiment, the verification synchronization management unit is further configured to: upon receiving a multi-core parallel verification request for multiple decoding IP cores, configure the number m of decoding IP cores to be verified in parallel, the number of parallel decoding verification paths for each decoding IP core and the video standard parameter information for each path, and the synchronization mechanism parameter information of the decoding IP core according to the decoding IP core information to be verified in parallel contained in the request, wherein m is an integer greater than or equal to 2, and transmit the aforementioned configured information to the video decoding firmware; and transmit the verification task information of each decoding IP core to the video decoding firmware, and simultaneously run m decoding IP cores for multi-core parallel decoding through the video decoding firmware, and perform the aforementioned multi-path multi-standard parallel verification through the multiple video streams of different video standards within each decoding IP core; and, according to the aforementioned synchronization mechanism parameters, collect the decoding results of each decoding IP core in parallel and send them to the result comparison unit on the PC.
[0093] The result comparison unit is used to compare the decoded frame data of each video stream received by each decoding IP core with the standard data corresponding to the decoded frame to verify the decoding result.
[0094] In this embodiment, the result comparison unit has a video decoding hardware submodule verification mode and a decoding frame verification mode.
[0095] In the video decoding hardware submodule verification mode, the result comparison unit generates a test vector of the hardware submodule based on the built-in video standard C code, and the test vector can be used for RTL simulation verification of the decoding IP;
[0096] In the decoding frame verification mode, the result comparison unit communicates with the video decoding firmware and generates standard data for comparison of each decoding frame. According to the synchronization mechanism parameters, the decoding frame data generated by multiple decoding IP cores are compared with the standard data to perform multi-core multi-channel parallel verification. This parallel verification can be used for module FPGA verification of the decoding IP.
[0097] For other technical features, please refer to the previous embodiments and will not be described in detail here.
[0098] The verification system without operating system proposed by the present invention uses a set of video decoding firmware and a set of PC-side result comparison unit. After the verification synchronization management unit configures the parameters such as the number of decoding paths and the video standard of each path, it can support multi-path multi-standard decoding parallel verification. Further, after the verification synchronization management unit configures the number of decoding IP cores, the number of decoding paths of each IP core, the video standard of each path, the synchronization mechanism and other parameters, multiple decoding IP cores can be allowed to run in parallel, and each IP core supports multi-path multi-standard decoding parallel verification. In this way, the single-core multi-path coupling problem and the multi-core multi-path coupling problem can be discovered in advance in the module FPGA verification stage of the video decoding IP. On the other hand, the result comparison unit of the PC end of the present invention has multiple modes, which can be applied to the RTL simulation verification stage of the video decoding IP, and can also be applied to the module FPGA verification stage of the video decoding IP. The result comparison unit communicates with the video decoding firmware to generate each decoding frame comparison data, and compares the decoding frames of each path generated by the video multi-decoding IP core according to the synchronization management mechanism.
[0099] In the above description, the disclosure of the present invention is not intended to limit itself to these aspects. Rather, within the scope of the target protection of the present disclosure, the components can be selectively and operatively combined in any number. In addition, terms such as "include", "encompass" and "have" should be interpreted as inclusive or open by default, rather than exclusive or closed, unless they are explicitly defined to the contrary. All technical, scientific or other terms are consistent with the meanings understood by those skilled in the art, unless they are defined to the contrary. Common terms found in dictionaries should not be interpreted too idealistically or too impractically in the context of relevant technical documents, unless the present disclosure explicitly defines them as such. Any changes and modifications made by a person of ordinary skill in the field of the present invention based on the above disclosure belong to the scope of protection of the claims.
Claims
1. A module FPGA verification method for chip video decoding IP, used for IP core verification without operating system, characterized in that Includes steps: Importing the video decoding firmware of the decoding IP core into the FPGA verification platform, wherein the video decoding firmware is used to initialize decoding-related parameters and configure the initial state of the decoding hardware; The verification synchronization management unit configures the number of parallel decoding verification paths of each decoding IP core and the video standard parameter information of each path, and initializes the result comparison unit on the PC according to the above configuration information. The number of paths is an integer greater than or equal to 2, and different video decoding paths correspond to different video standards; Initiate multi-channel communication between the result comparison unit and the video decoding firmware, for each multi-channel decoding verification video stream of the decoding IP core, the video decoding firmware interacts with the decoding hardware of each channel to perform multi-channel multi-standard parallel decoding of multiple video streams of different video standards, and during the decoding process, the video decoding firmware transmits the decoded frame data of each video stream to the result comparison unit on the PC; The result comparison unit compares the received decoded frame data of each video stream with the standard data corresponding to the decoded frame to verify the decoding result.
2. The method according to claim 1, characterized in that: The steps for multi-channel and multi-standard parallel verification of a single decoding IP core are as follows: Input multiple video ES streams into multiple ES stream buffers on the FPGA verification platform; The video decoding firmware configures the number of decoding firmware channels k and the video standard format type of each channel according to the configuration parameter information transmitted by the result comparison unit to complete initialization; k is an integer greater than or equal to 2; The video decoding firmware configures decoding parameters starting from the 0th frame of the 0th ES stream, parses the upper-layer syntax information of the 0th ES stream, configures the relevant syntax information into the corresponding registers of the hardware, and then starts the decoding IP core to start on-chip decoding. The decoding IP core completes the decoding of all slices of the 0th frame of the 0th ES stream; the decoding firmware transmits the decoded 0th decoded frame data of the 0th ES stream obtained by decoding to the result comparison unit on the PC. After the result comparison unit generates the standard data of the decoded frame through its own video standard C code, it compares the aforementioned 0th decoded frame data of the 0th ES stream with the standard data to verify the decoding result; According to the same method, the video decoding firmware completes the decoding of the 0th frame of the jth ES stream, where j=1, 2, ..., k-1, and transmits the 0th decoded frame of the jth ES stream obtained by decoding to the result comparison unit for comparison, so as to complete the comparison of the 0th decoded frame data of the kth ES stream with the standard data; According to the decoding verification method for the 0th decoded frame data of the aforementioned k-way ES stream, the 1st decoded frame data of the j-th ES stream is decoded in sequence and transmitted to the result comparison unit for comparison, wherein j=0, 1..., k-1, so as to complete the comparison between the 1st decoded frame data of the k-way ES stream and the standard data; and so on, according to the same method, the comparison between the n-1th decoded frame data of the k-way ES stream and the standard data is completed in sequence, wherein n represents the number of image frames contained in the video ES stream, and n is an integer greater than or equal to 2.
3. The method according to claim 1, characterized in that For a video decoding chip including multiple decoding IP cores, upon receiving a multi-core parallel verification request of the multiple decoding IP cores, the multi-core parallel verification is performed in the following manner: Collect the decoding IP core information and verification task information of each decoding IP core required for parallel verification contained in the request, configure the number m of decoding IP cores to be verified in parallel, the number of parallel decoding verification paths for each decoding IP core and the video standard parameter information of each path, and the synchronization mechanism parameter information of the decoding IP core, where m is an integer greater than or equal to 2, and transmit the above-mentioned configuration information to the video decoding firmware; The verification task information of each decoding IP core is transmitted to the video decoding firmware, and the video decoding firmware simultaneously controls the m decoding IP cores to perform multi-core parallel decoding, and controls the multiple video streams of different video standards inside each decoding IP core to perform the aforementioned multi-channel multi-standard parallel decoding; According to the aforementioned synchronization mechanism parameters, the decoding results of each decoding IP core are collected in parallel and sent to the result comparison unit on the PC; The result comparison unit compares the decoded frame data of each video stream received by each decoding IP core with the standard data corresponding to the decoded frame to verify the decoding result.
4. The method according to claim 3, characterized in that The specific steps for parallel verification of multiple decoding IP cores are as follows: The video decoding firmware configures the decoding verification path number k_i of each decoding IP core vdec_i and the video standard format type of each path according to the internal parameters and synchronization mechanism parameter information of each decoding IP core transmitted by the result comparison unit, and completes the initialization, where i=0, 1, ..., m-1, and there are m decoding IP cores in total; According to the synchronization mechanism parameters of the decoding IP core and the verification task information of each decoding IP core, the video decoding firmware controls the m decoding IP cores to simultaneously perform parallel decoding of multiple internal video streams of different video standards; and according to the synchronization mechanism parameters of the decoding IP core, the video decoding firmware transmits the internal k_i channels of each decoded frame data of the i-th decoding IP core vdec_i in parallel to the result comparison unit, where i=0, 1, ..., m-1; The result comparison unit is used to receive the decoded frame data of each channel from each decoding IP core, and to perform parallel comparison on the decoded frame data of each channel from m decoding IP cores at the same time.
5. The method according to claim 4, characterized in that The steps of controlling m decoding IP cores to decode multiple internal video streams of different video standards in parallel are: The video decoding firmware starts the decoding IP core vdec_0, and decodes the decoded frame data of the k_0 path of the decoding IP core vdec_0 in parallel; at the same time, the video decoding firmware starts the decoding IP core vdec_1, and decodes the decoded frame data of the k_1 path of the decoding IP core vdec_1 in parallel. Similarly, the video decoding firmware starts the decoding IP core vdec_m-1 at the same time, and decodes the decoded frame data of the k_m-1 path of the decoding IP core vdec_m-1 in parallel.
6. The method according to claim 5, characterized in that The steps for performing parallel comparison on the multi-channel decoded frame data of m decoding IP cores are: Compare the k_0-way decoded frame data inside the decoding IP core vdec_0 with the corresponding standard data, and perform k_0-way parallel verification; at the same time, compare the k_1-way decoded frame data inside the decoding IP core vdec_1 with the corresponding standard data, and perform k_1-way parallel verification; and so on, compare the k_m-1-way decoded frame data inside the decoding IP core vdec_m-1 with the corresponding standard data, and perform k_m-1-way parallel verification.
7. The method according to claim 1, characterized in that The result comparison unit has a video decoding hardware submodule verification mode and a decoding frame verification mode; In the video decoding hardware submodule verification mode, the result comparison unit generates a test vector of the hardware submodule based on the built-in video standard C code, and the test vector can be used for RTL simulation verification of the decoding IP; In the decoding frame verification mode, the result comparison unit communicates with the video decoding firmware and generates standard data for comparison of each decoding frame. According to the synchronization mechanism parameters, the decoding frame data generated by multiple decoding IP cores are compared with the standard data to perform multi-core multi-channel parallel verification. This parallel verification can be used for module FPGA verification of the decoding IP.
8. A module FPGA verification system for chip video decoding IP, used for IP core verification without operating system, characterized in that: It includes an FPGA verification platform, a PC, and a verification synchronization management unit corresponding to the FPGA verification platform and the PC; the FPGA verification platform is provided with a video decoding firmware of a decoding IP core, and the video decoding firmware is used to initialize decoding-related parameters and configure the initial state of the decoding hardware; the PC is provided with a result comparison unit, and the result comparison unit can perform multi-channel communication with the aforementioned video decoding firmware; The verification synchronization management unit is configured to: for each decoding IP core in the chip, configure the number of parallel decoding verification paths of the decoding IP core and the video standard parameter information of each path, initialize the result comparison unit on the PC according to the above configured information, and start the multi-path communication between the result comparison unit and the video decoding firmware, wherein the number of paths is an integer greater than or equal to 2, and different video decoding paths correspond to different video standards; And, for each decoding IP core's multi-channel decoding verification video stream, the aforementioned video decoding firmware interacts with each channel's decoding hardware to perform multi-channel multi-standard parallel verification of multiple video streams of different video standards. During the decoding process, the video decoding firmware transmits the decoded frame data of each video stream to a result comparison unit on the PC; The result comparison unit is used to compare the received decoded frame data of each video stream with the standard data corresponding to the decoded frame to verify the decoding result.
9. The modular FPGA verification system according to claim 8, characterized in that: The verification synchronization management unit is further configured to: upon receiving a multi-core parallel verification request of multiple decoding IP cores, configure the number m of decoding IP cores to be verified in parallel, the number of parallel decoding verification paths of each decoding IP core and the video standard parameter information of each path, and the synchronization mechanism parameter information of the decoding IP core according to the decoding IP core information to be verified in parallel contained in the request, wherein m is an integer greater than or equal to 2, and transmit the above-mentioned configured information to the video decoding firmware; and transmitting the verification task information of each decoding IP core to the video decoding firmware, and performing multi-core parallel decoding by running m decoding IP cores at the same time through the video decoding firmware, and performing the aforementioned multi-channel multi-standard parallel verification through the multi-channel video streams of different video standards inside each decoding IP core; and, according to the aforementioned synchronization mechanism parameters, collecting the decoding results of each decoding IP core in parallel and sending them to a result comparison unit on the PC; The result comparison unit is used to compare the decoded frame data of each video stream received by each decoding IP core with the standard data corresponding to the decoded frame to verify the decoding result.
10. The modular FPGA verification system according to claim 8, characterized in that: The result comparison unit has a video decoding hardware submodule verification mode and a decoding frame verification mode; in the video decoding hardware submodule verification mode, the result comparison unit generates a test vector of the hardware submodule based on the built-in video standard C code, and the test vector can be used for RTL simulation verification of the decoding IP; In the decoding frame verification mode, the result comparison unit communicates with the video decoding firmware and generates standard data for comparison of each decoding frame. According to the synchronization mechanism parameters, the decoding frame data generated by multiple decoding IP cores are compared with the standard data to perform multi-core multi-channel parallel verification. This parallel verification can be used for module FPGA verification of the decoding IP.