Nitrogen-rich silicon nitride films for thin-film transistors

Abstract

Various embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and various methods for depositing nitrogen-rich silicon nitride, and various transistors and other devices comprising nitrogen-rich silicon nitride. In one or more embodiments, a passivation film stack comprises a silicon oxide layer disposed on a workpiece; and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer. The nitrogen-rich silicon nitride layer has a silicon concentration of about 20 atomic percent (at%) to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%. In one or more examples, the passivation film stack comprises a silicon oxide layer, a nitrogen-rich silicon nitride layer, and a third layer, the third layer comprising any type of silicon nitride, such as nitrogen-rich silicon nitride and / or hydrogen-rich silicon nitride.

Description

[0001] background

[0002] field

[0003] Embodiments of the present disclosure relate generally to deposition processes, and more particularly to vapor deposition processes for depositing silicon nitride and other materials on workpieces. Background Art

[0004] Liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), and micro-LED panels are often used in flat panel displays. Generally speaking, LCDs typically consist of two bonded glass substrates with a liquid crystal material sandwiched between them. The glass substrate can be a semiconductor substrate or a transparent substrate such as glass, quartz, sapphire, or a transparent plastic film. LCDs may also include light-emitting diodes for backlighting.

[0005] As the resolution requirements for LCDs increase, it becomes necessary to control multiple independent regions of a large number of liquid crystal cells. These independent regions of liquid crystal are called pixels. Modern display panels may have approximately 8 million pixels (4K resolution), approximately 33 million pixels (8K resolution), or even more. At least the same number of transistors are formed on the glass substrate, allowing each pixel to switch between an enabled and disabled state relative to the other pixels on the substrate.

[0006] Silicon, a material containing multiple materials, has become the building block for most thin film transistors (TFTs). Silicon containing multiple materials is used to form channel materials, such as polysilicon for low-temperature polysilicon (LTPS) TFTs, and components used to form gate dielectric layers, interfacial layers, passivation layers, and / or even etch stop layers in TFTs.

[0007] For TFTs based on metal oxide channels, silicon, including passivation layers, cannot protect the device from moisture and gas diffusion, especially for devices with indium gallium zinc oxide (IGZO) channel semiconductors. Diffusion of moisture (H2O) and / or gases (such as H2, O2, and / or N2) into the IGZO channel semiconductor and other layers can cause overall device instability. Typically, moisture and gases can originate from multiple layers below and diffuse through or from passivation layers including silicon hydroxide-rich and / or hydrogen-rich silicon nitride.

[0008] Therefore, a need exists for protective materials that reduce or prevent moisture and / or gas diffusion in TFTs or other types of devices. Summary of the Invention

[0009] Various embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and various methods for depositing nitrogen-rich silicon nitride, and various transistors and other devices containing nitrogen-rich silicon nitride. In one or more embodiments, a passivation film stack includes a silicon oxide layer, the silicon oxide layer disposed on a workpiece; and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer. The nitrogen-rich silicon nitride layer has a silicon concentration of about 20 atomic percentages (atomic percentage, at%) to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%. In one or more examples, the passivation film stack includes a silicon oxide layer, a nitrogen-rich silicon nitride layer, and a third layer, the third layer comprising any type of silicon nitride, such as nitrogen-rich silicon nitride and / or hydrogen-rich silicon nitride.

[0010] In other embodiments, a passivation film stack includes a silicon oxide layer disposed on a workpiece; and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer; wherein the nitrogen-rich silicon nitride layer has a thickness of about 1×10 -8 g / m 2 / day to about 1×10 -4 g / m 2 / day water resistivity and a silicon-hydrogen bond concentration of about 0.1% to about 10%; and wherein the nitrogen-rich silicon nitride layer has a nitrogen-to-silicon ratio of greater than 1.03 to about 2. In some examples, the nitrogen-rich silicon nitride layer has a silicon-hydrogen bond concentration of about 0.5% to about 6% and a total hydrogen bond concentration (including the nitrogen-hydrogen bond concentration) of less than 30%.

[0011] In some embodiments, a method for depositing a silicon nitride material includes heating a workpiece to a temperature of about 200° C. to about 250° C.; exposing the workpiece to a deposition gas during a plasma-enhanced chemical vapor deposition (PE-CVD) process; and depositing a nitrogen-rich silicon nitride layer on the workpiece. The deposition gas includes a silicon precursor, a nitrogen precursor, and a carrier gas, and wherein the deposition gas has a molar ratio of the silicon precursor to the nitrogen precursor to the carrier gas in the deposition gas of about 1: a range from about 4 to about 8: a range from about 20 to about 80, respectively. In some examples, the deposition gas has a molar ratio of the silicon precursor to the nitrogen precursor to the carrier gas in the deposition gas of about 1: a range from about 5 to about 7: a range from about 30 to about 50, respectively. In one or more examples, the silicon precursor is or includes silane, the nitrogen precursor is or includes ammonia, and the carrier gas is or includes nitrogen (N2). BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to understand the above-mentioned features of the present disclosure in detail, a more particular description of the present disclosure, briefly summarized above, may be obtained by reference to a number of embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only a number of exemplary embodiments and are therefore not to be construed as limiting the scope of the present disclosure, and many other equally effective embodiments may be admitted.

[0013] Figure 1 is a schematic diagram of a thin film transistor (TFT) structure including a nitrogen-rich silicon nitride layer according to one or more embodiments described and discussed herein.

[0014] Figure 2 is a schematic diagram of another TFT structure including a nitrogen-rich silicon nitride layer according to one or more embodiments described and discussed herein.

[0015] Figure 3 is a schematic diagram of another TFT structure including a nitrogen-rich silicon nitride layer according to one or more embodiments described and discussed herein.

[0016] Figure 4 is a schematic diagram of another TFT structure including a nitrogen-rich silicon nitride layer according to one or more embodiments described and discussed herein.

[0017] Figure 5 is a schematic diagram of another TFT structure including a nitrogen-rich silicon nitride layer according to one or more embodiments described and discussed herein.

[0018] Figure 6 is a schematic diagram of another TFT structure including a nitrogen-rich silicon nitride layer according to one or more embodiments described and discussed herein.

[0019] Figure 7 is a schematic diagram of a TFT structure including two nitrogen-rich silicon nitride layers according to one or more embodiments described and discussed herein.

[0020] Figure 8 is a schematic diagram of another TFT structure including two nitrogen-rich silicon nitride layers according to one or more embodiments described and discussed herein.

[0021] To facilitate understanding, identical reference numerals have been used, wherever possible, to designate identical elements that are common to the figures. It will be appreciated that elements and features of one or more embodiments may be beneficially incorporated in other embodiments. DETAILED DESCRIPTION

[0022] Various embodiments of the present disclosure generally relate to passivation film stacks comprising nitrogen-rich silicon nitride, various methods for depositing the passivation film stacks, and various transistors and other devices comprising the passivation film stacks. In one or more embodiments, the passivation film stack comprises a silicon oxide layer and a nitrogen-rich silicon nitride layer, the silicon oxide layer being disposed on a workpiece, and the nitrogen-rich silicon nitride layer being disposed on the silicon oxide layer. In some examples, the passivation film stack is disposed on the workpiece and comprises the silicon oxide layer, the nitrogen-rich silicon nitride layer, and a third layer. The third layer comprises any type of silicon nitride, such as nitrogen-rich silicon nitride and / or hydrogen-rich silicon nitride.

[0023] Compared to conventional silicon nitride, a nitrogen-rich silicon nitride layer contains more nitrogen and / or less hydrogen. Conventional silicon nitride is generally nitrogen-poor silicon nitride and / or hydrogen-rich silicon nitride. As a result, the hydrogen-rich silicon nitride layer has a greater hydrogen concentration than the nitrogen-rich silicon nitride layer described and discussed herein. Furthermore, the nitrogen-rich silicon nitride layer has a greater water resistivity than nitrogen-poor silicon nitride and / or hydrogen-rich silicon nitride.

[0024] In one or more embodiments, the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 atomic percent (at%), about 22 at%, about 24 at%, about 25 at%, about 26 at%, about 27 at%, about 28 at%, about 29 at%, about 30 at%, or about 31 at% to about 32 at%, about 33 at%, about 34 at%, about 35 at%, about 36 at%, about 37 at%, about 38 at%, or more. For example, the nitrogen-rich silicon nitride layer has a nitrogen-rich silicon nitride layer having a nitrogen-rich silicon nitride layer thickness of about 20 at% to about 38 at%, about 22 at% to about 38 at%, about 25 at% to about 38 at%, about 27 at% to about 38 at%, about 28 at% to about 38 at%, about 30 at% to about 38 at%, about 31 at% to about 38 at%, about 32 at% to about 38 at%, about 33 at% to about 38 at%, about 35 at% to about 38 at%, about 36 at% to about 38 at%, about 20 at% to about 35 at%, about 22 at% to about 35 at%, about 25 at% to about 35 at%, about 27 at% to about 35 at%, about 28 at% to about 35 at%, about 30 at% to about 35 at%, about 31 at% to about 35 at%, about 32 at% to about 35 at%, about 33 at% to about 35 at%, about 20 at% to about 34 at%, about 22 at% to about 34 at%, about 25 at% to about 34 at%, about 27 at% to about 35 at%, about 28 at% to about 35 at%, about at % to about 34 at%, about 28 at % to about 34 at%, about 30 at % to about 34 at%, about 31 at % to about 34 at%, about 32 at % to about 34 at%, about 33 at % to about 34 at%, about 20 at % to about 33 at%, about 22 at % to about 33 at%, about 25 at % to about 33 at%, about 27 at % to about 33 at%, about 28 at % to about 33 at%, about 30 at % to about 33 at%, about 31 at % to about 33 at%, or about 32 at % to about 33 at%.

[0025] In some embodiments, the nitrogen-rich silicon nitride layer has a nitrogen concentration of about 40 at%, about 42 at%, about 43 at%, about 44 at%, about 45 at%, about 46 at%, about 48 at%, about 50 at%, or about 52 at% to about 54 at%, about 55 at%, about 58 at%, about 60 at%, about 65 at%, about 70 at%, about 72 at%, about 75 at%, or more. For example, the nitrogen-rich silicon nitride layer has a nitrogen-rich silicon nitride layer having a nitrogen-rich silicon nitride layer content of about 40 at% to about 75 at%, about 42 at% to about 75 at%, about 43 at% to about 75 at%, about 44 at% to about 75 at%, about 45 at% to about 75 at%, about 48 at% to about 75 at%, about 50 at% to about 75 at%, about 55 at% to about 75 at%, about 60 at% to about 75 at%, about 65 at% to about 75 at%, about 70 at% to about 75 at%, about 40 at% to about 65 at%, about 42 at% to about 65 at%, about 43 at% to about 65 at%, about 44 at% to about 65 at%, about 45 at% to about 65 at%, about 48 at% to about 65 at%, about 50 at% to about 65 at%, about 55 at% to about 65 at%, about 60 at% to about 65 at%, about 62 at% to about 65 at%, about 40 at% to about 58 at%, about 42 at% to about 58 at%, about 43 at% to about 65 at%, at % to about 58 at %, about 44 at % to about 58 at %, about 45 at % to about 58 at %, about 48 at % to about 58 at %, about 50 at % to about 58 at %, about 55 at % to about 58 at %, about 40 at % to about 55 at %, about 42 at % to about 55 at %, about 43 at % to about 55 at %, about 44 at % to about 55 at %, about 45 at % to about 55 at %, about 48 at % to about 55 at %, about 50 at % to about 55 at %, or about 52 at % to about 55 at %.

[0026] In one or more embodiments, the nitrogen-rich silicon nitride layer has a hydrogen concentration of about 10 at%, about 12 at%, about 15 at%, about 18 at%, or about 20 at% to about 21 at%, about 22 at%, about 23 at%, about 25 at%, about 27 at%, about 30 at%, about 32 at%, about 35 at%, or more. For example, the nitrogen-rich silicon nitride layer has a nitrogen-rich silicon nitride layer having a nitrogen-rich silicon nitride layer thickness of about 10 at% to about 35 at%, about 12 at% to about 35 at%, about 15 at% to about 35 at%, about 18 at% to about 35 at%, about 19 at% to about 35 at%, about 20 at% to about 35 at%, about 21 at% to about 35 at%, about 22 at% to about 35 at%, about 23 at% to about 35 at%, about 24 at% to about 35 at%, about 25 at% to about 35 at%, about 28 at% to about 35 at%, about 30 at% to about 35 at%, about 10 at% to about 25 at%, about 12 at% to about 25 at%, about 15 at% to about 25 at%, about 18 at% to about 25 at%, about 19 at% to about 25 at%, about 20 at% to about 25 at%, about 21 at% to about 25 at%, about 22 at% to about 25 at%, about 23 at% to about 25 at%, about 24 at% to about 25 at%, about 10 at% to about 25 at at % to about 23 at %, about 12 at % to about 23 at %, about 15 at % to about 23 at %, about 18 at % to about 23 at %, about 19 at % to about 23 at %, about 20 at % to about 23 at %, about 21 at % to about 23 at %, or about 22 at % to about 23 at %.

[0027] In one or more examples, the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 at % to about 35 at %, a nitrogen concentration of about 40 at % to about 75 at %, and a hydrogen concentration of about 10 at % to about 35 at %. In other examples, the nitrogen-rich silicon nitride layer has a silicon concentration of about 27 at % to about 34 at %, a nitrogen concentration of about 42 at % to about 65 at %, and a hydrogen concentration of about 18 at % to about 25 at %. In some examples, the nitrogen-rich silicon nitride layer has a silicon concentration of about 28 at % to about 33 at %, a nitrogen concentration of about 43 at % to about 58 at %, and a hydrogen concentration of about 19 at % to about 23 at %.

[0028] In one or more embodiments, the nitrogen-rich silicon nitride layer has a nitrogen-to-silicon ratio greater than 1, greater than 1.02, greater than 1.03, or greater than 1.05, such as about 1.06, about 1.08, about 1.10, about 1.12, about 1.15, about 1.18, about 1.20, about 1.22, or about 1.25 to about 1.28, about 1.30, about 1.35, about 1.38, about 1.40, about 1.45, about 1.50, about 1.55, about 1.60, about 1.80, about 1.90, about 2, or more. For example, the nitrogen-rich silicon nitride layer has a thickness of greater than 1.03 to about 2, greater than 1.03 to about 1.9, greater than 1.03 to about 1.8, greater than 1.03 to about 1.7, greater than 1.03 to about 1.6, greater than 1.03 to about 1.5, greater than 1.03 to about 1.45, greater than 1.03 to about 1.4, greater than 1.03 to about 1.39, greater than 1.03 to about 1.38, greater than 1.03 to about 1.36, greater than 1.03 to about 1.35, greater than 1.03 to about 1.3, and greater than 1.03 to about 1. .25, greater than 1.03 to about 1.2, greater than 1.03 to about 1.15, greater than 1.03 to about 1.1, about 1.05 to about 2, about 1.05 to about 1.9, about 1.05 to about 1.8, about 1.05 to about 1.7, about 1.05 to about 1.6, about 1.05 to about 1.5, about 1.05 to about 1.45, about 1.05 to about 1.4, about 1.05 to about 1.39, about 1.05 to about 1.38, about 1.05 to about 1.36, about 1.05 to about 1.35, about 1.05 to about 1.3, about 1.05 to about 1.25, about 1.05 to about 1.2, about 1.05 to about 1.15, about 1.05 to about 1.1, about 1.1 to about 2, about 1.1 to about 1.9, about 1.1 to about 1.8, about 1.1 to about 1.7, about 1.1 to about 1.6, about 1.1 to about 1.5, about 1.1 to about 1.45, about 1.1 to about 1.4, about 1.1 to about 1.39, about 1.1 to about 1.38, about 1.1 to about 1.36, about 1.1 to about 1.35, about 1.1 to about 1. 3, a nitrogen to silicon ratio of about 1.1 to about 1.25, about 1.1 to about 1.2, about 1.1 to about 1.15, about 1.2 to about 2, about 1.2 to about 1.9, about 1.2 to about 1.8, about 1.2 to about 1.7, about 1.2 to about 1.6, about 1.2 to about 1.5, about 1.2 to about 1.45, about 1.2 to about 1.4, about 1.2 to about 1.39, about 1.2 to about 1.38, about 1.2 to about 1.36, about 1.2 to about 1.35, about 1.2 to about 1.3, or about 1.2 to about 1.25.

[0029] In some embodiments, the nitrogen-rich silicon nitride layer has a silicon-hydrogen bond concentration of about 0.05%, about 0.1%, about 0.2%, about 0.5%, about 0.8%, about 1%, about 1.2%, about 1.5%, about 1.8%, or about 2% to about 2.2%, about 2.5%, about 2.8%, about 3%, about 3.5%, about 4%, about 5%, about 6%, about 8%, about 10%, about 12%, about 14%, about 15%, about 16%, about 17%, or less than 18% as measured by Fourier-transform infrared (FT-IR) spectroscopy. For example, the nitrogen-rich silicon nitride layer has a carbon content of about 0.1% to less than 18%, about 0.1% to about 17%, about 0.1% to about 15%, about 0.1% to about 12%, about 0.1% to about 10%, about 0.1% to about 8%, about 0.1% to about 6%, about 0.1% to about 5%, about 0.1% to about 4%, about 0.1% to about 3%, about 0.1% to about 2%, about 0.1% to about 1%, about 0.5% to less than 18%, about 0.5% to about 17%, about 0.5% to about 15%, about 0.5% to about The present invention also provides a silicon-hydrogen bond concentration of about 1% to about 12%, about 0.5% to about 10%, about 0.5% to about 8%, about 0.5% to about 6%, about 0.5% to about 5%, about 0.5% to about 4%, about 0.5% to about 3%, about 0.5% to about 2%, about 0.5% to about 1%, about 1% to less than 18%, about 1% to about 17%, about 1% to about 15%, about 1% to about 12%, about 1% to about 10%, about 1% to about 8%, about 1% to about 6%, about 1% to about 5%, about 1% to about 4%, about 1% to about 3%, about 1% to about 2%, or about 1% to about 1.5%.

[0030] In one or more embodiments, the nitrogen-rich silicon nitride layer has a nitrogen-hydrogen bond concentration of about 1%, about 3%, about 5%, about 6%, about 8%, about 10%, about 12%, about 15%, or about 18% to about 20%, about 22%, about 25%, about 26%, about 27%, about 28%, about 28%, or about 30% as measured by an FT-IR spectroscopy measurement device. For example, the nitrogen-rich silicon nitride layer has a nitrogen-hydrogen bond concentration of about 1% to about 30%, about 3% to about 30%, about 5% to about 30%, about 8% to about 30%, about 10% to about 30%, about 12% to about 30%, about 15% to about 30%, about 18% to about 30%, about 20% to about 30%, about 25% to about 30%, about 1% to about 25%, about 3% to about 25%, about 5% to about 25%, about 8% to about 25%, about 10% to about 25%, about 12% to about 25%, about 15% to about 25%, about 18% to about 25%, about 20% to about 25%, about 1% to about 22%, about 3% to about 22%, about 5% to about 22%, about 8% to about 22%, about 10% to about 22%, about 12% to about 22%, about 15% to about 22%, about 18% to about 22%, or about 20% to about 22%, as measured by an FT-IR spectroscopy measurement device.

[0031] The total hydrogen bonding concentration of the nitrogen-rich silicon nitride layer is the sum of the silicon-hydrogen bonding concentration and the nitrogen-hydrogen bonding concentration. In one or more embodiments, the nitrogen-rich silicon nitride layer has a total hydrogen bonding concentration of less than 30%, such as about 1%, about 2%, about 3%, about 5%, about 6%, about 8%, about 10%, about 12%, about 15%, about 16%, or about 18%, to about 20%, about 22%, about 23%, about 24%, about 25%, about 26%, about 27%, about 28%, about 29%, or less than 30%, as measured by FT-IR spectroscopy. For example, the nitrogen-rich silicon nitride layer has a carbon monoxide content of about 1% to less than 30%, about 3% to less than 30%, about 5% to less than 30%, about 8% to less than 30%, about 10% to less than 30%, about 12% to less than 30%, about 15% to less than 30%, about 18% to less than 30%, about 20% to less than 30%, about 25% to less than 30%, about 1% to about 28%, about 3% to about 28%, about 5% to about 28%, about 8% to about 28%, about 10% to about 28%, about 12% to about 28%, about 15% to about 28%, about 18% to about ... about 30%, about 1% to about 28%, about 3% to about 28%, about 5% to about 28%, about 8% to about 28%, about 10% to about 28%, about 12% to about 28%, about 15% to about 28%, about 18% to about 30%, about 23%, about 15% to 23%, about 8% to 23%, about 10% to about 23%, about 12% to about 23%, about 15% to about 24%, about 18% to about 24%, about 20% to about 24%, about 1% to about 23%, about 3% to about 23%, about 5% to about 23%, about 8% to about 23%, about 10% to about 23%, about 12% to about 23%, about 15% to about 23%, about 16% to about 23%, about 18% to about 23%, or about 20% to about 23% total hydrogen bonding concentration.

[0032] When compared to conventional silicon nitride, the nitrogen-rich silicon nitride layer has a higher water resistivity. In one or more embodiments, the nitrogen-rich silicon nitride layer has a water vapor transmission rate (WVTR) of about 1×10 -8 g / m 2 / day or greater water resistance, for example, about 2×10 -8 g / m 2 / day, about 5×10 -8 g / m 2 / day, about 1×10 -7 g / m 2 / day, about 5×10 -7 g / m 2 / day, about 1×10 -6 g / m 2 / day, or about 5×10 -6 g / m2 / day to about 1×10 -5 g / m 2 / day, about 5×10 -5 g / m 2 / day, about 1×10 -4 g / m 2 / day, about 5×10 -4 g / m 2 / day or about 1×10 -3 g / m 2 For example, a nitrogen-rich silicon nitride layer has a water resistivity of approximately 1×10 -8 g / m 2 / day to about 1×10 -4 g / m 2 / day, about 1×10 -7 g / m 2 / day to about 5×10 -4 g / m 2 / day or about 5×10 -6 g / m 2 / day to about 1×10 -5 g / m 2 In one or more examples, a nitrogen-rich silicon nitride layer having a thickness of about 2,000 Å has a water resistivity of about 2.8×10 -4 g / m 2 / day is about 4×10 -4 g / m 2 / day water resistance rate.

[0033] In one or more embodiments, a method for depositing a nitrogen-rich silicon nitride material or layer includes heating a workpiece to a processing temperature; exposing the workpiece to a deposition gas during a plasma-enhanced chemical vapor deposition (PE-CVD) process; and depositing the nitrogen-rich silicon nitride material or layer on the workpiece. In other embodiments, a method for depositing a nitrogen-rich silicon nitride material or layer includes heating the workpiece to a processing temperature; sequentially exposing the workpiece to a silicon precursor and a nitrogen precursor during a thermal atomic layer deposition (ALD) process or a plasma-enhanced ALD (PE-ALD) process; and depositing the nitrogen-rich silicon nitride material or layer on the workpiece. In various embodiments described and discussed herein, the workpiece can be or include a substrate, a thin film transistor (TFT) structure or a substrate, a portion of a TFT structure, a gate structure or a portion of a gate structure, or any other type of electronic device or portion of an electronic device related to display, semiconductor, photovoltaic, microelectronics, and / or other fields. In some embodiments, the workpiece includes one or more layers comprising silicon oxide. In one or more examples, a method includes depositing a silicon oxide layer on a workpiece, and then depositing a nitrogen-rich silicon nitride layer on the silicon oxide layer.

[0034] During the PE-CVD or other deposition process, the substrate or workpiece can be heated to or maintained at a process temperature. The process temperature can be about 25°C, about 50°C, about 80°C, about 100°C, about 150°C, or about 200°C to about 220°C, about 235°C, about 250°C, about 280°C, about 300°C, about 350°C, about 400°C, or higher. For example, the processing temperature can be from about 25°C to about 400°C, about 25°C to about 300°C, about 25°C to about 280°C, about 25°C to about 265°C, about 25°C to about 250°C, about 25°C to about 235°C, about 25°C to about 220°C, about 25°C to about 200°C, about 25°C to about 180°C, about 25°C to about 150°C, about 25°C to about 125°C, about 25°C to about 100°C, about 25°C to about 80°C, about 25°C to about 50°C, about 100°C to about 400°C, about 100°C to about 300°C, about 100°C to about 280°C, about 100°C to about C., about 100°C to about 250°C, about 100°C to about 235°C, about 100°C to about 220°C, about 100°C to about 200°C, about 100°C to about 180°C, about 100°C to about 150°C, about 100°C to about 125°C, about 200°C to about 400°C, about 200°C to about 300°C, about 200°C to about 280°C, about 200°C to about 265°C, about 200°C to about 250°C, about 200°C to about 235°C, about 200°C to about 220°C, about 220°C to about 250°C, about 230°C to about 250°C, or about 235°C to about 250°C. In one or more examples, the processing temperature is less than 350°C, less than 300°C, less than 280°C, less than 265°C, less than 250°C, less than 235°C, or less than 200°C.

[0035] In one or more embodiments, during a PE-CVD or other deposition process, the deposition gas may include one or more silicon precursors, one or more nitrogen precursors, and one or more carrier gases. The silicon precursor may be or include one or more of silane, disilane, trisilane, tetrasilane, silicon tetrafluoride, or any combination thereof. The nitrogen precursor may be or include one or more of ammonia, hydrazine, methylamine, dimethylamine, nitrogen (N2), plasmas of the foregoing, or any combination thereof. The carrier gas may be or include one or more of nitrogen (N2), hydrogen (H2), argon, helium, neon, xenon, krypton, or any combination thereof. In one or more examples, the silicon precursor is or includes silane, the nitrogen precursor is or includes ammonia, and the carrier gas is or includes nitrogen.

[0036] The flow rate of the silicon precursor in the deposition gas may be about 100 sccm (standard cubic centimeters per minute), about 150 sccm, about 180 sccm, about 200 sccm, about 220 sccm, or about 250 sccm to about 280 sccm, about 300 sccm, about 320 sccm, about 350 sccm, about 400 sccm, about 450 sccm, about 500 sccm, about 650 sccm, about 800 sccm, or about 1,000 sccm. For example, the flow rate of the silicon precursor may be from about 100 sccm to about 1,000 sccm, about 100 sccm to about 800 sccm, about 100 sccm to about 500 sccm, about 100 sccm to about 400 sccm, about 100 sccm to about 350 sccm, about 100 sccm to about 300 sccm, about 100 sccm to about 250 sccm, about 100 sccm to about 200 sccm, about 200 sccm to about 1,000 sccm, about 200 sccm to about 800 sccm, about 200 sccm to about 500 sccm, about 200 sccm to about 400 sccm, about 200 sccm to about 350 sccm, about 200 sccm to about 300 sccm, about 200 sccm to about 250 sccm, about 200 sccm to about The present invention relates to a method for producing a molten metal ion battery having a temperature of at least about 100 sccm and a maximum temperature of about 100 sccm. The method further comprises the step of: using a first molten metal ion battery having a temperature of at least about 100 sccm and a maximum temperature of about 100 sccm; a second molten metal ion battery having a temperature of at least about 100 sccm and a maximum temperature of about 100 sccm; and a third molten metal ion battery having a temperature of at least about 100 sccm and a maximum temperature of about 100 sccm.

[0037] The flow rate of the nitrogen precursor in the deposition gas may be about 800 sccm, about 1,000 sccm, about 1,200 sccm, about 1,350 sccm, about 1,500 sccm, or about 1,600 sccm to about 1,650 sccm, about 1,700 sccm, about 1,800 sccm, about 2,000 sccm, about 2,200 sccm, about 2,500 sccm, about 3,000 sccm, about 3,500 sccm, about 4,000 sccm, or about 5,000 sccm. For example, the flow rate of the nitrogen precursor may be from about 1,000 sccm to about 5,000 sccm, about 1,000 sccm to about 4,000 sccm, about 1,000 sccm to about 3,000 sccm, about 1,000 sccm to about 2,500 sccm, about 1,000 sccm to about 2,000 sccm, about 1,000 sccm to about 1,800 sccm, about 1,000 sccm to about 1,500 sccm, about 1,500 sccm to about 5,000 sccm, about 1,500 sccm to about 4,000 sccm, about 1,500 sccm to about 3,000 sccm, about 1,500 sccm to about 2,500 sccm, about 1,500 sccm to about 2,000 sccm, or about 1,500 sccm to about 2,000 sccm. sccm, about 1,500 sccm to about 1,800 sccm, about 1,800 sccm to about 5,000 sccm, about 1,800 sccm to about 4,000 sccm, about 1,800 sccm to about 3,000 sccm, about 1,800 sccm to about 2,500 sccm, or about 1,800 sccm to about 2,000 sccm.

[0038] The flow rate of the carrier gas in the deposition gas may be about 1 SLM (standard liters per minute), about 3 SLM, about 4 SLM, about 5 SLM, about 6 SLM, or about 8 SLM to about 9 SLM, about 10 SLM, about 12 SLM, about 15 SLM, about 18 SLM, about 20 SLM, about 22 SLM, about 25 SLM, or about 30 SLM. For example, the flow rate of the carrier gas can be from about 1 SLM to about 30 SLM, about 5 SLM to about 30 SLM, about 8 SLM to about 30 SLM, about 10 SLM to about 30 SLM, about 12 SLM to about 30 SLM, about 15 SLM to about 30 SLM, about 20 SLM to about 30 SLM, about 1 SLM to about 20 SLM, about 5 SLM to about 20 SLM, about 8 SLM to about 20 SLM, about 10 SLM to about 20 SLM, about 12 SLM to about 20 SLM, about 15 SLM to about 20 SLM, about 18 SLM to about 20 SLM, about 1 SLM to about 15 SLM, about 5 SLM to about 15 SLM, about 8 SLM to about 15 SLM, about 10 SLM to about 15 SLM, about 12 SLM to about 15 SLM, or about 13 SLM to about 15 SLM.

[0039] In one or more examples, the deposition gas has a molar ratio of silicon precursor to nitrogen precursor to carrier gas of about 1: nitrogen precursor ranging from about 4 to about 8: carrier gas ranging from about 20 to about 80, respectively. In other examples, the deposition gas has a molar ratio of silicon precursor to nitrogen precursor to carrier gas of about 1: nitrogen precursor ranging from about 5 to about 7: carrier gas ranging from about 30 to about 50, respectively. In some examples, the deposition gas has a molar ratio of silicon precursor to nitrogen precursor to carrier gas of about 1: nitrogen precursor ranging from about 5.5 to about 6.5: carrier gas ranging from about 35 to about 45, respectively.

[0040] PE-CVD or other deposition processes can be performed in various plasma systems, such as a capacitive coupling plasma (CCP) system, an inductive coupling plasma (ICP) system utilizing a high-density plasma (HDP), a remote plasma system (RPS), or other PE-CVD or PE-ALD processing chambers or systems. During the PE-CVD or other deposition process, the plasma can have a radio frequency (RF) power of less than 2,400 watts (W), such as about 800 W, about 1,000 W, about 1,200 W, about 1,500 W, about 1,700 W, or about 1,800 W to about 1,900 W, about 2,000 W, about 2,100 W, about 2,200 W, or about 2,300 W. For example, the plasma may have a power of about 800 W to less than 2,400 W, about 800 W to about 2,200 W, about 800 W to about 2,000 W, about 800 W to about 1,900 W, about 800 W to about 1,800 W, about 800 W to about 1,600 W, about 800 W to about 1,200 W, about 1,200 W to less than 2,400 W, about 1,200 W to about 2,200 W, about 1,200 W to about 2,000 W, about 1,200 W to about 1,900 W, about 1,200 W to about 1,800 W, about 1,200 W to about 1,600 W, about 1,200 W to about 1,500 W, about 1,500 W to less than 2,400 W, about 1,500 W to about 2,200 W, about 1,500 W to about W to about 2,000 W, about 1,500 W to about 1,900 W, or about 1,500 W to about 1,800 W of RF power.

[0041] In one or more embodiments, the nitrogen-rich silicon nitride layer is part of a passivation film stack, the passivation film stack comprising a silicon oxide layer and a nitrogen-rich silicon nitride layer, the nitrogen-rich silicon nitride layer being disposed on the silicon oxide layer. In some examples, the passivation film stack also comprises a third layer comprising silicon nitride, the third layer being disposed on the nitrogen-rich silicon nitride layer. The third layer can be or comprise any type of silicon nitride, such as nitrogen-rich silicon nitride, nitrogen-deficient silicon nitride, and / or hydrogen-rich silicon nitride. In other embodiments, the nitrogen-rich silicon nitride layer is part of an oxide buffer film stack, the oxide buffer film stack comprising an oxide buffer layer comprising nitrogen-rich silicon nitride, disposed on the oxide buffer layer comprising silicon oxide.

[0042] In some embodiments, during the PE-CVD process, a silicon oxide layer and / or an oxide buffer layer comprising silicon oxide may be deposited or otherwise formed. The PE-CVD process includes exposing the workpiece to an oxide deposition gas and depositing a silicon oxide layer and / or an oxide buffer layer comprising silicon oxide on the workpiece. The oxide deposition gas may include one or more silicon precursors, one or more oxidants, and optionally one or more carrier gases. The silicon precursor may be or include one or more of monosilane, disilane, trisilane, tetrasilane, silicon tetrafluoride, or any combination of the foregoing. The oxidant may be or include one or more of nitrous oxide, oxygen, ozone, water, one or more peroxides, plasma of the foregoing, or any combination of the foregoing. If a carrier gas is included, the carrier gas may be or include one or more of nitrogen (N2), hydrogen (H2), argon, helium, neon, xenon, krypton, or any combination of the foregoing. In one or more examples, the silicon precursor is or includes monosilane and the oxidant is or includes nitrous oxide.

[0043] The flow rate of the silicon precursor in the oxide deposition gas may be about 20 sccm, about 35 sccm, about 50 sccm, about 60 sccm, about 80 sccm, or about 100 sccm to about 120 sccm, about 135 sccm, about 150 sccm, about 165 sccm, about 180 sccm, about 200 sccm, about 250 sccm, about 280 sccm, about 300 sccm, about 350 sccm, about 400 sccm, or about 500 sccm. For example, the flow rate of the silicon precursor can be from about 20 sccm to about 500 sccm, about 20 sccm to about 400 sccm, about 20 sccm to about 350 sccm, about 20 sccm to about 300 sccm, about 20 sccm to about 250 sccm, about 20 sccm to about 220 sccm, about 20 sccm to about 200 sccm, about 20 sccm to about 180 sccm, about 20 sccm to about 165 sccm, about 20 sccm to about 150 sccm, about 20 sccm to about 135 sccm, about 20 sccm to about 120 sccm, about 20 sccm to about 100 sccm, about 20 sccm to about 80 sccm, about 20 sccm to about 50 sccm, about 100 sccm to about 500 sccm, about 100 sccm to about 400 sccm, or about 100 sccm to about 400 sccm. sccm, about 100 sccm to about 350 sccm, about 100 sccm to about 300 sccm, about 100 sccm to about 250 sccm, about 100 sccm to about 220 sccm, about 100 sccm to about 200 sccm, about 100 sccm to about 180 sccm, about 100 sccm to about 165 sccm, about 100 sccm to about 150 sccm, about 100 sccm to about 135 sccm, about 100 sccm to about 120 sccm, about 140 sccm to about 500 sccm, about 140 sccm to about 400 sccm, about 140 sccm to about 350 sccm, about 140 sccm to about 300 sccm, about 140 sccm to about 250 sccm, about 140 sccm to about 220 sccm, about 140 sccm to about 200 sccm, about 140 sccm to about 180 sccm, about 140 sccm to about 165 sccm, or about 140 sccm to about 150 sccm.

[0044] The flow rate of the oxidizer in the oxide deposition gas may be about 1 SLM, about 2 SLM, about 3 SLM, about 4 SLM, about 5 SLM, or about 6 SLM to about 7 SLM, about 8 SLM, about 9 SLM, about 10 SLM, about 11 SLM, about 12 SLM, about 14 SLM, about 16 SLM, about 18 SLM, or about 20 SLM. For example, the flow rate of the oxidant in the oxide deposition gas may be about 1 SLM to about 20 SLM, about 1 SLM to about 18 SLM, about 1 SLM to about 15 SLM, about 1 SLM to about 12 SLM, about 1 SLM to about 10 SLM, about 1 SLM to about 8 SLM, about 1 SLM to about 6 SLM, about 1 SLM to about 5 SLM, about 4 SLM to about 20 SLM, about 4 SLM to about 18 SLM, about 4 SLM to about 15 SLM, about 4 SLM to about 12 SLM, about 4 SLM to about 10 SLM, about 4 SLM to about 8 SLM, about 4 SLM to about 6 SLM, about 8 SLM to about 20 SLM, about 8 SLM to about 18 SLM, about 8 SLM to about 15 SLM, about 8 SLM to about 12 SLM, or about 8 SLM to about 10 SLM.

[0045] In some examples, during the PE-CVD process, the oxide deposition gas is exposed to a plasma having an RF power of about 800 W, about 1,000 W, about 1,500 W, about 1,800 W, or about 2,000 W to about 2,200 W, about 2,500 W, about 2,800 W, about 3,000 W, about 3,500 W, about 4,000 W, about 4,500 W, about 5,000 W, or more. For example, during the PE-CVD process, the oxide deposition gas is exposed to a plasma having an RF power from about 800 W to 5,000 W, about 1,000 W to about 4,000 W, about 1,000 W to about 3,500 W, about 1,000 W to about 3,000 W, about 1,000 W to about 2,500 W, about 1,000 W to about 2,000 W, about 2,000 W to about 4,000 W, about 2,000 W to about 3,500 W, about 2,000 W to about 3,000 W, about 2,000 W to about 2,500 W, about 2,000 W to about 2,200 W, or about 2,800 W to about 3,200 W.

[0046] Figure 1FIG1 is a schematic diagram of a thin film transistor (TFT) structure 100 including a passivation film stack 156 including a silicon oxide layer 160 and a nitrogen-rich silicon nitride layer 170 according to one or more embodiments described and discussed herein. The TFT structure 100 includes a buffer layer 110 and a first metal layer 120. The buffer layer 110 is disposed on a substrate 102, and the first metal layer 120 is disposed on the buffer layer 110. The buffer layer 110 is disposed between the substrate 102 and the first metal layer 120.

[0047] Substrate 102 may be a semiconductor substrate, a display substrate, or any other type of substrate. In some examples, substrate 102 may be transparent. Substrate 102 may be or include glass, quartz, sapphire, plastic or polymer (e.g., a transparent plastic film), silicon, silicon oxide, gallium, gallium arsenide, or doped variants thereof, or any combination thereof. Buffer layer 110 may be or include silicon oxide, silicon nitride, silicon oxynitride, dopants thereof, or any combination thereof. Buffer layer 110 may include one, two, three, four, or more layers of the same and / or different materials. In some examples, buffer layer 110 may be or include a stack of silicon oxide and silicon nitride. For example, buffer layer 110 may be or include a stack of silicon oxide and silicon nitride. For example, buffer layer 110 may include a first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer, wherein the first silicon nitride layer is disposed on the first silicon oxide layer, and the second silicon oxide layer is disposed on the first silicon nitride layer. The buffer layer 110 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1,000 Å, about 1,500 Å, or about 2,000 Å to about 2,500 Å, about 3,000 Å, about 4,000 Å, about 5,000 Å, about 8,000 Å, or about 10,000 Å. For example, the buffer layer 110 may have a thickness of about 50 Å to about 10,000 Å, about 500 Å to about 10,000 Å, or about 1,000 Å to about 8,000 Å.

[0048] The first metal layer 120 may be or include chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium-molybdenum, copper-molybdenum, alloys thereof, dopants thereof, or any combination thereof. The first metal layer 120 may have a thickness of about 500 Å, about 800 Å, about 1,000 Å, about 1,500 Å, or about 2,000 Å to about 2,500 Å, about 3,000 Å, about 4,000 Å, about 5,000 Å, about 8,000 Å, or about 10,000 Å. For example, the first metal layer 120 may have a thickness of about 500 Å to about 10,000 Å, about 1,000 Å to about 10,000 Å, or about 1,500 Å to about 8,000 Å.

[0049] The TFT structure 100 includes a gate insulating layer 130 disposed on and / or above the first metal layer 120 and on the buffer layer 110. A metal oxide layer 140 is disposed on the gate insulating layer 130. A second or contact metal layer 150 is disposed on and / or above the metal oxide layer 140 and on the gate insulating layer 130 to form a gate structure.

[0050] The gate insulating layer 130 may be or include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, silicates thereof, nitrides thereof, dopants thereof, or any combination thereof. The gate insulating layer 130 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1,000 Å, about 1,500 Å, or about 2,000 Å to about 2,500 Å, about 3,000 Å, about 4,000 Å, about 5,000 Å, about 8,000 Å, or about 10,000 Å. For example, the gate insulating layer 130 may have a thickness of about 50 Å to about 10,000 Å, about 500 Å to about 10,000 Å, or about 1,000 Å to about 8,000 Å.

[0051] The metal oxide layer 140 may be or include molybdenum oxide, copper oxide, aluminum oxide, titanium oxide, indium oxide, tin oxide, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), alloys thereof, dopants thereof, or any combination thereof. The metal oxide layer 140 may have a thickness of about 50 Å, about 100 Å, about 250 Å, or about 500 Å to about 800 Å, about 1,000 Å, about 1,200 Å, about 1,500 Å, about 1,800 Å, or about 2,000 Å. For example, the metal oxide layer 140 may have a thickness of about 50 Å to about 2,000 Å, about 100 Å to about 2,000 Å, or about 500 Å to about 1,500 Å.

[0052] The second or contact metal layer 150 can be or include chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium-molybdenum, copper-molybdenum, alloys thereof, dopants thereof, or any combination thereof. The second contact or metal layer 150 can have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1,000 Å, about 1,500 Å, or about 2,000 Å to about 2,500 Å, about 3,000 Å, about 4,000 Å, about 5,000 Å, about 8,000 Å, or about 10,000 Å. For example, the second or contact metal layer 150 can have a thickness of about 50 Å to about 10,000 Å, about 500 Å to about 10,000 Å, or about 1,000 Å to about 8,000 Å.

[0053] A passivation film stack 156 is disposed on and above the gate structure, such that a silicon oxide layer 160 is disposed on at least one, two, or more layers of the second or contact metal layer 150, the metal oxide layer 140, the gate insulating layer 130, or any combination thereof. In one or more examples, the silicon oxide layer 160 is disposed on the second or contact metal layer 150, the metal oxide layer 140, and the gate insulating layer 130. A nitrogen-rich silicon nitride layer 170 is disposed on the silicon oxide layer 160.

[0054] The silicon oxide layer 160 may be or include silicon dioxide or silica. The silicon oxide layer 160 may have a thickness of about 50 nm, about 100 nm, or about 200 nm to about 300 nm, about 500 nm, about 800 nm, about 1,000 nm, or more. For example, the silicon oxide layer 160 may have a thickness of about 50 nm to about 1,000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 200 nm, about 50 nm to about 100 nm, about 100 nm to about 1,000 nm, about 100 nm to about 800 nm, about 100 nm to about 500 nm, about 100 nm to about 300 nm, or about 100 nm to about 200 nm.

[0055] Nitrogen-rich silicon nitride layer 170 comprises the components described and discussed herein. Nitrogen-rich silicon nitride layer 170 may have a thickness of about 1 nm, about 5 nm, about 10 nm, about 20 nm, about 30 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 800 nm, about 1,000 nm, or more. For example, the nitrogen-rich silicon nitride layer 170 may have a thickness of about 1 nm to about 1,000 nm, about 1 nm to about 800 nm, about 1 nm to about 500 nm, about 1 nm to about 300 nm, about 1 nm to about 250 nm, about 1 nm to about 200 nm, about 1 nm to about 150 nm, about 1 nm to about 100 nm, about 1 nm to about 80 nm, about 1 nm to about 50 nm, about 1 nm to about 25 nm, about 1 nm to about 15 nm, about 1 nm to about 10 nm, about 1 nm to about 5 nm, about 20 nm to about 1,000 nm, about 20 nm to about 800 nm, about 20 nm to about 500 nm, about 20 nm to about 300 nm, about 20 nm to about 250 nm, about 20 nm to about 200 nm, about 20 nm to about 150 nm, about 20 nm to about 100 nm, about 20 nm to about 80 nm, about 20 nm to about 50 nm, about 20 nm to about nm to about 25 nm, about 50 nm to about 1,000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 250 nm, about 50 nm to about 200 nm, about 50 nm to about 150 nm, about 50 nm to about 100 nm, or about 50 nm to about 80 nm.

[0056] In one or more examples, the silicon oxide layer 160 has a thickness of about 50 nm to about 500 nm, and the nitrogen-rich silicon nitride layer 170 has a thickness of about 1 nm to about 200 nm.

[0057] Figure 2is a schematic diagram of a TFT structure 200 according to one or more embodiments described and discussed herein. TFT structure 200 includes a passivation film stack 158, which includes a silicon oxide layer 160, a nitrogen-rich silicon nitride layer 170, and a third layer 180, wherein the third layer 180 includes silicon nitride and is disposed on the nitrogen-rich silicon nitride layer 170. The third layer 180 can be or include any type of silicon nitride, such as nitrogen-rich silicon nitride, nitrogen-deficient silicon nitride, and / or hydrogen-rich silicon nitride. The silicon and nitrogen in the third layer 180 can have a stoichiometry or Si:N ratio of approximately 1:1, approximately 1:1.1, approximately 1:1.2, approximately 1:1.3, or approximately 3:4. In some examples, the third layer 180 is or includes a hydrogen-rich silicon nitride layer having a greater hydrogen concentration than the nitrogen-rich silicon nitride layer 170. In other examples, the third layer 180 is or includes a nitrogen-rich silicon nitride layer having the same or substantially the same nitrogen concentration as the nitrogen-rich silicon nitride layer 170 .

[0058] The third layer 180 comprising silicon nitride can be deposited by any deposition process, such as one or more thermal and / or plasma vapor deposition processes. Exemplary deposition processes can be or include chemical vapor deposition (CVD), plasma-enhanced CVD (PE-CVD), sputtering, or physical vapor deposition (PVD), or any combination thereof. In some examples, the third layer 180 comprising silicon nitride is deposited by a plasma system, such as a capacitively coupled plasma (CCP) system or an inductively coupled plasma (ICP) system utilizing a high-density plasma (HDP).

[0059] The third layer 180 comprising silicon nitride comprises a composition as described and discussed herein. The nitrogen-rich silicon nitride layer 170 can have a thickness of about 1 nm, about 5 nm, about 10 nm, about 20 nm, about 30 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 800 nm, about 1,000 nm, or more. For example, the third layer 180 including silicon nitride may have a thickness of about 1 nm to about 1,000 nm, about 5 nm to about 1,000 nm, about 5 nm to about 800 nm, about 5 nm to about 500 nm, about 5 nm to about 300 nm, about 5 nm to about 250 nm, about 5 nm to about 200 nm, about 5 nm to about 150 nm, about 5 nm to about 100 nm, about 5 nm to about 80 nm, about 5 nm to about 50 nm, about 5 nm to about 25 nm, about 5 nm to about 15 nm, about 5 nm to about 10 nm, about 20 nm to about 1,000 nm, about 20 nm to about 800 nm, about 20 nm to about 500 nm, about 20 nm to about 300 nm, about 20 nm to about 250 nm, about 20 nm to about 200 nm, about 20 nm to about 150 nm, about 20 nm to about 100 nm, about 20 nm to about 80 nm, about 20 nm to about 50 The present invention also provides a thickness of about 50 nm to about 100 nm, about 20 nm to about 25 nm, about 50 nm to about 1,000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 250 nm, about 50 nm to about 200 nm, about 50 nm to about 150 nm, or about 50 nm to about 100 nm.

[0060] In one or more examples, the silicon oxide layer 160 has a thickness of about 50 nm to about 500 nm, the nitrogen-rich silicon nitride layer 170 has a thickness of about 1 nm to about 200 nm, and the third layer 180 including silicon nitride has a thickness of about 5 nm to about 500 nm.

[0061] Figure 3 FIG2 is a schematic diagram of a TFT structure 300 according to one or more embodiments described and discussed herein. The TFT structure 300 includes a buffer layer 110, a first metal layer 120, and a gate insulating layer 130. The buffer layer 110 is disposed on a substrate 102, the first metal layer 120 is disposed on the buffer layer 110, and the gate insulating layer 130 is disposed on the first metal layer 120 and the buffer layer 110.

[0062] TFT structure 300 further includes a metal oxide layer 140 and an etch stop layer (ESL) 320. Metal oxide layer 140 is disposed on gate insulating layer 130. Etch stop layer 320 is disposed on and above metal oxide layer 140 and on gate insulating layer 130. TFT structure 300 also includes a second or contact metal layer 150 disposed on etch stop layer 320 and metal oxide layer 140. Second or contact metal layer 150 passes through or extends through etch stop layer 320 and contacts metal oxide layer 140 through vias or contact channels.

[0063] The etch stop layer 320 may be or include silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, silicates thereof, nitrides thereof, dopants thereof, or any combination thereof. The etch stop layer 320 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1,000 Å, or about 1,500 Å to about 2,000 Å, about 2,500 Å, about 3,000 Å, about 3,500 Å, about 4,000 Å, or about 5,000 Å. For example, the etch stop layer 320 may have a thickness of about 50 Å to about 5,000 Å, about 100 Å to about 5,000 Å, or about 1,000 Å to about 5,000 Å.

[0064] Silicon oxide layer 160 is disposed on and / or over at least one of second or contact metal layer 150 and etch stop layer 320, or both. For example, silicon oxide layer 160 of passivation film stack 156 is disposed on or over second or contact metal layer 150. Nitrogen-rich silicon nitride layer 170 is disposed on silicon oxide layer 160.

[0065] Figure 4 FIG4 is a schematic diagram of a TFT structure 400 according to one or more embodiments described and discussed herein. TFT structure 400 includes a passivation film stack 158. Passivation film stack 158 includes a silicon oxide layer 160, a nitrogen-rich silicon nitride layer 170, and a third layer 180. Third layer 180, comprising silicon nitride, is disposed on nitrogen-rich silicon nitride layer 170.

[0066] Figure 5is a schematic diagram of a TFT structure 500 according to one or more embodiments described and discussed herein. The TFT structure 500 system includes a buffer layer 110, a metal oxide layer 140, a gate insulating layer 520, and a first or gate metal layer 530. The buffer layer 110 is disposed on the substrate 102, the metal oxide 140 is disposed on the buffer layer 110, the gate insulating layer 520 is disposed on the metal oxide layer 140, and the first or gate metal layer 530 is disposed on the gate insulating layer 520. The gate insulating layer 520 is disposed between the metal oxide layer 140 and the first or gate metal layer 530.

[0067] The gate insulating layer 520 may be or include silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, silicates thereof, nitrides thereof, dopants thereof, or any combination thereof. The gate insulating layer 520 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1,000 Å, or about 1,500 Å to about 2,000 Å, about 2,500 Å, about 3,000 Å, about 3,500 Å, about 4,000 Å, or about 5,000 Å. For example, the gate insulating layer 520 may have a thickness of about 50 Å to about 5,000 Å, about 100 Å to about 5,000 Å, or about 1,000 Å to about 5,000 Å.

[0068] The first or gate metal layer 530 may be or include chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium-molybdenum, copper-molybdenum, alloys thereof, dopants thereof, or any combination thereof. The first or gate metal layer 530 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1,000 Å, about 1,500 Å, or about 2,000 Å to about 2,500 Å, about 3,000 Å, about 4,000 Å, about 5,000 Å, about 8,000 Å, or about 10,000 Å. For example, the first or gate metal layer 530 may have a thickness of about 50 Å to about 10,000 Å, about 500 Å to about 10,000 Å, or about 1,000 Å to about 8,000 Å.

[0069] TFT structure 500 also includes an interlayer dielectric (ILD) layer 540 disposed on and / or over at least one of buffer layer 110, metal oxide layer 140, gate insulation layer 520, and / or first or gate metal layer 530. In one or more examples, interlayer dielectric layer 540 is disposed on at least one of buffer layer 110 and on and over metal oxide layer 140, gate insulation layer 520, and first or gate metal layer 530.

[0070] The interlayer dielectric layer 540 may be or include one, two, or more layers of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, silicates thereof, nitrides thereof, dopants thereof, or any combination thereof. In one or more examples, the interlayer dielectric layer 540 may include a double layer of silicon nitride disposed on silicon oxide. In other examples, the interlayer dielectric layer 540 may include a double layer of silicon oxide disposed on silicon nitride. The intermediate dielectric layer 540 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1,000 Å, about 1,500 Å, or about 2,000 Å to about 2,500 Å, about 3,000 Å, about 4,000 Å, about 5,000 Å, about 8,000 Å, or about 10,000 Å. For example, the intermediate dielectric layer 540 may have a thickness of about 50 Å to about 10,000 Å, about 500 Å to about 10,000 Å, or about 1,000 Å to about 8,000 Å.

[0071] The second or contact metal layer 150 is disposed on the ILD layer 540 and the metal oxide layer 140. The second or contact metal layer 150 passes through or extends through the interlayer dielectric layer 540 and contacts the metal oxide layer 140 through vias or contact channels.

[0072] The silicon oxide layer 160 of the passivation film stack 156 is disposed on at least one of the ILD layer 540 and the second or contact metal layer 150, or both. For example, the silicon oxide layer 160 is disposed on and above the ILD layer 540 and the second or contact metal layer 150. The nitrogen-rich silicon nitride layer 170 is disposed on the silicon oxide layer 160.

[0073] Figure 6 FIG2 is a schematic diagram of a TFT structure 600 according to one or more embodiments described and discussed herein. TFT structure 600 has all the same layers or components as TFT structure 500, but also includes a third metal layer 550 disposed on substrate 102. Buffer layer 110 is disposed on and / or over third metal layer 550 and on substrate 102.

[0074] The third metal layer 550 may be or include chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium-molybdenum, copper-molybdenum, alloys thereof, dopants thereof, or any combination thereof. The third metal layer 550 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1,000 Å, or about 1,500 Å to about 2,000 Å, about 2,500 Å, about 3,000 Å, about 3,500 Å, about 4,000 Å, or about 5,000 Å. For example, the third metal layer 550 may have a thickness of about 50 Å to about 5,000 Å, about 100 Å to about 5,000 Å, or about 1,000 Å to about 5,000 Å.

[0075] Figure 7 is a schematic diagram of a TFT 700 according to one or more embodiments described and discussed herein. Figure 8 7 is a schematic diagram of a TFT 700 according to one or more embodiments described and discussed herein. Each TFT 700, 800 includes at least two nitrogen-rich silicon nitride layers, such as nitrogen-rich silicon nitride layer 170 and a first oxide buffer layer 760 including nitrogen-rich silicon nitride material.

[0076] TFTs 700 and 800 include a buffer layer 710 disposed on substrate 102. The buffer layer 710 comprises one or more low-temperature polysilicon (LTPS) materials. The LTPS material can be or include one or more polysilicon materials, amorphous silicon (α-Si) materials, microcrystalline silicon materials, dopants thereof, or any combination thereof. The buffer layer 710 can have a thickness of approximately 50 Å, approximately 100 Å, approximately 250 Å, approximately 500 Å, approximately 800 Å, approximately 1,000 Å, approximately 1,500 Å, or approximately 2,000 Å to approximately 2,500 Å, approximately 3,000 Å, approximately 4,000 Å, approximately 5,000 Å, approximately 8,000 Å, or approximately 10,000 Å. For example, the buffer layer 710 may have a thickness of about 50 Å to about 10,000 Å, about 500 Å to about 10,000 Å, or about 1,000 Å to about 8,000 Å.

[0077] TFTs 700 and 800 include a polysilicon layer 720, a first gate insulating layer 730, a first metal layer 732, and a first interlayer dielectric (ILD) layer 740. The polysilicon layer 720 is disposed on a buffer layer 710, the first gate insulating layer 730 is disposed on the polysilicon layer 720 and the buffer layer 710, the first metal layer 732 is disposed on the first gate insulating layer 730, and the first interlayer dielectric layer 740 is disposed on at least one of the first metal layer 732 and the first gate insulating layer 730. The polysilicon layer 720 may be or include one or more polysilicon materials, amorphous silicon (α-Si) materials, microcrystalline silicon materials, dopants thereof, or any combination thereof. The polysilicon layer 720 may have a thickness of about 50 Å, about 100 Å, about 250 Å, or about 500 Å to about 600 Å, about 800 Å, about 1,000 Å, about 1,500 Å, about 1,800 Å, or about 2,000 Å. For example, the polysilicon layer 720 may have a thickness of about 50 Å to about 2,000 Å, about 100 Å to about 2,000 Å, or about 500 Å to about 1,500 Å.

[0078] The first gate insulating layer 730 may be or include silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, silicates thereof, nitrides thereof, dopants thereof, or any combination thereof. The first gate insulating layer 730 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1,000 Å, or about 1,500 Å to about 2,000 Å, about 2,500 Å, about 3,000 Å, about 3,500 Å, about 4,000 Å, or about 5,000 Å. For example, the first gate insulating layer 730 may have a thickness of about 50 Å to about 5,000 Å, about 100 Å to about 5,000 Å, or about 1,000 Å to about 5,000 Å.

[0079] The first metal layer 732 may be or include chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium-molybdenum, copper-molybdenum, alloys thereof, dopants thereof, or any combination thereof. The first metal layer 732 may have a thickness of about 100 Å, about 150 Å, about 200 Å, about 250 Å, about 500 Å, about 800 Å, about 1,000 Å, about 1,500 Å, or about 2,000 Å to about 2,500 Å, about 3,000 Å, about 4,000 Å, about 5,000 Å, about 8,000 Å, or about 10,000 Å. For example, the first metal layer 732 may have a thickness of about 100 Å to about 10,000 Å, about 500 Å to about 10,000 Å, or about 1,000 Å to about 8,000 Å.

[0080] The first ILD layer 740 can be or include one, two, or more layers of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, silicates thereof, nitrides thereof, dopants thereof, or any combination thereof. In one or more examples, the first interlayer dielectric layer 740 can include a double layer of silicon nitride disposed on silicon oxide. In other examples, the first ILD layer 740 can include a double layer of silicon oxide disposed on silicon nitride. The first ILD layer 740 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1,000 Å, about 1,500 Å, or about 2,000 Å to about 2,500 Å, about 3,000 Å, about 4,000 Å, about 5,000 Å, about 8,000 Å, or about 10,000 Å. For example, the first ILD layer 740 may have a thickness of about 50 Å to about 10,000 Å, about 500 Å to about 10,000 Å, or about 1,000 Å to about 8,000 Å.

[0081] In one or more embodiments, the TFTs 700 and 800 include an oxide buffer film 756, which includes one or more first oxide buffer layers 760 and one or more second oxide buffer layers 770. The first oxide buffer layer 760 includes a nitrogen-rich silicon nitride material and is disposed on the first ILD layer 740. The second oxide buffer layer 770 includes a silicon oxide material and is disposed on the first oxide buffer layer 760.

[0082] The first oxide buffer layer 760 comprising a nitrogen-rich silicon nitride material has a thickness of about 1 nm, about 5 nm, about 10 nm, about 20 nm, about 30 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 800 nm, about 1,000 nm, or more. For example, the first oxide buffer layer 760 including a nitrogen-rich silicon nitride material may have a thickness of about 1 nm to about 1,000 nm, about 5 nm to about 1,000 nm, about 5 nm to about 800 nm, about 5 nm to about 500 nm, about 5 nm to about 300 nm, about 5 nm to about 250 nm, about 5 nm to about 200 nm, about 5 nm to about 150 nm, about 5 nm to about 100 nm, about 5 nm to about 80 nm, about 5 nm to about 50 nm, about 5 nm to about 25 nm, about 5 nm to about 15 nm, about 5 nm to about 10 nm, about 20 nm to about 1,000 nm, about 20 nm to about 800 nm, about 20 nm to about 500 nm, about 20 nm to about 300 nm, about 20 nm to about 250 nm, about 20 nm to about 200 nm, about 20 nm to about 150 nm, about 20 nm to about 100 nm, about 20 nm to about 80 nm, about 20 nm to about 50 nm, about 20 nm to about 25 nm, about 50 nm to about 1,000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 250 nm, about 50 nm to about 200 nm, about 50 nm to about 150 nm, or about 50 nm to about 100 nm.

[0083] The second oxide buffer layer 770 comprising a silicon oxide material has a thickness of about 1 nm, about 5 nm, about 10 nm, about 20 nm, about 30 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 800 nm, about 1,000 nm or more. For example, the second oxide buffer layer 770 including a silicon oxide material may have a thickness of about 1 nm to about 1,000 nm, about 5 nm to about 1,000 nm, about 5 nm to about 800 nm, about 5 nm to about 500 nm, about 5 nm to about 300 nm, about 5 nm to about 250 nm, about 5 nm to about 200 nm, about 5 nm to about 150 nm, about 5 nm to about 100 nm, about 5 nm to about 80 nm, about 5 nm to about 50 nm, about 5 nm to about 25 nm, about 5 nm to about 15 nm, about 5 nm to about 10 nm, about 20 nm to about 1,000 nm, about 20 nm to about 800 nm, about 20 nm to about 500 nm, about 20 nm to about 300 nm, about 20 nm to about 250 nm, about 20 nm to about 200 nm, about 20 nm to about 150 nm, about 20 nm to about 100 nm, about 20 nm to about 80 nm, about 20 nm to about 50 nm, about 20 nm to about nm to about 25 nm, about 50 nm to about 1,000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 250 nm, about 50 nm to about 200 nm, about 50 nm to about 150 nm, or about 50 nm to about 100 nm.

[0084] In one or more examples, the first oxide buffer layer 760 comprising nitrogen-rich silicon nitride material has a thickness of about 50 nm to about 500 nm, and the second oxide buffer layer 770 comprising silicon oxide material has a thickness of about 5 nm to about 500 nm.

[0085] In both TFTs 700 and 800, the second metal layer 750 contacts the first oxide buffer layer 760 and the polysilicon layer 720. In one or more embodiments of the TFT 700, the second metal layer 750 further contacts the first ILD layer 740, as shown in FIG. Figure 7As shown in . For example, the second metal layer 750 is disposed on the first ILD layer 740, and the first oxide buffer layer 760 comprising nitrogen-rich silicon nitride material is disposed on and / or above the second metal layer 750. In one or more embodiments of the TFT 800, the second metal layer 750 further contacts the second oxide buffer layer 770, as shown in Figure 8 For example, the second metal layer 750 is disposed on the first oxide buffer layer 760 including the nitrogen-rich silicon nitride material, and the second oxide buffer layer 770 is disposed on and / or over the second metal layer 750 .

[0086] TFTs 700 and 800 also include a metal oxide layer 140, a second gate insulating layer, and a third metal gate layer, such as gate metal layer 530. The metal oxide layer 140 is disposed on the second oxide buffer layer 770. The second gate insulating layer is disposed on the metal oxide layer 140, and the third metal gate layer is disposed on the second gate insulating layer. TFTs 700 and 800 further include a second ILD layer, such as ILD layer 540, disposed on at least one of the second oxide buffer layer 770, the metal oxide layer 140, the second gate insulating layer, and the gate metal layer 530.

[0087] like Figure 7 and Figure 8 As further shown, TFTs 700 and 800 include a fourth contact metal layer, such as contact metal layer 150, disposed on second ILD layer 540 and contacting metal oxide layer 140, second metal layer 750, or both. A silicon oxide layer 160 of a passivation film stack 156 is disposed on at least one second ILD layer and on and / or over contact metal layer 150. A nitrogen-rich silicon nitride layer 170 is disposed on silicon oxide layer 160.

[0088] Various embodiments of the present disclosure further relate to any one or more of paragraphs 1-23 below.

[0089] 1. A passivation film stack comprising: a silicon oxide layer disposed on a workpiece; and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 atomic percentage (atomic percentage, at%) to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%.

[0090] 2. A thin film transistor comprising the passivation film stack of paragraph 1, wherein the thin film transistor comprises: a buffer layer disposed on a substrate; a first metal layer disposed on the buffer layer; a gate insulating layer disposed on the first metal layer and the buffer layer; a metal oxide layer disposed on the gate insulating layer; and a second metal layer disposed on the metal oxide layer and the gate insulating layer, wherein the silicon oxide layer of the passivation film stack is disposed on at least one of the second metal layer, the metal oxide layer, and the gate insulating layer.

[0091] 3. The thin film transistor of paragraph 2, wherein the passivation film stack further comprises a hydrogen-rich silicon nitride layer, the hydrogen-rich silicon nitride layer being disposed on the nitrogen-rich silicon nitride layer, and wherein the hydrogen-rich silicon nitride layer has a greater hydrogen concentration than the nitrogen-rich silicon nitride layer.

[0092] 4. A thin film transistor comprising the passivation film stack of paragraph 1, wherein the thin film transistor comprises: a buffer layer disposed on a substrate; a first metal layer disposed on the buffer layer; a gate insulating layer disposed on the first metal layer and the buffer layer; a metal oxide layer disposed on the gate insulating layer; an etch stop layer disposed on the metal oxide layer and the gate insulating layer; and a second metal layer disposed on the etch stop layer and the metal oxide layer, wherein the silicon oxide layer of the passivation film stack is disposed on at least one of the second metal layer and the etch stop layer.

[0093] 5. The thin film transistor of paragraph 4, wherein the passivation film stack further comprises a hydrogen-rich silicon nitride layer, the hydrogen-rich silicon nitride layer being disposed on the nitrogen-rich silicon nitride layer, and wherein the hydrogen-rich silicon nitride layer has a greater hydrogen concentration than the nitrogen-rich silicon nitride layer.

[0094] 6. A thin film transistor comprising the passivation film stack of paragraph 1, wherein the thin film transistor comprises: a buffer layer disposed on a substrate; a metal oxide layer disposed on the buffer layer; a gate insulating layer disposed on the metal oxide layer; a first metal layer disposed on the gate insulating layer; an intermediate dielectric layer disposed on at least one of the buffer layer, the metal oxide layer, the gate insulating layer, and the first metal layer; and a second metal layer disposed on the intermediate dielectric layer and the metal oxide layer, wherein the silicon oxide layer of the passivation film stack is disposed on at least one of the intermediate dielectric layer and the second metal layer.

[0095] 7. The thin film transistor of paragraph 6, further comprising a third metal layer, the third metal layer being disposed on the substrate, wherein the buffer layer is disposed on the third metal layer and the substrate.

[0096] 8. A thin film transistor comprising the passivation film stack of paragraph 1, wherein the thin film transistor comprises: a buffer layer disposed on a substrate, wherein the buffer layer comprises low-temperature polysilicon; a polysilicon layer disposed on the buffer layer; a first gate insulating layer disposed on the polysilicon layer and the buffer layer; a first metal layer disposed on the first gate insulating layer; a first interlayer dielectric layer disposed on at least one of the first metal layer and the first gate insulating layer; a first oxide buffer layer comprising nitrogen-rich silicon nitride, the first oxide buffer layer being disposed on the first interlayer dielectric layer; a second oxide buffer layer comprising silicon oxide, the second oxide buffer layer being disposed on the first oxide layer; a metal oxide layer disposed on the second oxide buffer layer; a second metal layer contacting the first oxide buffer layer and the polysilicon layer; a metal oxide layer disposed on the second oxide buffer layer; a second gate insulating layer disposed on the metal oxide layer; a third metal layer disposed on the second gate insulating layer; a second intermediate dielectric layer disposed on at least one of the second oxide buffer layer, the metal oxide layer, the second gate insulating layer and the third metal layer; and a fourth metal layer disposed on the second intermediate dielectric layer and contacting the metal oxide layer, the second metal layer or both, wherein the silicon oxide layer of the passivation film stack is disposed on at least one of the second intermediate dielectric layer and the fourth metal layer.

[0097] 9. The thin film transistor of paragraph 8, wherein the second metal layer further contacts the first interlayer dielectric layer or the second oxide buffer layer.

[0098] 10. A passivation film stack, comprising: a silicon oxide layer disposed on a workpiece; and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, wherein the nitrogen-rich silicon nitride layer has a thickness of about 1×10 -8 g / m 2 / day to about 1×10 -4 g / m 2 / day and a silicon-hydrogen bonding concentration of about 0.1% to about 10%, and wherein the nitrogen-rich silicon nitride layer has a nitrogen-to-silicon ratio of greater than 1.03 to about 2.

[0099] 11. A method for depositing a silicon nitride material, comprising: heating a workpiece to a temperature of about 200° C. to about 250° C.; exposing the workpiece to a deposition gas during a plasma enhanced chemical vapor deposition process; and depositing a nitrogen-rich silicon nitride layer on the workpiece, wherein the deposition gas comprises a silicon precursor, a nitrogen precursor, and a carrier gas, and wherein a molar ratio of the silicon precursor to the nitrogen precursor to the carrier gas in the deposition gas is about 1: in a range from about 4 to about 8: in a range from about 20 to about 80, respectively.

[0100] 12. The method of paragraph 11, wherein the molar ratio of the silicon precursor to the nitrogen precursor to the carrier gas in the deposition gas is about 1: in the range from about 5 to about 7: in the range from about 30 to about 50, respectively, and wherein the silicon precursor comprises monosilane, the nitrogen precursor comprises ammonia, and the carrier gas comprises nitrogen (N2).

[0101] 13. The method of paragraph 11, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 at % to about 35 at %, a nitrogen concentration of about 40 at % to about 75 at %, and a hydrogen concentration of about 10 at % to about 35 at %, and wherein the nitrogen-rich silicon nitride layer has a nitrogen-to-silicon ratio of greater than 1.03 to about 2.

[0102] 14. The passivation film stack, thin film transistor, and / or method of any of paragraphs 1-13, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of about 27 at % to about 34 at %.

[0103] 15. The passivation film stack, thin film transistor, and / or method of any of paragraphs 1-14, wherein the nitrogen-rich silicon nitride layer has a nitrogen concentration of about 42 at % to about 65 at %.

[0104] 16. The passivation film stack, thin film transistor, and / or method of any of paragraphs 1-15, wherein the nitrogen-rich silicon nitride layer has a hydrogen concentration of about 18 at % to about 25 at %.

[0105] 17. The passivation film stack, thin film transistor, and / or method of any of paragraphs 1-16, wherein the nitrogen-rich silicon nitride layer has a nitrogen-to-silicon ratio of greater than 1.03 to about 2.

[0106] 18. The passivation film stack, thin film transistor, and / or method of any of paragraphs 1-17, wherein the nitrogen-rich silicon nitride layer has a silicon-hydrogen bond concentration of about 0.5% to about 6%.

[0107] 19. The passivation film stack, thin film transistor, and / or method of any of paragraphs 1-18, wherein the nitrogen-rich silicon nitride layer has a total hydrogen bonding concentration of less than 30%.

[0108] 20. The passivation film stack, thin film transistor, and / or method of any of paragraphs 1-19, wherein the nitrogen-rich silicon nitride layer has a thickness of about 1×10 -8 g / m 2 / day to about 1×10 -4 g / m 2 / day water resistance rate.

[0109] 21. The passivation film stack, thin film transistor, and / or method of any of paragraphs 1-20, wherein the nitrogen-rich silicon nitride layer has a thickness of about 1 nm to about 500 nm.

[0110] 22. The passivation film stack, thin film transistor, and / or method of any of paragraphs 1-21, wherein the silicon oxide layer has a thickness of about 50 nm to about 1,000 nm.

[0111] 23. The passivation film stack, thin film transistor, and / or method of any of paragraphs 1-22, further comprising a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, wherein the hydrogen-rich silicon nitride layer has a greater hydrogen concentration than the nitrogen-rich silicon nitride layer.

[0112] Although the above is directed to multiple embodiments of the disclosure, multiple other and further embodiments can be devised without departing from the basic scope of the disclosure, and the scope of the disclosure is determined by the appended claims. All documents described herein are incorporated by reference, including any priority documents and / or testing procedures that are not inconsistent with this document. It will be clear from the foregoing general description and multiple specific embodiments that although multiple forms of the disclosure have been illustrated and described, various modifications can be made without departing from the spirit and scope of the disclosure. Therefore, it is not intended that the disclosure be limited thereby. Similarly, for purposes of U.S. law, the term "comprising" is deemed to be synonymous with the term "including". Likewise, when a component, element, or group of elements is preceded by the transitional phrase "comprising," we should understand that we also contemplate the same component or group of elements when the transitional phrase "consisting essentially of," "consisting of," "selected from the group of consisting of," or "is" is preceded by the recited component, element, or elements, and vice versa.

[0113] A number of specific embodiments and features are described using a set of numerical upper limits and a set of numerical lower limits. It should be understood that, unless otherwise indicated, ranges including combinations of any two values ​​are contemplated, for example, including combinations of any lower value and any higher value, combinations of any two lower values, and / or combinations of any two higher values. Specific lower limits, upper limits, and ranges are set forth in one or more of the accompanying claims.

Claims

1. A passivation film stack comprising: a silicon oxide layer disposed on the workpiece; and a nitrogen-rich silicon nitride layer, disposed on the silicon oxide layer; The nitrogen-rich silicon nitride layer has a silicon concentration of 20 atomic percent (at%) to 35 at%, a nitrogen concentration of 40 at% to 75 at%, and a hydrogen concentration of 10 at% to 35 at%.

2. The passivation film stack of claim 1 , wherein the nitrogen-rich silicon nitride layer has a silicon concentration of 27 at % to 34 at %, a nitrogen concentration of 42 at % to 65 at %, and a hydrogen concentration of 18 at % to 25 at %, and wherein the nitrogen-rich silicon nitride layer has a nitrogen-to-silicon ratio of 1.03 to 2. 3 . The passivation film stack of claim 1 , wherein the nitrogen-rich silicon nitride layer has a silicon-hydrogen bonding concentration of 0.5% to 6%. 4 . The passivation film stack of claim 1 , wherein the nitrogen-rich silicon nitride layer has a total hydrogen bonding concentration of less than 30%.

5. The passivation film stack according to claim 1, wherein the nitrogen-rich silicon nitride layer has a thickness of 1×10 -8 g / m 2 / day to 1×10 -4 g / m 2 / day water resistance rate. The passivation film stack of claim 1 , wherein the nitrogen-rich silicon nitride layer has a thickness of 1 nm to 500 nm. 7 . The passivation film stack of claim 1 , wherein the silicon oxide layer has a thickness of 50 nm to 1,000 nm. 8 . The passivation film stack of claim 1 , further comprising a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, wherein the hydrogen-rich silicon nitride layer has a greater hydrogen concentration than the nitrogen-rich silicon nitride layer.

9. A thin film transistor comprising the passivation film stack according to claim 1, wherein the thin film transistor comprises: a buffer layer disposed on the substrate; a first metal layer, disposed on the buffer layer; a gate insulating layer, disposed on the first metal layer and the buffer layer; a metal oxide layer, disposed on the gate insulating layer; and a second metal layer, disposed on the metal oxide layer and the gate insulating layer; The silicon oxide layer of the passivation film stack is disposed on at least one of the second metal layer, the metal oxide layer, and the gate insulating layer. 10 . The thin film transistor of claim 9 , wherein the passivation film stack further comprises a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, and wherein the hydrogen-rich silicon nitride layer has a greater hydrogen concentration than the nitrogen-rich silicon nitride layer.

11. A thin film transistor comprising the passivation film stack according to claim 1, wherein the thin film transistor comprises: a buffer layer disposed on the substrate; a first metal layer, disposed on the buffer layer; a gate insulating layer, disposed on the first metal layer and the buffer layer; a metal oxide layer, disposed on the gate insulating layer; an etching stop layer, disposed on the metal oxide layer and the gate insulating layer; and a second metal layer disposed on the etch stop layer and the metal oxide layer; The silicon oxide layer of the passivation film stack is disposed on at least one of the second metal layer and the etch stop layer.

12. The thin film transistor of claim 11, wherein the passivation film stack further comprises a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, and wherein the hydrogen-rich silicon nitride layer has a greater hydrogen concentration than the nitrogen-rich silicon nitride layer.

13. A thin film transistor comprising the passivation film stack according to claim 1, wherein the thin film transistor comprises: a buffer layer disposed on the substrate; a metal oxide layer, disposed on the buffer layer; a gate insulating layer, disposed on the metal oxide layer; A first metal layer is disposed on the gate insulating layer; an intermediate dielectric layer, disposed on at least one of the buffer layer, the metal oxide layer, the gate insulating layer, and the first metal layer; and a second metal layer disposed on the intermediate dielectric layer and the metal oxide layer; The silicon oxide layer of the passivation film stack is disposed on at least one of the intermediate dielectric layer and the second metal layer. 14 . The thin film transistor according to claim 13 , further comprising a third metal layer, wherein the third metal layer is disposed on the substrate, and wherein the buffer layer is disposed on the third metal layer and the substrate.

15. A thin film transistor comprising the passivation film stack according to claim 1, wherein the thin film transistor comprises: a buffer layer disposed on the substrate, wherein the buffer layer comprises low-temperature polysilicon; a polysilicon layer, disposed on the buffer layer; a first gate insulating layer, disposed on the polysilicon layer and the buffer layer; a first metal layer, disposed on the first gate insulating layer; a first intermediate dielectric layer disposed on at least one of the first metal layer and the first gate insulating layer; a first oxide buffer layer comprising nitrogen-rich silicon nitride, wherein the first oxide buffer layer is disposed on the first intermediate dielectric layer; a second oxide buffer layer comprising silicon oxide, wherein the second oxide buffer layer is disposed on the first oxide buffer layer; a second metal layer contacting the first oxide buffer layer and the polysilicon layer; a metal oxide layer, disposed on the second oxide buffer layer; a second gate insulating layer, disposed on the metal oxide layer; a third metal layer, disposed on the second gate insulating layer; a second interlayer dielectric layer disposed on at least one of the second oxide buffer layer, the metal oxide layer, the second gate insulating layer, and the third metal layer; and a fourth metal layer disposed on the second intermediate dielectric layer and contacting the metal oxide layer, the second metal layer, or both; The silicon oxide layer of the passivation film stack is disposed on at least one of the second interlayer dielectric layer and the fourth metal layer. 16 . The thin film transistor of claim 15 , wherein the second metal layer further contacts the first interlayer dielectric layer or the second oxide buffer layer.

17. A passivation film stack comprising: a silicon oxide layer disposed on the workpiece; and a nitrogen-rich silicon nitride layer, disposed on the silicon oxide layer; The nitrogen-rich silicon nitride layer has a 1×10 -8 g / m 2 / day to 1×10 -4 g / m 2 / day water resistivity and a silicon-hydrogen bond concentration of 0.1% to 10%; and The nitrogen-rich silicon nitride layer has a nitrogen-to-silicon ratio of 1.03 to 2.

18. A method for depositing a silicon nitride material, comprising: Heating the workpiece to a temperature of 200°C to 250°C; exposing the workpiece to a deposition gas during a plasma enhanced chemical vapor deposition process; and depositing a nitrogen-rich silicon nitride layer on the workpiece; The nitrogen-rich silicon nitride layer has a 1×10 -8 g / m 2 / day to 1×10 -4 g / m 2 Water resistance rate per day, wherein the deposition gas comprises a silicon precursor, a nitrogen precursor and a carrier gas; and The molar ratios of the silicon precursor to the nitrogen precursor to the carrier gas in the deposition gas are 1: in the range of 4 to 8: in the range of 20 to 80, respectively.

19. The method of claim 18, wherein the molar ratio of the silicon precursor to the nitrogen precursor to the carrier gas in the deposition gas is 1: in the range of 5 to 7: in the range of 30 to 50, respectively, and wherein the silicon precursor comprises monosilane, the nitrogen precursor comprises ammonia, and the carrier gas comprises nitrogen (N2).

20. The method of claim 18, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of 20 at% to 35 at%, a nitrogen concentration of 40 at% to 75 at%, and a hydrogen concentration of 10 at% to 35 at%, and wherein the nitrogen-rich silicon nitride layer has a nitrogen-to-silicon ratio of 1.03 to 2.

21. The method of claim 18, wherein the plasma has an RF power of 800 W to 2,400 W.

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