Ferroelectric Transistor and Assembly Comprising the Ferroelectric Transistor

Abstract

Some embodiments include a ferroelectric transistor having a first electrode and a second electrode. The second electrode is offset from the first electrode by up to an active region. A transistor gate is along a portion of the active region. The active region includes a first source / drain region adjacent to the first electrode, a second source / drain region adjacent to the second electrode, and a body region between the first and second source / drain regions. The body region includes a gated channel region adjacent to the transistor gate. The active region includes at least one barrier between the second electrode and the gated channel region that is penetrable by electrons but not by holes. A ferroelectric material is between the transistor gate and the gated channel region.

Description

[0001] Related patent data

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 892,117, filed on Aug. 27, 2019, entitled “Ferroelectric Transistors and Assemblies Comprising Ferroelectric Transistors,” the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Ferroelectric transistors and assemblies comprising ferroelectric transistors. Background Art

[0004] Memory is a type of integrated circuit system and is used in a computer system to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be written to or read using digital lines (which may also be referred to as bit lines, data lines, sense lines, or data / sense lines) and access lines (which may also be referred to as word lines). Digital lines can conductively interconnect memory cells along the columns of the array, and access lines can conductively interconnect memory cells along the rows of the array.

[0005] Memory cells can be volatile or non-volatile. Non-volatile memory cells can store data for long periods of time, including when the computer is turned off. Volatile memory dissipates and thus needs to be refreshed / rewritten, many times per second in many instances. In any case, memory cells are configured to store or hold memory in at least two different selectable states. In a binary system, the states are considered “0” or “1”. In other systems, at least some individual memory cells can be configured to store information of more than two levels or states.

[0006] Ferroelectric field effect transistors (FeFETs) can be used as memory cells. Specifically, an FeFET can have two selectable memory states corresponding to two different polarization modes of the ferroelectric material within the FeFET. The different polarization modes can be characterized by, for example, different threshold voltages (V T ) or different channel conductivities at a selected operating voltage. The ferroelectric polarization mode of an FeFET can be retained (at least for a measurable duration) in the absence of power.

[0007] One type of ferroelectric transistor is a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistor. This has a gate dielectric (insulator I) between a metal (M) and a semiconductor substrate (S). It also has a ferroelectric (F) material adjacent to the metal and a gate (usually including metal M) adjacent to the ferroelectric material. In operation, an electric field across the ferroelectric material is used to switch the ferroelectric material from one polarization mode to another. The ferroelectric transistor includes a pair of source / drain regions and a channel region between the source / drain regions. The conductivity across the channel region is affected by the polarization mode of the ferroelectric material.

[0008] Another type of ferroelectric transistor is a metal-ferroelectric-insulator-semiconductor (MFIS), where the ferroelectric material is in direct contact with the insulator (i.e., where there is no intervening metal between the ferroelectric material and the insulator).

[0009] The channel region can be considered to be contained within the body region of the ferroelectric transistor. During a programming operation, carriers (holes and electrons) migrate in and out of the body region.

[0010] There is a desire to develop ferroelectric transistors that can be programmed quickly and that can be upgraded according to increasing levels of integration. It has proven difficult to achieve the desired quick programming with conventional ferroelectric transistor configurations.

[0011] It would be desirable to develop new ferroelectric transistors that address the above problems and to develop new memory array architectures using such transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagrammatic cross-sectional view of a region of an example assembly.

[0013] Figure 2 and 3 is Figure 1 a diagrammatic cross-sectional view of an enlarged region of the assembly of.

[0014] Figure 3A ILLUSTRATIVE DESCRIPTION Figure 3 shows the relationship between the conduction band and the valence band of the materials shown in.

[0015] Figures 4 to 6 is a diagrammatic cross-sectional view of a region of an example assembly at various programming stages of Figure 1 is a diagrammatic cross-sectional view of a region of an example assembly at various programming stages of

[0016] Figure 7 is a schematic view of a region of an example memory array.

[0017] Figures 8 to 10 is a diagrammatic cross-sectional view of a region of an example assembly.

[0018] Figure 11 is a diagrammatic cross-sectional side view of a region of an example assembly including stacked levels. Detailed Implementation Modes

[0019] One problem with some embodiments that involve identifying conventional ferroelectric transistors is that the body region of such transistors can "float" and thus be isolated from the carrier (hole or electron) source, leading to the floating body effect (FBE).

[0020] The floating body effect can be problematic during programming operations. The speed-limiting factor for a programming operation can be the rate at which carriers are refreshed within the body region of the transistor, and this rate is reduced due to the floating body effect.

[0021] Some embodiments include an arrangement in which the active region of a ferroelectric transistor extends between two electrodes. Electrons can pass between either of the electrodes and the active region, but due to the presence of one or more hole barrier structures, holes are permitted to travel back and forth between only one of the electrodes. Holes can be effectively supplied from the one of the electrodes during a write operation (specifically, a write-0 operation) to enable high-speed programming. However, since holes are supplied from only one of the electrodes, the ferroelectric transistor can operate in a manner such that the holes do not interfere with the read operation. Refer to Figures 1 to 11 to describe example embodiments.

[0022] Refer to Figure 1 , the integrated assembly 10 includes a ferroelectric transistor 14 supported by a substrate 12.

[0023] The substrate 12 can include a semiconductor material and can (for example) include single-crystalline silicon, consist essentially of single-crystalline silicon, or consist of single-crystalline silicon. The substrate 12 can be referred to as a semiconductor substrate. The term "semiconductor substrate" means any structure including a semiconducting material, which includes (but is not limited to) bulk semiconducting materials such as semiconducting wafers (alone or in assemblies including other materials) and semiconducting material layers (alone or in assemblies including other materials). The term "substrate" refers to any support structure, including (but not limited to) the aforementioned semiconductor substrates. In some applications, the substrate 12 can correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials can include (for example) one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

[0024] A gap is provided between the substrate 12 and the ferroelectric transistor 14 to indicate that in some embodiments, other materials, circuit components, etc. can be provided between the substrate and the ferroelectric transistor 14.

[0025] The ferroelectric transistor 14 includes an active region 16 that extends vertically between a pair of electrodes 30 and 32. The electrodes 30 and 32 can be referred to as the first and second electrodes, the bottom and top electrodes, the lower and upper electrodes, etc., respectively.

[0026] The electrodes 30 and 32 respectively include conductive materials 34 and 36. The conductive materials 34 and 36 may include any suitable conductive composition, for example (by way of example) one or more of various metals (such as titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.) and / or metal-containing compositions (such as metal silicides, metal nitrides, metal carbides, etc.). The conductive materials 34 and 36 may include the same composition as each other, or may include different compositions from each other.

[0027] The active region 16 includes a first (or lower) source / drain region 18, a second (or upper) source / drain region 20, and a body region (or channel region) 22 between the source / drain regions 18 and 20. In the illustrated embodiment, the active region 16 extends perpendicular to the substrate 12 (i.e., the electrodes 30 and 32 are vertically offset relative to each other). In other embodiments, the active region may have a different configuration relative to the substrate 12 (i.e., the electrodes 30 and 32 may be horizontally offset relative to each other).

[0028] The lower source / drain region 18 is shown to directly abut the bottom electrode 30, and the upper source / drain region 20 is shown to directly abut the upper electrode 32.

[0029] The active region 16 includes two different semiconductor materials 38 and 40 joined at an interface 41. The semiconductor materials 38 and 40 may be referred to as the first and second semiconductor materials, respectively.

[0030] In some embodiments, the interface 41 may be configured to be penetrable with respect to electron migration and non-penetrable with respect to hole migration. Thus, the interface 41 may be configured as a hole barrier structure 42. In such embodiments, the first and second semiconductor materials 38 and 40 may be selected to have conduction bands that are similar in energy to each other and valence bands that are offset in energy relative to each other (as discussed in more detail below with reference to Figure 3A ).

[0031] In some embodiments, the first semiconductor material 38 may include a semiconductor oxide. The semiconductor oxide may include any suitable composition, and in some embodiments may contain one or more of indium, zinc, tin, and gallium. For example, the semiconductor oxide may include a composition having a combination of oxygen and tin, consisting essentially of or consisting of said composition. This composition may be represented as SnO, where the chemical formula indicates the main component rather than a specific stoichiometry. In some embodiments, the semiconductor oxide may contain dopants (such as one or more of hydrogen, magnesium, yttrium, fluorine, etc.).

[0032] In some embodiments, the second semiconductor material 40 may comprise, consist essentially of, or consist of a semiconductor composition that includes a combination of at least one element from Group 13 of the periodic table and at least one element from Group 15 of the periodic table. For example, such semiconductor composition may include one or more of the following: GaP, AlAs, GaAs, AlP, InP, AlSb, GaAlAs, GaInAs, GaInP, etc., where the chemical formula indicates the main components rather than a specific stoichiometry. In some specific embodiments, the second semiconductor material may comprise, consist essentially of, or consist of a composition that includes a combination of gallium and phosphorus (e.g., GaP, where the chemical formula indicates the main components rather than a specific stoichiometry). In some embodiments, the second semiconductor material 40 may contain dopants (e.g., one or more elements selected from Group 14 of the periodic table, such as (by way of example) one or more of silicon, carbon, and germanium), which are incorporated into a semiconductor composition that includes elements from Groups 13 and 15 of the periodic table.

[0033] A dashed line 19 is provided to show the approximate boundary of the lower source / drain region 18. The upper boundary may be in any suitable location within the active region 16 and corresponds to the region where the doping within the active region 16 transitions from the source / drain region doping associated with region 18 to the lighter doping associated with the body region 22. In some embodiments, the source / drain region 18 may be heavily doped with an n-type dopant.

[0034] Example locations of the lower boundary of the upper source / drain region 20 are indicated by lines 21a to c. Dashed lines 21a and 21b are provided to show that the lower boundary of the upper source / drain region 20 may be above or below the interface 41. The interface is labeled 21c to indicate that the interface itself may correspond to the lower boundary of the upper source / drain region 20.

[0035] In some embodiments, the upper semiconductor material 40 may be heavily doped with an n-type dopant and may correspond to the upper source / drain region 20. For example, the semiconductor material 40 may include silicon doped with an n-type dopant (e.g., phosphorus) to a concentration of at least about 10 19 atoms / cm 3 . In embodiments where the upper semiconductor material 40 is heavily doped with an n-type dopant, the interface 37 between the doped semiconductor material 40 and the metal-containing electrode 36 may correspond to the hole barrier structure 44; and specifically, may be a junction that is penetrable by electrons but not by holes.

[0036] In some embodiments, both the hole barrier structures 42 and 44 may be incorporated into the ferroelectric transistor. In other embodiments, one of the hole barrier structures may be omitted. In still other embodiments, more than the two hole barrier structures illustrated may be utilized.

[0037] Although Figure 1 is configured to have a structure that is a hole barrier but electronically penetrable, one of ordinary skill in the art will recognize that a similar configuration can be formed by a barrier that is not electronically penetrable while being hole penetrable. Specifically, electrons and holes are identified as carrier types. Generally speaking, Figure 1 the ferroelectric transistor is configured to have one or more barriers that are penetrable by one of the carrier types (e.g., electrons) while not penetrable by the other carrier type (e.g., holes).

[0038] Figure 1 The ferroelectric transistor 14 includes an insulating material 24 extending along a body region 22, includes a ferroelectric material 26 adjacent to the insulating material, and includes a conductive gate material 28 adjacent to the ferroelectric material.

[0039] The insulating material 24 can include any suitable composition and, in some embodiments, can include silicon dioxide, consist essentially of silicon dioxide, or consist of silicon dioxide.

[0040] The ferroelectric material 26 can include any suitable composition and can (e.g.) include one or more materials, consist essentially of the one or more materials, or consist of the one or more materials, the one or more materials selected from the group consisting of transition metal oxides, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconate titanate, tantalum oxide, and barium strontium titanate and having a dopant including one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium, and rare earth elements. The ferroelectric material can be provided in any suitable configuration, e.g., (by way of example) a single homogeneous material or a stack of two or more discrete separated materials.

[0041] The conductive material 28 can include any suitable conductive composition, e.g., (by way of example) one or more of the following: various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, the conductive material 28 can be a metal-containing material, e.g., (by way of example) a material including one or more of titanium nitride, tungsten nitride, tungsten, titanium, etc.

[0042] The vertically extending active region 16 has a pair of opposing sidewalls 17 along the Figure 1 cross-section thereof. The sidewalls 17 extend along the body region 22, the upper source / drain region 20, and the lower source / drain region 18.

[0043] The insulating material 24 is along the opposing sidewalls 17, and the ferroelectric material 26 and the conductive gate material 28 can also be considered to be along such sidewalls. The materials 24, 26, and 28 can have any suitable vertical dimension relative to the illustrated active region 16. The insulating material 24 can extend along the entire sidewall 17 or can extend along only a portion of such sidewall. The ferroelectric material 26 can or cannot vertically extend beyond the conductive gate material 28. The conductive gate material 28 can or cannot overlap with the interface where the body region 22 is joined to the source / drain regions 18 and 20.

[0044] The conductive gate material 28 can be considered to be configured as a transistor gate (conductive gate) 46. The transistor gate directly overlaps a portion (section, region) 48 of the active region 16, and such portion can be considered to be adjacent to the gated channel region adjacent to the transistor gate 46. In the illustrated embodiment, the first semiconductor material 38 extends from the upper surface 31 of the first electrode 30 across the first source / drain region 18 and across the gated channel region 48. The second semiconductor material 40 extends from the first semiconductor material 38 to the lower surface 33 of the second electrode 32. The second semiconductor material 40 can or cannot completely extend across the source / drain region 20, depending on the position of the boundary 21 of the source / drain region 20 relative to the interface between the first and second semiconductor materials 38 and 40.

[0045] The insulating material 51 is shown to extend around the transistor gate 46. The insulating material 51 can include any suitable composition and, in some embodiments, can include silicon dioxide, consist essentially of silicon dioxide, or consist of silicon dioxide.

[0046] The ferroelectric transistor 14 can be used as a memory cell 50 of a memory array 52. In such applications, the conductive gate material 28 can be coupled to a word line WL-1, the upper electrode 32 can be coupled to a first comparison digit line DL-1T, and the lower electrode 30 can be coupled to a second comparison digit line DL-1C. The comparison digit lines DL-1T and DL-1C extend to a sense amplifier 54. The comparison digit lines DL-1T and DL-1C can be considered to correspond to a set of paired digit lines (DL-1T / DL-1C). The set includes a true digit line (DL-1T) and a complementary digit line (DL-1C). The terms "true" and "complementary" are arbitrary. The electrical values of the true and complementary digit lines of the set are utilized together during read / write operations of the memory cell (e.g., 50) associated with the set. In some embodiments, the true comparison digit line (DL-1T) can be referred to as the first comparison digit line, and the complementary comparison digit line (DL-1C) can be referred to as the second comparison digit line.

[0047] Figure 2 and 3 shown Figure 1 The enlarged region of the memory cell 50 to illustrate a specific configuration of the hole barrier structures 44 and 42.

[0048] Reference Figure 2 , this shows a configuration in which the semiconductor material 40 is heavily doped with an n-type dopant (i.e., n+ doping). For example, the semiconductor material 40 may comprise silicon doped with an n-type dopant (such as phosphorus) to a concentration of at least about 10 19 atoms / cm 3 , and in some embodiments, doped with an n-type dopant to a concentration of at least about 10 20 atoms / cm 3 , or even at least about 10 22 atoms / cm 3 . The hole barrier structure 44 may correspond to the interface between the metal-containing material 36 and the n-type doped semiconductor material 40.

[0049] Reference Figure 3 and 3A , this shows a configuration in which the hole barrier structure 42 corresponds to the interface between two semiconductor materials 38 and 40, the semiconductor materials 38 and 40 being configured to have conduction bands (CBs) that are substantially matched (aligned) in energy such that electrons can readily be transferred between the materials 38 and 40 and valence bands (VBs) that are offset in energy relative to each other such that holes are substantially prevented from being transferred from the semiconductor material 40 to the semiconductor material 38. Figure 3A The offset between the valence bands of the materials 38 and 40 is shown as ΔE, which may be at least about 0.5 volts in some embodiments.

[0050] Figures 4 to 6 Illustrates an example operating mode of the memory cell 50.

[0051] Reference Figure 4 , the memory cell 50 may be programmed to a first memory state (a so-called "1" state) by operating the word line WL-1 and the digital line group DL-1T / DL-1C to form electrons 56 (only some of which are labeled) in the active region 16. The electrons may be provided from either or both of the electrodes 30 and 32 by providing an electrical bias between the word line (WL-1) and either or both of the electrodes 30 and 32. The electrons 56 may be considered to be pumped from one or both of the metal-containing electrodes 30 and 32 into the channel region 48 of the body region 22 (labeled in Figure 1 ). The memory state "1" may be considered to correspond to a state in which holes are depleted in the body region 22.

[0052] Reference Figure 5, the memory cell 50 can be programmed to a second memory state (the so-called "0" state) by operating the word line WL-1 and the digital line group DL-1T / DL-1C to replenish holes 58 (only some of which are marked) in the body region 22. An electrical bias can be provided between the word line WL-1 and the bottom electrode 30; and the holes 58 can be regarded as being pumped from the metal-containing bottom electrode 30 into the channel region 48 of the body region 22 (marked in Figure 1 ). The holes will not flow from the metal-containing top electrode 32 into the body region 22 due to the presence of one or both of the hole barrier structures 42 and 44. Since the holes are provided by the metal-containing structure 30, the above-mentioned floating body effect can be avoided; and the "write 0" operation can occur at a high programming speed.

[0053] Reference Figure 6 , the memory cell 50 can be read by providing an electrical bias between the top and bottom electrodes 30 and 32 and a voltage on the word line WL-1. Electrons can easily flow across the active region 16 (from the source to the drain) because the barrier structures 42 and 44 can be penetrated by electrons. In some embodiments, the above write operation can be regarded as bipolar (i.e., using both electrons and holes), and the read operation is not bipolar because it only uses electrons. Since electrons are not inhibited by the barrier structures 42 and 44, the "read window" is not adversely affected by using the configuration described herein.

[0054] In some embodiments, Figure 1 the ferroelectric transistor 14 and the memory cell 50 can be regarded as representing many substantially identical structures across the memory array 52. The first and second comparison digital lines Dl-1T and DL-1C together are a paired group DL-1T / DL-1C, which can represent many substantially identical paired groups of the first and second comparison digital lines across the memory array. The word line WL-1 can represent many substantially identical word lines across the memory array. The term "substantially identical" means identical within reasonable manufacturing and measurement tolerances. An example memory array 52 is referenced Figure 7 described.

[0055] The memory array 52 includes a plurality of memory cells 50, each of which includes a ferroelectric transistor 14. Word lines WL-1 and WL-2 are coupled to a driver 60 (i.e., a word line driver) and extend along the rows of the memory array. Digital line pairs DL-1T / DL-1C and DL-2T / DL-2C extend along the columns of the memory array. True (i.e., first) comparison digital lines DL-1T and DL-2T are coupled to a digital line driver 62, and complementary (i.e., second) comparison digital lines DL-1C and DL-2C are coupled to a circuitry 64, which can be a driver circuitry or a reference source (the reference source can be any suitable structure that holds any suitable reference voltage, such as ground, VCC / 2, etc.). Each of the memory cells 50 is uniquely addressed by a combination of one of the word lines and one of several sets of first and second comparison digital lines.

[0056] The true and complementary comparison digital lines (e.g., DL-1T and DL-1C) of each pair of digital lines (e.g., DL-1T / DL-1C) are electrically coupled to a device 54. This device 54 can be a sense amplifier for comparing the electrical properties of the true digital line (e.g., DL-1T) with the electrical properties of the comparison digital line (e.g., DL-1C) during a read operation. Alternatively or additionally, the device 54 can be used to impart desired electrical properties to the true and complementary comparison digital lines (e.g., DL-1T and DL-1C) during a programming (i.e., write) operation. Although two pairs of digital lines (e.g., DL-1T / DL-1C and DL-2T / Dl-2C) are shown as extending to the same device 54, in other embodiments, one of the digital line sets can extend to a device different from the other set.

[0057] Figure 1 The ferroelectric material 26 of the ferroelectric transistor 14 can be utilized in an MFMIS configuration, an MFIS configuration, or any other suitable configuration. Figures 8 to 10 Illustrate several example configurations.

[0058] Figure 8 Shows a configuration in which the ferroelectric material 26 is within a stack 70 (a so-called MFM stack) that includes a pair of ferroelectric materials between metallic materials 72 and 74. Dashed lines are used to diagrammatically illustrate the approximate boundaries between the various materials within the stack 70. The metallic materials 72 and 74 can include any suitable metal or metal-containing composition, including, for example, one or more of tungsten, titanium, titanium nitride, etc. In some embodiments, the metallic material 72 can be referred to as an intermediate conductive material between the ferroelectric material 26 and the insulating material 24.

[0059] Figure 9 Shows a configuration similar to Figure 8 except that the stack 70 only includes the metallic material 74 and the ferroelectric material 26. Figure 9The configuration can be considered an instance of the MFIS configuration.

[0060] Figure 10 Illustrate a configuration where the ferroelectric material 26 is the only material between the insulating material 24 and the conductive gate material 28. The conductive gate material 28 can include a metal adjacent to the ferroelectric material 26, and thus, Figure 10 can be considered another instance of the MFIS configuration. It should be noted that Figure 9 and 10 are substantially the same configuration, where the only difference is whether the metal of the MFIS configuration is defined as part of the gate material 28 or instead defined as part of a separate stack 70. Similarly, Figure 8 the MFMIS configuration of

[0061] In some embodiments, the memory array 52 can be within a memory tier (i.e., a memory plane) within a tier (or level) in a vertically stacked arrangement. For example, Figure 11 illustrate a portion of an integrated assembly 10b that includes tiers 80, 82, 84, and 86 in a vertically stacked arrangement (also labeled as tiers 1 to 4). The vertically stacked arrangement can extend upward to include additional tiers. Tiers 1 to 4 can be considered examples of levels stacked on top of each other. The levels can be within different semiconductor dies, or at least two of the levels can be within the same semiconductor die. The tiers can all be contained within a single semiconductor package.

[0062] The bottom tier (tier 1) can include control circuitry and / or sensing circuitry (e.g., can include word line drivers, sense amplifiers, etc.), and in some applications can include CMOS circuitry, and / or can include memory circuitry. The upper tiers (tiers 2 to 4) can include a memory array (e.g., (by way of example) the memory array 52), and / or can include control circuitry or other logic circuitry. If the memory array is within multiple tiers, then the memory arrays within each tier can be the same as or different from each other.

[0063] The ferroelectric transistors described herein are example configurations. The embodiments described herein can be adapted for use in other ferroelectric transistors having other geometries, other channel configurations, and / or other channel materials.

[0064] The assemblies and structures discussed above can be used within an integrated circuit, where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate, and can be incorporated into an electronic system. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and specialized modules, and can include multi-layer multi-chip modules. The electronic system can be any of a variety of systems, such as, for example, a camera, a wireless device, a display, a chipset, a set-top box, a gaming console, a lighting device, a vehicle, a clock, a television, a mobile phone, a personal computer, an automobile, an industrial control system, an aircraft, etc.

[0065] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0066] The terms "dielectric" and "insulating" can be used to describe materials having insulating electrical properties. In the present disclosure, these terms are considered synonyms. The use of the term "dielectric" in some examples and the term "insulating" (or "electrically insulating") in other examples can provide a variation in language within the present disclosure to simplify the antecedent basis within the appended claims and is not used to indicate any significant chemical or electrical differences.

[0067] Both the terms "electrically connected" and "electrically coupled" can be used in the present disclosure. These terms are considered synonyms. The use of one term in some examples and the other term in other examples can provide a variation in language within the present disclosure to simplify the antecedent basis within the appended claims.

[0068] The specific orientation of each embodiment in the figures is for illustration only, and the embodiments can be rotated relative to the shown orientation in some applications. The description provided herein and the appended claims relate to any structure having the described relationships between various features, whether the structure is in the specific orientation of the figures or rotated relative to this orientation.

[0069] Unless otherwise indicated, the cross-sectional views of the accompanying description only show the features in the plane of the cross-section and do not show the materials behind the plane of the cross-section in order to simplify the figures.

[0070] When a structure is referred to above as "on another structure", "adjacent to another structure", or "against another structure", it can be directly on the other structure or there can also be an intervening structure. In contrast, when a structure is referred to as "directly on another structure", "directly adjacent to another structure", or "directly against another structure", there is no intervening structure. The terms "directly below", "directly above", etc. do not indicate direct physical contact (unless otherwise expressly specified), but rather indicate vertical alignment.

[0071] A structure (such as a layer, material, etc.) may be referred to as "vertically extending" to indicate that the structure generally extends upward from a bottom substrate (such as a substrate). The vertically extending structure may or may not extend substantially orthogonally to the upper surface of the substrate.

[0072] Some embodiments include a ferroelectric transistor having a first electrode and a second electrode offset from the first electrode by up to an active region. A transistor gate is along a portion of the active region. The active region includes a first source / drain region adjacent to the first electrode, a second source / drain region adjacent to the second electrode, and a body region between the first and second source / drain regions. The body region includes a gated channel region adjacent to the transistor gate. The active region includes at least one barrier between the second electrode and the gated channel region that can be penetrated by electrons but not by holes. A ferroelectric material is between the transistor gate and the gated channel region.

[0073] Some embodiments include an integrated assembly that includes a ferroelectric transistor. The ferroelectric transistor includes an active region that vertically extends between a first electrode and a second electrode. The active region includes a first source / drain region proximate to the first electrode, a second source / drain region proximate to the second electrode, and a body region between the first and second source / drain regions. The ferroelectric transistor includes a conductive gate proximate to a section of the body region. The section is a gated channel region. The active region includes a first semiconductor composition that extends from a surface of the first electrode across the first source / drain region and across the gated channel region. The active region includes a second semiconductor composition that extends from the first semiconductor composition to a surface of the second electrode. The first semiconductor composition includes a semiconductor oxide, and the second semiconductor composition is compositionally different from the first semiconductor composition. A first comparison digital line is coupled to the first source / drain region. A second comparison digital line is coupled to the second source / drain region.

[0074] Some embodiments include an integrated assembly that includes a ferroelectric transistor. The ferroelectric transistor includes a vertically extending active region. The active region includes a first source / drain region, a second source / drain region, and a body region between the first and second source / drain regions. The active region includes two different semiconductor materials joined at an interface that is penetrable by a first type of charge carrier and not penetrable by a second type of charge carrier. One of the first and second types of charge carriers is an electron and the other of the first and second types of charge carriers is a hole. The active region has a pair of opposing sidewalls along a cross-section. A first electrode is proximate to the first source / drain region. A second electrode is proximate to the second source / drain region. Insulating material is along each of the opposing sidewalls. Ferroelectric material is adjacent to the insulating material. Conductive gate material is adjacent to the ferroelectric material. A portion of the active region overlaps with the conductive gate material and is a gated portion of the active region. The first semiconductor material abuts directly against the first electrode and extends across the first source / drain region and the gated portion of the active region. The second semiconductor material abuts directly against the second electrode and extends from the first semiconductor material to the second electrode. A first comparison digital line is coupled to the first electrode. A second comparison digital line is coupled to the second electrode.

[0075] Subject matter disclosed herein has been described in language more or less specific to structural and method features. However, it is to be understood that the claims are not limited to the specific features shown and described, since the means disclosed herein include example embodiments. Accordingly, the claims are to be accorded full scope in literal sense and construed appropriately under the doctrine of equivalents.

Claims

1. A ferroelectric transistor, which comprises: a first electrode; a second electrode offset from the first electrode across an active region; a transistor gate along a portion of the active region; the active region including a first source / drain region adjacent to the first electrode, a second source / drain region adjacent to the second electrode, and a body region between the first and second source / drain regions; the body region including a gated channel region adjacent to the transistor gate; the active region including at least one barrier between the second electrode and the gated channel region that is penetrable by electrons but not by holes; and a ferroelectric material between the transistor gate and the gated channel region.

2. The ferroelectric transistor according to claim 1, wherein the at least one barrier comprises a semiconductor heterojunction in which a first semiconductor material is in direct contact with a second semiconductor material; the first and second semiconductor materials have first and second conduction bands respectively and first and second valence bands respectively; the first and second conduction bands are substantially energy-aligned with each other, and the first and second valence bands are offset from each other by at least about 0.5 volts.

3. The ferroelectric transistor according to claim 2, wherein the first semiconductor material is a semiconductor oxide, and wherein the second semiconductor material comprises a combination of at least one element from Group 13 of the periodic table and at least one element from Group 15 of the periodic table.

4. The ferroelectric transistor according to claim 3, wherein the second semiconductor material comprises one or more of GaP, AlAs, GaAs, AlP, InP, AlSb, GaAlAs, GaInAs, GaInP; where the chemical formula indicates the main components rather than a specific stoichiometry.

5. The ferroelectric transistor according to claim 4, wherein the second semiconductor material further comprises one or more of silicon, carbon, and germanium.

6. The ferroelectric transistor according to claim 4, wherein the first semiconductor material comprises one or more of indium, zinc, tin, and gallium.

7. The ferroelectric transistor according to claim 6, wherein the first semiconductor material further comprises one or more of hydrogen, magnesium, yttrium, and fluorine.

8. The ferroelectric transistor according to claim 2, wherein the first semiconductor material comprises SnO, where the chemical formula indicates the main components rather than a specific stoichiometry; and wherein the second semiconductor material comprises GaP, where the chemical formula indicates the main components rather than a specific stoichiometry.

9. The ferroelectric transistor according to claim 1, wherein the at least one barrier comprises a junction in which a heavily n-type doped semiconductor material is in direct contact with another material.

10. The ferroelectric transistor according to claim 1, wherein the source / drain regions are n-type semiconductor materials; the first and second electrodes comprise metals; and the at least one barrier comprises a junction in which the n-type semiconductor material of the second source / drain region is in direct contact with the metal of the second electrode.

11. An integrated assembly, which comprises: a ferroelectric transistor; The ferroelectric transistor includes an active region that extends vertically between a first electrode and a second electrode; The active region includes a first source / drain region adjacent to the first electrode, a second source / drain region adjacent to the second electrode, and a body region between the first and second source / drain regions; the ferroelectric transistor includes a conductive gate adjacent to a section of the body region, and the section is a gated channel region; the active region includes a first semiconductor composition that extends from the surface of the first electrode across the first source / drain region and across the gated channel region; The active region includes a second semiconductor composition that extends from the first semiconductor composition to the surface of the second electrode; the first semiconductor composition includes a semiconductor oxide, and the second semiconductor composition is compositionally different from the first semiconductor composition; the active region includes at least one barrier between the second electrode and the gated channel region that can be penetrated by electrons but not by holes; A first comparison digital line that is coupled to the first source / drain region; and A second comparison digital line that is coupled to the second source / drain region.

12. The integrated assembly according to claim 11, wherein the first and second semiconductor compositions are joined at an interface, and wherein the interface is a boundary of the second source / drain region.

13. The integrated assembly according to claim 11, wherein the first and second semiconductor compositions are joined at an interface, and wherein the interface is not a boundary of the second source / drain region.

14. The integrated assembly according to claim 11, wherein the second semiconductor material is n-type and includes an n-type dopant at a concentration of at least about 10 19 atoms / cm 3 of the concentration.

15. The integrated assembly according to claim 11, wherein the second semiconductor material includes n-type silicon.

16. The integrated assembly according to claim 11, wherein the second semiconductor material includes a combination of at least one element from Group 13 of the periodic table and at least one element from Group 15 of the periodic table.

17. The integrated assembly according to claim 11, wherein the second semiconductor material includes one or more of GaP, AlAs, GaAs, AlP, InP, AlSb, GaAlAs, GaInAs, GaInP; wherein the chemical formula indicates the main component rather than a specific stoichiometry.

18. The integrated assembly according to claim 11, wherein the first semiconductor material includes an oxide, and the oxide includes one or more of indium, zinc, tin, and gallium.

19. The integrated assembly according to claim 11, wherein one of the first and second source / drain regions is an upper source / drain region and the other of the first and second source / drain regions is a lower source / drain region; and wherein the ferroelectric transistor includes, along a cross-section : A pair of opposing sidewalls that extend along the body region, the upper source / drain region, and the lower source / drain region; Insulating material that extends along each of the opposing sidewalls; Ferroelectric material that is adjacent to the insulating material; And The conductive gate that is adjacent to the ferroelectric material.

20. The integrated assembly according to claim 19, wherein: The ferroelectric transistor is one of a number of substantially identical ferroelectric transistors within a memory array and corresponding to a memory cell; The conductive gate is coupled to a word line that is one of a number of substantially identical word lines; The first and second comparison digit lines together are a paired group of first and second comparison digit lines, where the paired group is one of a number of substantially identical paired groups of first and second comparison digit lines; and Each of the memory cells is uniquely addressed by a combination of one of the word lines and one of the paired groups of first and second comparison digit lines.

21. The integrated assembly according to claim 20, wherein the first and second comparison digit lines of each paired group are coupled to a sense amplifier.

22. The integrated assembly according to claim 20, wherein the memory array is within a tier in a vertically stacked arrangement of tiers.

23. An integrated assembly, which comprises: A ferroelectric transistor; The ferroelectric transistor comprises: A vertically extending active region that includes a first source / drain region, a second source / drain region, and a body region between the first and second source / drain regions; the active region includes a first semiconductor material and a second semiconductor material, where the first semiconductor material and the second semiconductor material are two different semiconductor materials joined at an interface that is penetrable by a first type of charge carrier and not penetrable by a second type of charge carrier, where one of the first and second types of charge carriers is an electron and the other of the first and second types of charge carriers is a hole; the active region has a pair of opposing sidewalls along a cross-section; A first electrode proximate to the first source / drain region; A second electrode proximate to the second source / drain region; Insulating material along each of the opposing sidewalls; Ferroelectric material adjacent to the insulating material; Conductive gate material adjacent to the ferroelectric material; A portion of the active region overlapping with the conductive gate material is the gated portion of the active region; The first semiconductor material abuts directly against the first electrode and extends across the first source / drain region and the gated portion of the active region; and The second semiconductor material abuts directly against the second electrode and extends from the first semiconductor material to the second electrode; A first comparison digit line coupled to the first electrode; and A second comparison digit line coupled to the second electrode.

24. The integrated assembly according to claim 23, wherein each of the first and second electrodes comprises a metal abutting directly against the active region.

25. The integrated assembly according to claim 23, wherein the first type of charge carrier is an electron and the second type of charge carrier is a hole.

26. The integrated assembly according to claim 25, wherein the second semiconductor material includes n-type silicon.

27. The integrated assembly according to claim 25, wherein the second semiconductor material includes a combination of at least one element from Group 13 of the periodic table and at least one element from Group 15 of the periodic table.

28. The integrated assembly according to claim 25, wherein the second semiconductor material comprises one or more of GaP, AlAs, GaAs, AlP, InP, AlSb, GaAlAs, GaInAs, GaInP; wherein the chemical formula indicates the main components rather than a specific stoichiometry.

29. The integrated assembly according to claim 25, wherein the first semiconductor material comprises an oxide, and the oxide comprises one or more of indium, zinc, tin, and gallium.

30. The integrated assembly according to claim 25, wherein the first semiconductor material comprises SnO, wherein the chemical formula indicates the main components rather than a specific stoichiometry; and wherein the second semiconductor material comprises GaP, wherein the chemical formula indicates the main components rather than a specific stoichiometry.

31. The integrated assembly according to claim 23, wherein: the ferroelectric transistor is within a memory array and is one of a number of substantially identical ferroelectric transistors corresponding to memory cells; the conductive gate material is coupled to a word line that is one of a number of substantially identical word lines; the first and second comparison digit lines together are a paired group of the first and second comparison digit lines, wherein the paired group is one of a number of substantially identical paired groups of the first and second comparison digit lines; and each of the memory cells is uniquely addressable by a combination of one of the word lines and one of the paired groups of the first and second comparison digit lines.

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