An MCU+FPGA control platform suitable for standardized feeder terminals

Abstract

The present invention relates to an MCU+FPGA control platform suitable for a standardized feeder terminal, comprising an MCU chip, an FPGA chip, an SDRAM chip, an Ethernet PHY chip, an Ethernet MAC+PHY chip, a NAND FLASH chip, a WDG watchdog chip, an ADC chip, an RTC chip, and a FLASH chip; the MCU chip communicates with the Ethernet PHY chip, the Ethernet MAC+PHY chip, and the NAND FLASH chip respectively, and the MCU end has an external WDG watchdog chip; the FPGA chip communicates with the ADC chip, and the FPGA end has an external RTC, which communicates with the FLASH chip via SPI; the MCU chip writes a configuration program into the FPGA external FLASH via the JTAG interface of the FPGA. The control platform of the present invention can fully meet the requirements of the primary and secondary equipment integration standardization specifications for feeder terminal equipment.

Description

Technical Field

[0001] The present invention relates to the technical field of power distribution automation equipment, and in particular to an MCU+FPGA control platform suitable for a standardized feeder terminal. Background Art

[0002] The integration and standardization of primary and secondary equipment in the field of distribution automation will become the mainstream development trend of various types of distribution terminal equipment in the future. Its standardized design principles put forward higher requirements and challenges for the scalability, flexibility and real-time performance of the existing terminal control platform. Most of the mainstream feeder terminal (FTU) equipment manufacturers on the market currently use a control platform based on a single MCU, which has the following shortcomings:

[0003] (1) The IO pin resources are limited and cannot meet the growing differentiated demand for digital input and output of feeder terminal equipment, resulting in poor scalability.

[0004] (2) Communication interface resources are limited and cannot meet the compatibility requirements of new wireless communications such as 5G, Bluetooth, WIFI, LoRa, etc., and have poor flexibility.

[0005] (3) The new feeder terminal has high requirements for real-time functions such as ADC sampling speed, Beidou / GPS timing accuracy, digital telemetering resolution, and digital remote control export delay. In addition, the functions of the operating system and application software are becoming increasingly powerful, which is also a great challenge to the performance of the single-core MCU.

[0006] FPGA, with its fast speed and strong flexibility, just makes up for the lack of performance and resources of a single MCU control platform. At this stage, domestic FPGA alternatives are becoming increasingly mature and the market price is relatively stable, which also effectively controls the hardware cost of single-core platform expansion.

[0007] Currently, there are two main communication methods between MCU and FPGA: serial port and parallel port. The serial port communication method greatly limits the speed of FPGA and is not suitable for the power distribution field with high real-time and reliability requirements. The parallel port communication has better speed and reliability, but occupies more IO pins. If a large-capacity parallel port memory is connected at the same time, the IO port resources of the MCU will be greatly consumed, which greatly reduces the cost-effectiveness of expanding the dual-core platform.

[0008] The patent document with the authorization publication number CN205141828U discloses a hood-type FTU power distribution terminal hardware platform based on DSP MK60. The published hardware platform adopts DSPK60 as the main control chip and uses 12-bit on-chip AD to collect AC quantity. Its transient and steady-state accuracy cannot meet the requirements of standardization specifications; the SRAM and the second extended Ethernet port of the platform are both implemented by parallel port communication, which consumes a large amount of IO port resources, resulting in the need for external CPLD to implement functions such as remote control export, remote signal entry, switch, LED, etc., which invisibly increases the design difficulty and hardware cost; a large number of complex analog quantity calculations are completed inside the MCU, which greatly slows down the platform's response speed to real-time operations; the platform's external communication interface is relatively fixed and cannot be compatible with new external communication equipment.

[0009] Therefore, a high-performance, scalable and flexible control platform suitable for standardized feeder terminals deserves in-depth study. Summary of the invention

[0010] In order to solve the existing technical problems, the present invention provides an MCU+FPGA control platform suitable for a standardized feeder terminal.

[0011] The specific contents of the present invention are as follows: an MCU+FPGA control platform suitable for a standardized feeder terminal, comprising an MCU chip, an FPGA chip, an SDRAM chip, an Ethernet PHY chip, an Ethernet MAC+PHY chip, a NAND FLASH chip, a WDG watchdog chip, an ADC chip, an RTC chip, and an FPGA external expansion FLASH chip;

[0012] The MCU chip communicates with the Ethernet PHY chip, the Ethernet MAC+PHY chip, and the NAND FLASH chip respectively, and the MCU end is externally connected with a WDG watchdog chip;

[0013] The FPGA chip communicates with the ADC chip, and the FPGA has an external RTC that communicates with the FLASH chip via SPI;

[0014] The MCU chip writes the configuration program into the FPGA external FLASH through the FPGA's JTAG interface;

[0015] The MCU communicates with the FPGA and SDRAM respectively through the FSMC controller bus multiplexing method.

[0016] Furthermore, the MCU communicates with the Ethernet PHY chip through the RMII bus, the MCU communicates with the Ethernet MAC+PHY chip through SPI, and the MCU communicates with the NAND FLASH chip through SPI; the FPGA communicates with the external 16-bit ADC chip through the parallel port bus, and the FPGA communicates with the external FLASH through SPI.

[0017] Furthermore, the JTAG pin of the FPGA is connected to the IO pin of the MCU. The MCU directly writes the configuration data into the SPI flash of the FPGA plug-in by simulating the JTAG interface timing of the FPGA. The FPGA adopts the MSPI configuration mode for loading.

[0018] Furthermore, the FPGA bus adopts PSRAM asynchronous mode, no burst, no waiting, data / address line multiplexing, and the initialization process includes:

[0019] fmc_addr_en=((!fpga_cs_ne1)&fpga_nl_nadv); / / enable address validity

[0020] assign fmc_wr_en=((!fpga_cs_ne1)&(!fpga_wr_nwe)&fpga_nl_nadv); / / write enable is valid

[0021] assign fmc_rd_en=((!fpga_cs_ne1)&(!fpga_rd_noe)&fpga_nl_nadv); / / Read enable is valid.

[0022] Furthermore, the MCU and SDRAM communicate through the 13-bit address bus A[12:0] and 16-bit data bus D[15:0] of the FSMC.

[0023] The MCU and FPGA communicate through the 16-bit data / address multiplexed bus AD[15:0] of the FSMC. D[15:0] and AD[15:0] share the 16 IO ports of the MCU.

[0024] The PSRAM mode control pins FSMC_NE1, FSMC_NOE, FSMC_NWE, and FSMC_NL of FSMC are connected to the IO ports of FPGA respectively.

[0025] The SDRAM mode control pins FSMC_NBL0, FSMC_NBL1, FSMC_SDNWE, FSMC_SDNCAS, FSMC_SDNRAS, FSMC_SDNE0, and FSMC_BA[1:0] of the FSMC are respectively connected to the UDQM, LDQM, WE, CAS, RAS, CS, and BA[1:0] pins of the external SDRAM chip.

[0026] Furthermore, the MCU chip uses ST's STM32F429ZGT6 or the domestic GigaDevice's GD32F450ZET6.

[0027] Furthermore, the FPGA uses Xilinx's XC6SLX25, or domestic Anlu Technology's EG4X20BG256.

[0028] Furthermore, the SDRAM uses Winbond's W9825G6KH-6I, or ISSI's IS42S16800F-7TLI.

[0029] The MCU+FPGA control platform of the present invention has a significant improvement in overall performance, scalability, flexibility, and real-time performance compared to a single MCU platform, and can fully meet the requirements of the primary and secondary equipment integration standardization specifications for feeder terminal equipment. The multiplexing method of the communication bus effectively saves the IO port resources of the main chip while ensuring fast and reliable communication between the MCU and SDRAM and FPGA. The method of directly configuring the FPGA by the MCU can also effectively reduce the production process and improve production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The specific implementation of the present invention will be further explained below in conjunction with the accompanying drawings.

[0031] Figure 1 It is the overall block diagram of the control platform of the present invention;

[0032] Figure 2 It is a schematic diagram of the communication bus interface of the present invention;

[0033] Figure 3 This is a schematic diagram of the MCU bus interface of the present invention;

[0034] Figure 4 This is a schematic diagram of the SDRAM bus interface of the present invention;

[0035] Figure 5 This is a schematic diagram of the FPGA bus interface of the present invention. DETAILED DESCRIPTION

[0036] like Figure 1As shown, an MCU+FPGA control platform suitable for a standardized feeder terminal mainly includes: an MCU chip, an FPGA chip, an SDRAM chip, an Ethernet PHY chip, an Ethernet MAC+PHY chip, a NAND FLASH chip, a WDG watchdog chip, an ADC chip, an RTC chip, and an FPGA external FLASH chip.

[0037] The MCU has a built-in MAC, and a 100M Ethernet PHY chip is connected to the RMII bus to generate a network port. The MCU uses a high-speed SPI to connect a 100M Ethernet MAC+PHY chip to expand another network port to meet the communication requirements of the two network ports of the standardized FTU. The MCU uses a large-capacity NAND FLASH to expand through the serial port, which mainly stores file systems, recording files, etc. The MCU has an external independent hardware watchdog chip. The FPGA communicates with the external 16-bit ADC chip through the parallel bus and function pins, and the relevant AC analog quantity calculation is completed on the FPGA side to reduce the MCU workload and ensure the speed of analog signal acquisition. The FPGA has an external RTC and Beidou / GPS. The FPGA synchronizes the Beidou / GPS second time to the RTC, and then sends the accurate time to the MCU to meet the standardized specification requirements of the Beidou / GPS mode that the time error is no more than 5ms. The FPGA external SPI FLASH is used to store the configuration program.

[0038] like Figure 2 As shown in the figure, the JTAG pin of FPGA is connected to the IO of MCU, and MCU simulates the JTAG interface of FPGA to directly write the configuration data into the SPI flash of FPGA external plug-in. FPGA adopts MSPI configuration mode for loading. This design can save the process of using emulator to burn program to FPGA in production process, and can use the Ethernet port of platform to download configuration program to FPGA directly through MCU to improve production efficiency.

[0039] like Figure 2 As shown in the figure, the MCU communicates with the FPGA and SDRAM respectively through the FSMC controller bus multiplexing method. Among them, the MCU and SDRAM communicate through the 13-bit address bus A[12:0] and 16-bit data bus D[15:0] of the FSMC. The MCU and FPGA communicate through the 16-bit data / address multiplexing bus AD[15:0] of the FSMC. D[15:0] and AD[15:0] share the 16 IO ports of the MCU. This multiplexing method greatly saves the IO port resources of the two main chips. The 16-bit address bus of the FPGA can completely cover the number of its internal storage units.

[0040] like Figure 2As shown in the figure, the PSRAM mode control pins FSMC_NE1, FSMC_NOE, FSMC_NWE, and FSMC_NL of FSMC are connected to the IO ports of FPGA respectively, and the SDRAM mode control pins FSMC_NBL0, FSMC_NBL1, FSMC_SDNWE, FSMC_SDNCAS, FSMC_SDNRAS, FSMC_SDNE0, and FSMC_BA[1:0] of FSMC are connected to the UDQM, LDQM, WE, CAS, RAS, CS, and BA[1:0] pins of the external SDRAM chip respectively. The bus interface of MCU, SDRAM, and FPGA is shown in the figure. Figure 3-Figure 5 shown.

[0041] The FPGA bus uses PSRAM asynchronous mode, no burst, no waiting, data / address line multiplexing, and its initialization process is:

[0042] fpga_cs_ne1 / / Chip select, low effective

[0043] fpga_wr_nwe / / write enable, low effective

[0044] fpga_nl_nadv / / Address enable, low effective

[0045] fpga_rd_noe / / read enable, low effective

[0046] fpga_db[15:0] / / address data multiplexing

[0047] Enable address validity:

[0048] fmc_addr_en=((!fpga_cs_ne1)&fpga_nl_nadv);

[0049] Write enable is valid:

[0050] wire fmc_wr_en;

[0051] assign fmc_wr_en=((!fpga_cs_ne1)&(!fpga_wr_nwe)&fpga_nl_nadv);

[0052] wire[15:0]Din;

[0053] assign Din = fpga_db;

[0054] Read enable is valid:

[0055] wire fmc_rd_en;

[0056] assign fmc_rd_en=((!fpga_cs_ne1)&(!fpga_rd_noe)&fpga_nl_nadv);

[0057] reg[15:0]rd_data_reg;

[0058] assign fpga_db=fmc_rd_en? rd_data_reg:16'hzzzz;

[0059] FPGA has abundant IO port resources, and both remote signaling and remote control functions can be realized on the FPGA side. The remote signaling function cooperates with RTC and Beidou / GPS to accurately record the time information of digital quantity changes, which can meet the standardized specification requirements of 5ms remote signaling resolution. The remote control output also benefits from the low latency characteristics of FPGA, effectively shortening the action time of remote control opening and closing.

[0060] The MCU chip of this control platform can be ST's STM32F429ZGT6, or GD32F450ZET6 made by GigaDevice. The FPGA can be Xilinx's XC6SLX25, or EG4X20BG256 made by Anlu Technology. The SDRAM can be Winbond's W9825G6KH-6I, or ISSI's IS42S16800F-7TLI.

[0061] The MCU+FPGA control platform suitable for standardized feeder terminals in this embodiment has two Ethernet ports expanded by RMII and SPI respectively, and a large-capacity FLASH expanded by a high-speed serial port. FPGA interacts with an external 16-bit ADC through a parallel bus to complete the acquisition and calculation of AC analog quantities, and externally plugs in RTC and Beidou / GPS for time synchronization operations. MCU communicates with FPGA and SDRAM respectively through bus multiplexing, and MCU directly writes the configuration program into the FPGA external Flash for FPGA initialization configuration. The control platform of the present invention can effectively save the IO port resources occupied by the communication bus, and has a significant improvement in overall performance, scalability, flexibility, and real-time performance compared to a single MCU platform. It can fully meet the requirements of the primary and secondary equipment integration standardization specifications for feeder terminal equipment. The way in which MCU directly configures FPGA can also reduce production processes and improve production efficiency.

[0062] Many specific details are described in the above description to facilitate a full understanding of the present invention. However, the above description is only a preferred embodiment of the present invention. The present invention can be implemented in many other ways different from those described herein, so the present invention is not limited to the specific implementation disclosed above. At the same time, any person familiar with the art can make many possible changes and modifications to the technical solution of the present invention using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. An MCU+FPGA control platform suitable for standardized feeder terminals, characterized in that: Including MCU chip, FPGA chip, SDRAM chip, Ethernet PHY chip, Ethernet MAC+PHY chip, NAND FLASH chip, WDG watchdog chip, ADC chip, RTC chip, FPGA external expansion FLASH chip; The MCU chip communicates with the Ethernet PHY chip, the Ethernet MAC+PHY chip, and the NAND FLASH chip respectively, and the MCU end is externally mounted with a WDG watchdog chip; The FPGA chip communicates with the ADC chip, and the FPGA has an external RTC that communicates with the FLASH chip via SPI; The MCU chip writes the configuration program into the FPGA external FLASH through the FPGA's JTAG interface; The MCU communicates with the FPGA and SDRAM respectively through the FSMC controller bus multiplexing method.

2. The MCU+FPGA control platform applicable to the standardized feeder terminal according to claim 1, characterized in that: The MCU communicates with the Ethernet PHY chip through the RMII bus, the MCU communicates with the Ethernet MAC+PHY chip through SPI, and the MCU communicates with the NAND FLASH chip through SPI; the FPGA communicates with the external 16-bit ADC chip through the parallel port bus, and the FPGA communicates with the external FLASH through SPI.

3. The MCU+FPGA control platform applicable to the standardized feeder terminal according to claim 1, characterized in that: The JTAG pin of the FPGA is connected to the IO pin of the MCU. The MCU directly writes the configuration data into the SPI flash of the FPGA plug-in by simulating the JTAG interface timing of the FPGA. The FPGA uses the MSPI configuration mode for loading.

4. The MCU+FPGA control platform applicable to the standardized feeder terminal according to claim 1, characterized in that: The FPGA bus uses PSRAM asynchronous mode, no burst, no waiting, data / address line multiplexing, and the initialization process includes: fmc_addr_en = ((!fpga_cs_ne1) & fpga_nl_nadv); assign fmc_wr_en = ((!fpga_cs_ne1) & (!fpga_wr_nwe) & fpga_nl_nadv); assign fmc_rd_en = ((!fpga_cs_ne1) & (!fpga_rd_noe) & fpga_nl_nadv).

5. The MCU+FPGA control platform applicable to the standardized feeder terminal according to claim 1, characterized in that: The MCU and SDRAM communicate through the 13-bit address bus A[12:0] and 16-bit data bus D[15:0] of the FSMC. The MCU and FPGA communicate through the 16-bit data / address multiplexed bus AD[15:0] of the FSMC. D[15:0] and AD[15:0] share the 16 IO ports of the MCU. The PSRAM mode control pins FSMC_NE1, FSMC_NOE, FSMC_NWE, and FSMC_NL of FSMC are connected to the IO ports of FPGA respectively. The SDRAM mode control pins FSMC_NBL0, FSMC_NBL1, FSMC_SDNWE, FSMC_SDNCAS, FSMC_SDNRAS, FSMC_SDNE0, and FSMC_BA[1:0] of the FSMC are respectively connected to the UDQM, LDQM, WE, CAS, RAS, CS, and BA[1:0] pins of the external SDRAM chip.

6. The MCU+FPGA control platform applicable to the standardized feeder terminal according to claim 1, characterized in that: The MCU chip uses ST's STM32F429ZGT6 or China's GigaDevice's GD32F450ZET6.

7. The MCU+FPGA control platform applicable to the standardized feeder terminal according to claim 1, characterized in that: The FPGA uses Xilinx's XC6SLX25, or domestic Anlu Technology's EG4X20BG256.

8. The MCU+FPGA control platform applicable to the standardized feeder terminal according to claim 1, characterized in that: The SDRAM uses Winbond's W9825G6KH-6I, or ISSI's IS42S16800F-7TLI.

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