Non-volatile magnetic random storage structure and non-volatile magnetic random memory

Abstract

The application discloses a nonvolatile magnetic random storage structure and a nonvolatile magnetic random memory, wherein the storage structure comprises at least one storage unit, the storage unit comprises a first storage body, a second storage body and a switching transistor; and the magnetization states of the first storage body and the second storage body are opposite. The first end of the first storage body and the first end of the second storage body are respectively connected with the drain of the switching transistor. The second end of the first storage body is connected with a first bit line, and the second end of the second storage body is connected with a second bit line and is respectively connected to a reading circuit. The gate of the switching transistor is connected with a word line, the source of the switching transistor is connected with a source line, and the source line is connected with a first voltage generator. The scheme connects two storage bodies with opposite magnetization states in parallel, utilizes the small area proportion of the storage body, and uses one storage body as a judgment unit and the other as a reference unit, so that the influence of a single reference current on a drift current is avoided, and the sensitivity of judgment is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a non-volatile magnetic random access memory structure and a non-volatile magnetic random access memory. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a type of non-volatile magnetic random access memory. It possesses the high-speed read and write capabilities of Static Random Access Memory (SRAM) and the high integration density of Dynamic Random Access Memory (DRAM), making it a promising memory type as semiconductor device manufacturing processes continue to shrink.

[0003] Existing non-volatile magnetic random access memory (MRMH) structures typically consist of a magnetic tunnel junction (MTJ) and a transistor, i.e., a structure consisting of a magnetic tunnel junction and a transistor. Specifically, for example... Figure 1a As shown, the storage cell of the non-volatile magnetic random access memory (MRAM) includes a storage bank 02 and a three-stage transistor 05 connected to each storage bank 02. M=1 indicates that the bias voltage circuit corresponds to one storage bank 02, and M=2 indicates that the bias voltage circuit corresponds to two storage banks 02. Each storage bank 02 is connected to its corresponding bit line address selector 03 and bit line voltage clamp 04, and then connected to the non-inverting or inverting input of the comparator amplifier 01. The gate of the transistor 05 is connected to the word line (WL) of the chip, responsible for selecting the MRAM storage cell. The MTJ and the transistor 05 are connected in series on the bit line (BL) of the chip for read and write operations. When several MRAM storage cells form a storage cell array, the word line of each MRAM storage cell extends along the row of the storage cell, and the bit line extends along the column of the storage cell. Each MRAM storage cell is located at the intersection of the word line and the bit line.

[0004] refer to Figure 2 In the prior art, the memory cells of multiple non-volatile magnetic random access memories can be arranged into a memory cell array. The gate G of the three-stage transistor 05 corresponding to the memory bank 02 in each row is connected to the word line WL of each row; the source S of the three-stage transistor 05 corresponding to the memory bank 02 in each column is connected to the source line SL of each column; one end of the memory bank 02 in each column is connected to the bit line BL of each column.

[0005] The memory cell stores information using the magnetization direction, and the magnetization of each memory cell exhibits one of two stable directions, namely the parallel direction and the anti-parallel direction, which are the logical variables "0" and "1". The magnetization direction affects the resistance of the memory cell. If the magnetization direction is parallel, the resistance of the memory cell is R; if the magnetization direction is anti-parallel, the resistance of the memory cell is R + △R. Therefore, the logical state of the memory cell can be read out by the resistance of the memory cell.

[0006] The specific read process of MRAM is as follows: Apply a voltage to the word line crossing the selected memory cell, and at the same time read the current of the bit line, then the resistance state of the memory cell can be read out. The read current (Is) is the ratio of the read voltage (Vs) to the resistance of the selected memory cell. The read current can be converted into a voltage. By comparing the data voltage (Vdata) with the reference voltage (Vref), the resistance state of the selected memory cell can be determined. When Vdata > Vref, the logical value of the selected memory cell is "0"; when Vdata < Vref, the logical value is "1".

[0007] Due to the limitations of device volume and process, the existing MRAM memory cells have a low resistance ratio in the high-resistance state and the low-resistance state, resulting in a small window for the sense amplifier to distinguish the two states, and thus a small judgment margin. This causes the problem of slow read speed. Especially in a memory cell array containing multiple memory cells, using a fixed reference cell as the comparison benchmark, due to the influence of the drift current on the memory cells, it will affect the accuracy of judgment.

[0008] For a traditional sense amplifier, the reference resistance is selected as the average value of the high-resistance state and the low-resistance state, and the overall judgment margin depends on the smaller gap current (the difference between the smaller one of the currents in the low-resistance state or the high-resistance state and the reference current). That is to say, only this part of the smaller gap current is used to judge the resistance state, and the other parts are lost.

[0009] Selecting an appropriate reference cell can increase the reference resistance of the high and low resistance states, but if a larger judgment margin is desired, the read time still needs to be increased.

[0010] Therefore, there is a need to propose a memory cell that can improve the judgment margin when judging the high and low resistance states of MRAM. Summary of the Invention

[0011] The purpose of the present invention is to solve the problem that the judgment margin is low when judging the high and low resistance states of MRAM in the prior art. The present invention provides a non-volatile magnetic random storage structure and a non-volatile magnetic random memory, which can improve the judgment margin when judging the high and low resistance states of the non-volatile magnetic random memory.

[0012] To address the aforementioned technical problems, embodiments of the present invention disclose a non-volatile magnetic random access memory structure, comprising at least one memory cell, wherein the memory cell includes a first memory bank, a second memory bank, and a switching transistor; wherein the magnetization states of the first memory bank and the second memory bank are opposite.

[0013] The first terminal of the first memory bank and the first terminal of the second memory bank are respectively connected to the drain of the switching transistor;

[0014] The second end of the first memory cell is connected to the first bit line, and the second end of the second memory cell is connected to the second bit line, and both are connected to the read circuit.

[0015] The gate of the switching transistor is connected to the word line, the source of the switching transistor is connected to the source line, and the source line is connected to the first voltage generator.

[0016] According to another specific embodiment of the present invention, the non-volatile magnetic random access memory structure disclosed in the embodiment of the present invention has a first memory cell and a second memory cell, both of which are magnetic tunnel junctions, and the first end is a fixed layer and the second end is a free layer.

[0017] According to another specific embodiment of the present invention, the non-volatile magnetic random access memory structure disclosed in this embodiment includes a memory cell array composed of a plurality of memory cells; wherein,

[0018] In the memory cell array, the gates of the switching transistors in each row of memory cells are connected to the word lines of that row; and,

[0019] In the memory cell array, the source of the switching transistor in each column of memory cells is connected to the source line of each column; and,

[0020] In a storage cell array, the first end of the storage cell in each column is connected to the bit line of each column.

[0021] According to another specific embodiment of the present invention, the non-volatile magnetic random access memory structure disclosed in the embodiment of the present invention uses an NMOS transistor as the switching transistor.

[0022] The present invention also discloses a non-volatile magnetic random access memory, including a non-volatile magnetic random access memory structure and a read circuit. The non-volatile memory structure is the non-volatile memory structure described in any of the above embodiments; and the read circuit includes:

[0023] Comparator amplifier; bit line address selector, which includes a first bit line address selector and a second bit line address selector; wherein

[0024] The first bit line address selector is connected to the non-inverting input of the comparator amplifier and the second terminal of the first memory bank; the second bit line address selector is connected to the inverting input of the comparator amplifier and the second terminal of the second memory bank; and...

[0025] The first line address selector and the non-inverting input of the comparator amplifier are connected to the data voltage, and the second line address selector and the inverting input of the comparator amplifier are connected to the reference voltage.

[0026] According to another specific embodiment of the present invention, the non-volatile magnetic random access memory disclosed in this embodiment further includes a first line voltage clamp between the first line address selector and the non-inverting input of the comparator amplifier; and,

[0027] A second bit line voltage clamp is also provided between the second bit line address selector and the inverting input of the comparator amplifier.

[0028] According to another specific embodiment of the present invention, the non-volatile magnetic random access memory disclosed in the embodiments of the present invention further includes a second voltage generator and a third voltage generator in its read circuit; wherein...

[0029] The second voltage generator is connected to the first line address selector to provide voltage for write operations on the first memory bank; and...

[0030] The third voltage generator is connected to the second bit line address selector to provide voltage for write operations on the second memory bank.

[0031] According to another specific embodiment of the present invention, the non-volatile magnetic random access memory disclosed in the embodiments of the present invention has the same voltage generator for the second voltage generator and the third voltage generator.

[0032] According to another specific embodiment of the present invention, the non-volatile magnetic random access memory disclosed in this embodiment further includes a first bias voltage module, a second bias voltage module, and a bias current module in its read circuit; wherein,

[0033] The first bias voltage module is connected to the data voltage, and the second bias voltage module is connected to the reference voltage; and...

[0034] The first bias voltage module and the second bias voltage module are also connected to the power supply voltage, and the bias current module is located between the first bias voltage module and the second bias voltage module.

[0035] According to another specific embodiment of the present invention, the non-volatile magnetic random access memory disclosed in the embodiment of the present invention includes a bias current module comprising a first bias current circuit and a second bias current circuit, the first bias current circuit and the second bias current circuit being mirror-symmetrical, and the first bias current circuit and the second bias current circuit being connected to the power supply voltage in parallel.

[0036] According to another specific embodiment of the present invention, the non-volatile magnetic random access memory disclosed in this embodiment includes a first bias current circuit comprising a first diode, a first capacitor, and a second capacitor. The first diode and the first capacitor are connected in parallel, and then connected in series with the second capacitor.

[0037] The second bias current circuit includes a second diode, a third capacitor, and a fourth capacitor. The second diode and the third capacitor are connected in parallel, and then connected in series with the fourth capacitor.

[0038] The first bias current circuit is connected to the reference voltage and the second bit line voltage clamp, and the second bias current circuit is connected to the data voltage and the first bit line voltage clamp.

[0039] According to another specific embodiment of the present invention, the non-volatile magnetic random access memory disclosed in the embodiments of the present invention includes a first bias voltage module comprising a first transistor and a second transistor connected in series; wherein

[0040] The first transistor is connected to the power supply voltage, and the second transistor is connected to the first line voltage clamp; the first transistor and the second transistor have opposite polarities; and,

[0041] The second bias voltage module includes a third transistor and a fourth transistor connected in series; wherein

[0042] The third transistor is connected to the power supply voltage, and the fourth transistor is connected to the second bit line voltage clamp; the third transistor and the fourth transistor have opposite polarities.

[0043] According to another specific embodiment of the present invention, the non-volatile magnetic random access memory disclosed in this embodiment includes a bias current module comprising a pre-charge circuit, and a first switching element, a second switching element, a third switching element, and a fourth switching element connected to the pre-charge circuit; wherein,

[0044] The first switching element is connected to the drain of the first transistor and the third transistor, and the source of the second transistor and the fourth transistor.

[0045] The two switching elements are connected to the gates of the first transistor, the second transistor, the third transistor, and the fourth transistor;

[0046] The third switching element is connected to the drain of the second transistor;

[0047] The fourth switching element is connected to the drain of the fourth transistor.

[0048] According to another specific embodiment of the present invention, the non-volatile magnetic random access memory disclosed in this embodiment of the present invention uses PMOS transistors for the first transistor and the third transistor; and,

[0049] The second and fourth transistors are NMOS transistors.

[0050] By employing the above scheme, a first and second memory bank with opposite magnetization states are connected in parallel and connected to the same switching transistor. When writing and / or reading operations are performed on the two memory banks, one memory bank is in a high-resistance state and the other is in a low-resistance state. During writing, the timing sequence is divided into two steps: while writing to one memory bank, the other memory bank is left floating, preventing mutual interference between the two memory banks and improving the accuracy of the judgment. Furthermore, using only one switching transistor saves circuit space compared to the prior art where a corresponding switching transistor is set for each memory bank. Further, compared to the prior art using a fixed memory bank as a reference unit, this embodiment connects two memory banks with opposite resistance states in parallel. When one memory bank is used as the judgment unit, the other can serve as the reference unit. This avoids the susceptibility of a single reference current to drift current, improving the sensitivity of the judgment and avoiding the area cost of two transistors. Moreover, by using symmetrical first and second memory banks with a symmetrical latch structure, the decision margin between the high-resistance and low-resistance memory banks can be maximized, further improving the sensitivity of the read circuit. Attached Figure Description

[0051] Figure 1a This is a schematic diagram of the circuit structure of a non-volatile magnetic random access memory in the prior art;

[0052] Figure 1b This is a schematic diagram of the circuit structure of a non-volatile magnetic random access memory structure in the prior art;

[0053] Figure 2 This is a schematic diagram of the circuit structure of the non-volatile magnetic random access memory provided in an embodiment of the present invention;

[0054] Figure 3 This is a schematic diagram of another circuit structure of the non-volatile magnetic random access memory provided in an embodiment of the present invention;

[0055] Figure 4 This is a schematic diagram of another circuit structure of the non-volatile magnetic random access memory provided in an embodiment of the present invention;

[0056] Figure 5This is a schematic diagram of the circuit structure of the non-volatile magnetic random access memory structure provided in the embodiments of the present invention;

[0057] Figure 6 This is a timing diagram of a non-volatile magnetic random access memory being written to 0 according to an embodiment of the present invention;

[0058] Figure 7 This is a timing diagram of a non-volatile magnetic random access memory being written with a 1 according to an embodiment of the present invention;

[0059] Figure 8 This is a timing diagram of data being read into the non-volatile magnetic random access memory provided in an embodiment of the present invention;

[0060] Figure 9 This is a state table of the non-volatile magnetic random access memory provided in this embodiment of the invention during read and write operations;

[0061] Figure 10 This is a comparison diagram of the judgment margin of the non-volatile magnetic random access memory provided in the embodiments of the present invention and the judgment margin of the non-volatile magnetic random access memory in the prior art.

[0062] Background Art Figure Labels:

[0063] 01. Comparator amplifier; 02. Memory cell; 03. Bit line address selector; 04. Bit line voltage clamper; 05. Three-stage transistor.

[0064] Reference numerals in the accompanying drawings:

[0065] 1. Memory cell; 11. First memory cell; 12. Second memory cell; 13. Switching transistor; 2. Read circuit; 21. Comparative amplifier; 22. First bit line address selector; 23. Second bit line address selector; 24. First bit line voltage clamp; 25. Second bit line voltage clamp; 3. First voltage generator; 4. Second voltage generator; 5. Third voltage generator; 6. First bias voltage module; 61. First transistor; 62. Second transistor; 7. Second bias voltage module; 71. Third transistor; 72. Fourth transistor; 8. Bias voltage Current module; 81, First bias current circuit; 811, First diode; 812, First capacitor; 813, Second capacitor; 82, Second bias current circuit; 821, Second diode; 822, Third capacitor; 823, Fourth capacitor; 83, Precharge circuit; 84, First switching element; 85, Second switching element; 86, Third switching element; 87, Fourth switching element; Vdata, Data voltage; Vref, Reference voltage; D, Drain; G, Gate; S, Source; WL, Word line; BL, Bit line; SL, Source line; VDD, Power supply voltage. Detailed Implementation

[0066] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Although the description of the present invention is presented in conjunction with preferred embodiments, this does not mean that the features of the invention are limited to these embodiments. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of the present invention. To provide a deep understanding of the invention, many specific details will be included in the following description. The invention may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of the invention, some specific details will be omitted in the description. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0067] It should be noted that in this specification, similar reference numerals and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0068] In the description of this embodiment, it should be noted that the terms "upper", "lower", "inner", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of the invention is usually placed in during use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the present invention.

[0069] The terms “first”, “second”, etc., are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0070] In the description of this embodiment, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this embodiment based on the specific circumstances.

[0071] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0072] To address the issue of low judgment margin in high / low resistance state determination in existing non-volatile magnetic random access memory (NRAM), this embodiment provides a NRAM structure, specifically, as follows: Figures 2 to 4As shown. The non-volatile magnetic random access memory structure provided in this embodiment includes at least one memory cell 1, which includes a first memory bank 11, a second memory bank 12, and a switching transistor 13.

[0073] Specifically, in this embodiment, the first end of the first memory bank 11 and the first end of the second memory bank 12 are respectively connected to the drain G of the switching transistor 13; the second end of the first memory bank 11 is connected to the first bit line BL, and the second end of the second memory bank 12 is connected to the second bit line BL, and are respectively connected to the read circuit 2. The gate of the switching transistor 13 is connected to the word line WL, the source S of the switching transistor 13 is connected to the source line SL, and the source line SL is connected to the first voltage generator 3.

[0074] It should be noted that in this embodiment, both the first memory cell 11 and the second memory cell 12 are magnetic tunnel junctions, with the first end being the fixed layer of the magnetic tunnel junction and the second end being the free layer of the magnetic tunnel junction. The magnetization states of the first memory cell 11 and the second memory cell 12 are opposite.

[0075] It should be explained that in this embodiment, before writing and / or reading, the magnetization states of the first memory bank 11 and the second memory bank 12 are set to opposite states so that subsequent writing and / or reading can be performed. Specifically, the opposite magnetization states mean that the resistance states of the first memory bank 11 and the second memory bank 12 are opposite. In other words, when the output of the first memory bank 11 is logic "1", the output of the second memory bank 12 is logic "0"; or when the output of the first memory bank 11 is logic "0", the output of the second memory bank 12 is logic "1".

[0076] It should also be noted that in this embodiment, the first memory cell 11 and the second memory cell 12 are physically close together, thereby overcoming the influence of drift current on the determination of the high and low resistance states.

[0077] The first voltage generator 3, also known as the source line drive module, mainly provides voltage for the first memory bank 11 and the second memory bank 12 when performing write operations.

[0078] Further, refer to Figure 5 In this embodiment, the non-volatile memory structure includes a memory cell array composed of several memory cells 1. In the memory cell array, the gate of the switching transistor 13 in each row of memory cells 1 is connected to the word line of each row; and the source S of the switching transistor 13 in each column of memory cells 1 is connected to the source line SL of each column; and the first end of the memory cell body in each column of memory cells 1 is connected to the bit line BL of each column.

[0079] Preferably, in this embodiment, the switching transistor 13 is an NMOS transistor.

[0080] It should be noted that in this embodiment, the non-volatile memory structure is formed by at least one memory cell 1. Figure 5 This illustrates one scenario of a storage cell array configured in a 2x2 configuration.

[0081] When the memory cells 1 are arranged in a row, the gates G of all the switching transistors 13 in that row are connected to the same word line WL. When the memory cells 1 are arranged in a column, the sources S of all the switching transistors 13 in that column are connected to the same source line SL.

[0082] Based on the above-described non-volatile memory structure, embodiments of the present invention also provide a non-volatile magnetic random access memory (MRAM). In this embodiment, the non-volatile magnetic random access memory includes a non-volatile magnetic random access memory structure and a read circuit 2. Furthermore, the non-volatile memory structure is the non-volatile memory structure described in any of the above embodiments.

[0083] Furthermore, in this embodiment, the read circuit 2 includes a comparator amplifier 21 and a bit line address selector.

[0084] In this embodiment, the comparator amplifier 21 can amplify the input signal, and the bit line address selector can select data.

[0085] Specifically, the bit line address selector includes a first bit line address selector 22 and a second bit line address selector 23. The first bit line address selector 22 is connected to the non-inverting input of the comparator amplifier 21 and the second terminal of the first memory bank 11. The second bit line address selector 23 is connected to the inverting input of the comparator amplifier 21 and the second terminal of the second memory bank 12. Furthermore, the first bit line address selector 22 and the non-inverting input of the comparator amplifier 21 are connected to the data voltage Vdata, and the second bit line address selector 23 and the inverting input of the comparator amplifier 21 are connected to the reference voltage Vref.

[0086] More specifically, a first line voltage clamp 24 is provided between the first line address selector 22 and the non-inverting input of the comparator amplifier 21; and a second line voltage clamp 25 is provided between the second line address selector 23 and the inverting input of the comparator amplifier 21.

[0087] It should be noted that in this embodiment, the bit line address selector is connected to the bit line BL, the second voltage generator 4, the third voltage generator 5, and the bit line voltage clamper. Its main function is to select a valid bit line BL to connect to the second voltage generator 4 and the third voltage generator 5 for write operations, or to select a valid bit line BL to connect to the bit line voltage clamper for read operations. Furthermore, the bit line address selector also sets a default excitation state for unselected bit lines BL.

[0088] Furthermore, the non-volatile magnetic random access memory provided in this embodiment further includes a second voltage generator 4 and a third voltage generator 5 in its read circuit 2. The second voltage generator 4 is connected to the first bit line address selector 22 to provide voltage for the write operation of the first memory bank 11; and the third voltage generator 5 is connected to the second bit line address selector 23 to provide voltage for the write operation of the second memory bank 12.

[0089] It is important to understand that the second voltage generator 4 and the third voltage generator 5 have strong current-driving or voltage-driving capabilities, which can meet the requirements for the state switching of the first memory bank 11 and the second memory bank 12. Specifically, they can be power managers, such as LDO linear regulated power supplies, REG power supplies, etc.

[0090] During a read operation, the bit line address selector connects the current or voltage signal of bit line BL to the bit line voltage clamp through the selected open transmission gate. The bit line voltage clamp can then transmit this signal to the read circuit 2.

[0091] During a write operation, the bit line address selector is used to apply a voltage that meets the operating conditions to the selected bit line BL or source line SL.

[0092] It should be noted that in this embodiment, the first memory bank 11 and the second memory bank 12 may be driven by their respective voltage generators, or the first memory bank 11 and the second memory bank 12 may be driven by the same voltage generator.

[0093] Preferably, in order to save on circuit layout, in this embodiment, the second voltage generator 4 and the third voltage generator 5 are the same voltage generator.

[0094] In this embodiment, reference Figure 2The reading circuit 2 also includes a first bias voltage module 6, a second bias voltage module 7, and a bias current module 8. The first bias voltage module 6 is connected to the data voltage Vdata, and the second bias voltage module 7 is connected to the reference voltage Vref. Furthermore, the first bias voltage module 6 and the second bias voltage module 7 are also connected to the power supply voltage VDD, and the bias current module 8 is located between the first bias voltage module 6 and the second bias voltage module 7.

[0095] Next, combine Figures 2 to 4 The specific structure and connection relationship of the first bias voltage module 6, the second bias voltage module 7, and the bias current module 8 are described.

[0096] In one specific embodiment of the present invention, reference is made to... Figure 3 The bias current module 8 includes a first bias current circuit 81 and a second bias current circuit 82. The first bias current circuit 81 and the second bias current circuit 82 are mirror-symmetrical and are connected to the power supply voltage VDD in parallel.

[0097] Specifically, the first bias current circuit 81 includes a first diode 811, a first capacitor 812, and a second capacitor 813. The first diode 811 and the first capacitor 812 are connected in parallel, and then connected in series with the second capacitor 813. The second bias current circuit 82 includes a second diode 821, a third capacitor 822, and a fourth capacitor 823. The second diode 821 and the third capacitor 822 are connected in parallel, and then connected in series with the fourth capacitor 823. Furthermore, the first bias current circuit 81 is connected to the reference voltage Vref and the second bit line voltage clamp 25, and the second bias current circuit 82 is connected to the data voltage Vdata and the first bit line voltage clamp 24.

[0098] It should be noted that the negative terminals of the first diode 811, the second diode 821, the first capacitor 812, the second capacitor 813, the third capacitor 822, and the fourth capacitor 823 are all connected to switching components.

[0099] Continue to refer to Figure 3 It should be explained that in this embodiment, the read circuit 2 has a symmetrical latch-type circuit structure. The latch-type comparator amplification structure can maintain the voltage output by the first memory bank 11 and the second memory bank 12 at a high level and / or a low level. Therefore, when the memory cell 1 is written to and / or read from, the level will not be reversed due to external forces, which can prevent inaccurate results from writing and / or reading.

[0100] In another specific embodiment of the invention, reference is made to... Figure 4The first bias voltage module 6 includes a first transistor 61 and a second transistor 62 connected in series. The first transistor 61 is connected to the power supply voltage VDD, and the second transistor 62 is connected to the first line voltage clamp 24; the first transistor 61 and the second transistor 62 have opposite polarities.

[0101] Furthermore, the second bias voltage module 7 includes a third transistor 71 and a fourth transistor 72 connected in series. The third transistor 71 is connected to the power supply voltage VDD, and the fourth transistor 72 is connected to the second bit line voltage clamp 25; the polarities of the third transistor 72 and the fourth transistor 72 are opposite.

[0102] Furthermore, the bias current module 8 includes a pre-charge circuit 83, and a first switching element 84, a second switching element 85, a third switching element 86, and a fourth switching element 87 connected to the pre-charge circuit 83. The first switching element 84 is connected to the drain D of the first transistor 61 and the third transistor 71, and to the source S of the second transistor 62 and the fourth transistor 72.

[0103] Furthermore, the second switching element 85 is connected to the gate G of the first transistor 61, the second transistor 62, the third transistor 71, and the fourth transistor 72; the third switching element 86 is connected to the drain D of the second transistor 61; and the fourth switching element 87 is connected to the drain D of the fourth transistor 72.

[0104] The first transistor 61, the second transistor 62, the third transistor 71, the fourth transistor 72, and the comparator amplifier 21, connected in the above manner, constitute a latching circuit structure.

[0105] Preferably, in this embodiment, the first transistor 61 and the third transistor 71 are PMOS transistors. Furthermore, the second transistor 62 and the fourth transistor 72 are NMOS transistors.

[0106] The following is for reference. Figure 2-9 The process of reading and writing to the non-volatile magnetic random access memory provided in the embodiments of the present invention will be described in detail.

[0107] For details, please refer to Figure 2 - As shown in Figure 9, when writing 0, in the first timing sequence (within the first group of dashed lines), the source line SL is grounded, the first bit line BL1 on the left is given the write operation voltage, and the second bit line BL2 on the right is floating. Current flows from the bit line BL through the memory bank, then to the switching transistor 13 that is turned on by the word line WL, and finally to the source line SL. At this time, SL is grounded.

[0108] In the second timing sequence (within the second set of dashed lines), the first bit line BL1 on the left is floating, the source line SL provides the voltage under write operation conditions, and the current flows from the switching transistor 13 controlled by the word line WL through the memory bank to the second bit line BL2 on the right, and is then pulled low to the ground potential at the bit line address selector. Through these two operations, the first memory bank 11 and the second memory bank 12 are written with different resistance values.

[0109] Continue to refer to Figure 4 and Figure 6-9 When writing a 1, the first memory bank 11 has a high resistance, the second memory bank 12 has a low resistance, and the current between the second transistor 62 and the fourth transistor 72 and their corresponding bit line voltage clamps is equal. The bit line voltage connected to the second memory bank 12 is lower than the bit line voltage connected to the first memory bank 11, causing the voltage between the second transistor 62 and the first bit line voltage clamp 24 to be higher than the voltage between the fourth transistor 72 and the second bit line voltage clamp 25. Therefore, after positive feedback amplification, the output voltage of the comparator amplifier 21 is a high voltage.

[0110] When writing 0, the first memory bank 11 has a low resistance, and the second memory bank 12 has a high resistance. The current between the second transistor 62 and the fourth transistor 72 and their corresponding bit line voltage clamps is equal. The bit line voltage connected to the first memory bank 11 is lower than the bit line voltage connected to the second memory bank 12, causing the voltage between the second transistor 62 and the first bit line voltage clamp 24 to be lower than the voltage between the fourth transistor 72 and the second bit line voltage clamp 25. Therefore, after positive feedback amplification, the output voltage of the comparator amplifier 21 is a low voltage.

[0111] refer to Figure 10 As can be seen, the non-volatile magnetic random access memory using the non-volatile magnetic random access memory structure provided in this embodiment of the invention improves the current margin range for judging the low-resistance state and high-resistance state of the memory cell from the relatively narrow (25%) current range in the prior art to at least 50% of the current range.

[0112] By employing the above technical solution, a first and second memory bank with opposite magnetization states are connected in parallel and connected to the same switching transistor. When writing and / or reading operations are performed on the two memory banks, one memory bank is in a high-resistance state and the other is in a low-resistance state. During writing, the timing sequence is divided into two steps: while writing to one memory bank, the other memory bank is left floating, preventing the two memory banks from interfering with each other and resulting in higher accuracy. Furthermore, using only one switching transistor saves circuit space compared to the prior art where a corresponding switching transistor is set for each memory bank. Moreover, compared to the prior art using a fixed memory bank as a reference unit, this embodiment connects two memory banks with opposite resistance states in parallel. When one memory bank is used as the judgment unit, the other can serve as the reference unit. This avoids the susceptibility of a single reference current to drift current, improves judgment sensitivity, and avoids the area cost associated with two transistors. Furthermore, by using a symmetrical first and second memory bank paired with a symmetrical latch storage structure, the decision margin between the high-resistance and low-resistance memory banks can be maximized, thereby further improving the sensitivity of the read circuit.

[0113] While the present invention has been illustrated and described with reference to certain preferred embodiments, those skilled in the art should understand that the above description is a further detailed explanation of the invention in conjunction with specific embodiments, and should not be construed as limiting the specific implementation of the invention to these descriptions. Various changes in form and detail can be made by those skilled in the art, including several simple deductions or substitutions, without departing from the spirit and scope of the invention.

Claims

1. A non-volatile magnetic random access memory, the non-volatile memory comprising a non-volatile magnetic random access structure and a read circuit, characterized in that, The non-volatile memory structure includes at least one memory cell, the memory cell including a first memory bank, a second memory bank, and a switching transistor; wherein the first memory bank and the second memory bank have opposite magnetization states; The first end of the first memory cell and the first end of the second memory cell are respectively connected to the drain of the same switching transistor; The second end of the first memory cell is connected to the first bit line, and the second end of the second memory cell is connected to the second bit line, and both are connected to the read circuit. The gate of the switching transistor is connected to a word line, the source of the switching transistor is connected to a source line, and the source line is connected to a first voltage generator; and, The reading circuit includes: Comparator amplifier; A bit line address selector, comprising a first bit line address selector and a second bit line address selector; wherein The first bit line address selector is connected to the non-inverting input of the comparator amplifier and the second terminal of the first memory bank, and the second bit line address selector is connected to the inverting input of the comparator amplifier and the second terminal of the second memory bank. The first bit line address selector is connected to the non-inverting input of the comparator amplifier and to the data voltage, and the second bit line address selector is connected to the inverting input of the comparator amplifier and to the reference voltage. The reading circuit further includes a first bias voltage module, a second bias voltage module, and a bias current module; wherein, The first bias voltage module is connected to the data voltage, and the second bias voltage module is connected to the reference voltage; and... The first bias voltage module and the second bias voltage module are also connected to the power supply voltage, and the bias current module is located between the first bias voltage module and the second bias voltage module.

2. The non-volatile magnetic random access memory as described in claim 1, characterized in that, Both the first and second memory cells are magnetic tunnel junctions, with the first end being a fixed layer and the second end being a free layer.

3. The non-volatile magnetic random access memory as described in claim 1 or 2, characterized in that, The non-volatile memory structure includes a memory cell array composed of several of the aforementioned memory cells; wherein... In the memory cell array, the gate of the switching transistor in each row of memory cells is connected to the word line of that row; and, In the memory cell array, the source of the switching transistor in each column of memory cells is connected to the source line of that column; and, In the memory cell array, the first end of the memory cell in each column is connected to the bit line of each column.

4. The non-volatile magnetic random access memory as described in claim 1 or 2, characterized in that, The switching transistor is an NMOS transistor.

5. The non-volatile magnetic random access memory as described in claim 1, characterized in that, A first bit line voltage clamp is also provided between the first bit line address selector and the non-inverting input of the comparator amplifier; and, A second bit line voltage clamp is also provided between the second bit line address selector and the inverting input of the comparator amplifier.

6. The non-volatile magnetic random access memory as described in claim 1, characterized in that, The reading circuit further includes a second voltage generator and a third voltage generator; wherein... The second voltage generator is connected to the first bit line address selector to provide voltage for write operations on the first memory bank; and... The third voltage generator is connected to the second bit line address selector to provide voltage for write operations on the second memory bank.

7. The non-volatile magnetic random access memory as described in claim 6, characterized in that, The second voltage generator and the third voltage generator are the same voltage generator.

8. The non-volatile magnetic random access memory as described in claim 1, characterized in that, The bias current module includes a first bias current circuit and a second bias current circuit. The first bias current circuit and the second bias current circuit are mirror-symmetrical and are connected to the power supply voltage in parallel.

9. The non-volatile magnetic random access memory as described in claim 8, characterized in that, The first bias current circuit includes a first diode, a first capacitor, and a second capacitor. The first diode and the first capacitor are connected in parallel, and then connected in series with the second capacitor. and, The second bias current circuit includes a second diode, a third capacitor, and a fourth capacitor. The second diode is connected in parallel with the third capacitor and then connected in series with the fourth capacitor. and, The first bias current circuit is connected to the reference voltage and the second bit line voltage clamp, and the second bias current circuit is connected to the data voltage and the first bit line voltage clamp.

10. The non-volatile magnetic random access memory as described in claim 1, characterized in that, The first bias voltage module includes a first transistor and a second transistor connected in series; wherein The first transistor is connected to the power supply voltage, and the second transistor is connected to the first bit line voltage clamp; the first transistor and the second transistor have opposite polarities; and... The second bias voltage module includes a third transistor and a fourth transistor connected in series; in The third transistor is connected to the power supply voltage, and the fourth transistor is connected to the second bit line voltage clamp; the polarities of the third transistor and the fourth transistor are opposite.

11. The non-volatile magnetic random access memory as described in claim 10, characterized in that, The bias current module includes a pre-charge circuit, and a first switching element, a second switching element, a third switching element, and a fourth switching element connected to the pre-charge circuit; wherein, The first switching element is connected to the drain of the first transistor and the third transistor, and the source of the second transistor and the fourth transistor; The two switching elements are connected to the gates of the first transistor, the second transistor, the third transistor, and the fourth transistor; The third switching element is connected to the drain of the second transistor; The fourth switching element is connected to the drain of the fourth transistor.

12. The non-volatile magnetic random access memory as described in claim 11, characterized in that, The first transistor and the third transistor are PMOS transistors; and, The second transistor and the fourth transistor are NMOS transistors.

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