Method for storing image frames in a memory and related image processor

Abstract

The present application proposes a method for storing an image frame in a memory and a related image processor. The method includes: receiving the image frame; dividing the image frame into M columns of data block columns along a first direction; dividing each column of the M columns of data block columns into N data blocks along a second direction perpendicular to the first direction; performing a compression operation on each of the M*N data blocks to generate M*N compressed data blocks; and storing the N compressed data blocks corresponding to the first column of the M columns of data block columns and the N compressed data blocks corresponding to the (P+1)th column of the M columns of data block columns in a continuous storage space in the memory, wherein M, N and P are integers, and M>1, N>0 and P<M.

Description

Technical Field

[0001] The present invention relates to an image processor; in particular, an image processor and a related method for storing image frames in a memory. Background Art

[0002] In recent years, with the development of the Internet and effective displays, the amount of multimedia data is increasing rapidly. Taking movies (e.g., dynamic images, dynamic images, etc.) as an example, traditionally, standard definition (SD) resolution (480p) movies are the mainstream, but now, full high-definition (Full-HD) movies with a resolution of 1080p and movies beyond high definition (720p) are becoming increasingly popular. Therefore, how to improve the memory usage efficiency in the process of image data processing has become a technical problem that needs to be solved in the relevant field. Summary of the invention

[0003] The embodiment of the present disclosure provides a method for storing an image frame in a memory, the method comprising: receiving the image frame; dividing the image frame into M columns of data block columns along a first direction; dividing each column of the M columns of data block columns into N data blocks along a second direction perpendicular to the first direction; performing a compression operation on each of the M*N data blocks to generate M*N compressed data blocks; and storing the N compressed data blocks corresponding to the first column of the M columns of data block columns and the N compressed data blocks corresponding to the (P+1)th column of the M columns of data block columns in a continuous storage space in the memory, wherein M, N and P are integers, and M>1, N>0 and P<M.

[0004] The embodiment of the present disclosure provides an image processor for storing an image frame in a memory, the image processor comprising: a compression engine for receiving the image frame, dividing the image frame into M columns of data block columns along a first direction, dividing each column of the M columns of data block columns into N data blocks along a second direction perpendicular to the first direction, and performing a compression operation on each of the M*N data blocks to generate M*N compressed data blocks; and a control unit for storing the N compressed data blocks corresponding to the first column of the M columns of data block columns and the N compressed data blocks corresponding to the (P+1)th column of the M columns of data block columns in a continuous storage space in the memory, wherein M, N and P are integers, and M>1, N>0 and P<M.

[0005] The above method and image processor can not only improve the memory usage performance, but also further save the transmission bandwidth and reduce the overall power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1It is a schematic diagram of an embodiment of an image processor of the present application being applied to a system.

[0007] Figure 2 This is an embodiment of an image frame received by the compression engine of the present application.

[0008] Figure 3 This is an embodiment of the arrangement of compressed image frames in a memory according to the present application. DETAILED DESCRIPTION

[0009] Figure 1 1 is a schematic diagram of an embodiment of an image processor 101 of the present application applied to a system 100. The system 100 includes an image processor 101, a memory 106, and a display 108, wherein the memory 106 is coupled between the image processor 101 and the display 108. In this embodiment, the memory 106 and the image processor 101 are respectively disposed in different chips. That is, for the image processor 101, the memory 106 is an external memory. In this embodiment, the memory 106 is a dynamic random access memory, but the present application is not limited thereto.

[0010] The image processor 101 includes a compression engine 102 and a control unit 104. The compression engine 102 is used to receive at least one image frame F in an image and / or a video and perform a compression operation thereon. In the present embodiment, the compression operation may be, for example, a lossless compression algorithm or a lossy compression algorithm, but the present application is not limited thereto. The control unit 104 is used to store the compressed image frame FC in the memory 106, and the compressed image frame FC is then transmitted to the display 108 for display. In the present application, the control unit 104 uses an optimized method to arrange the compressed image frame FC in the memory 106, which not only improves the performance of the memory 106, but also further saves the transmission bandwidth between the memory 106 and the display 108, and reduces the overall power consumption of the system 100. Please see further discussion below.

[0011] Figure 2 In an embodiment of an image frame F received by the compression engine 102 of the present application, the compression engine 102 divides the image frame F into a plurality of data blocks of fixed size. For example, the length of each data block along the X direction is 16 pixels; the width along the Y direction is 4 pixels. After the division, the image frame F includes N rows of data block rows in the X direction; and includes M columns of data block rows in the Y direction, wherein the direction X is perpendicular to the direction Y, and N and M are integers greater than 0.

[0012] Thereafter, the compression engine 102 performs compression operations on each of the M*N data blocks in the image frame F to generate M*N compressed data blocks. In the present embodiment, the Z-scan method is used to perform compression operations on the M*N data blocks in sequence. For example, the order of the compression operation on the image frame F may be data blocks 1_1, 1_2, 2_1, 2_2, 1_3, 1_4, 2_3, 2_4… However, the present application is not limited to the above order. After the compression operation, the width of the M*N compressed data blocks in the direction Y is a fixed size and is the same, for example, the width may be 1 pixel; the length of the M*N compressed data blocks in the direction x is not a fixed size. In other words, the lengths of any two of the M*N compressed data blocks may be different.

[0013] The control unit 104 stores the compressed data blocks corresponding to the first group of data block columns among the M*N compressed data blocks in a continuous storage space in the memory 106. Figure 3 As shown, Figure 3 The first compressed data block column corresponds to the first group of data block columns, Figure 3 The label 1_1′ in the table refers to the compressed data block obtained after the data block 1_1 is compressed, and so on. The first group of data blocks includes Figure 2 In other words, the first set of data block rows includes the first data block row, the (P+1)th data block row, ..., the (k*P+1)th data block row, and so on (k+1)th data block row, and the first set of data block rows are arranged equidistantly in the Y direction. In the present disclosure, Figure 3 In the illustrated embodiment, M, N and P are integers, and M>1, N>0 and P<M.

[0014] Specifically, the control unit 104 allocates the N compressed data blocks obtained by compressing the N data blocks in the 1st data block column to the first set of continuous addresses of the memory 106, and then allocates the N compressed data blocks obtained by compressing the N data blocks in the (P+1)th data block column to another second set of continuous addresses of the memory 106. The second set of continuous addresses follows the first set of continuous addresses, so that the address of the compressed data block (P+1)_1′ and the address of the compressed data block 1_N′ are continuous addresses. The configuration method of the remaining compressed data blocks corresponding to the first set of data block columns in the memory is also the same, so that Figure 3 The first column of compressed data blocks in the is a total of N*(k+1) compressed data blocks with consecutive addresses.

[0015] Similarly, the control unit 104 stores the compressed data blocks corresponding to the second group of data block columns among the M*N compressed data blocks in the continuous storage space of the memory 106, that is, Figure 3 The second set of compressed data block columns includes Figure 2 The (n*P+2)th column of data blocks in . And so on, we will get Figure 3 In the P columns of compressed data block rows, each column is stored in a continuous space of the memory 106, and the space allocated to each compressed data block row is not continuous with the space allocated to the adjacent compressed data block row, that is, the address of the compressed data block 2_1′ is not continuous with the address of the compressed data block (k*P+1)_N′, such as Figure 3 As shown, the compressed data block (k*P+1)_N′ is followed by a dummy storage space 302. In other words, the compressed data block 2_1′ and the compressed data block (k*P+1)_N′ are separated by at least the dummy storage space 302. The address of the compressed data block 3_1′ is not continuous with the address of the compressed data block (k*P+2)_N′, and the compressed data block (k*P+2)_N′ is followed by a dummy storage space 304. In other words, the compressed data block 3_1′ and the compressed data block (k*P+2)_N′ are separated by at least the dummy storage space 304, and so on. The length of the dummy storage space following each compressed data block row along the X direction may be different. Compared with the general method, the above method can reduce the wasted dummy storage space in the memory 106, so as to improve the use efficiency of the memory 106.

[0016] It should be noted that in Figure 2 and Figure 3 In order to facilitate understanding, the image frames received by the compression engine and the arrangement of the compressed image frames in the memory are shown in a block manner (i.e., in a two-dimensional manner). However, before the image frames are transmitted from the compression engine 102 to the control unit 104 and / or the compressed image frames are transmitted from the control unit 104 to the memory 106, a serialization process can be used so that the transmission can be performed in a sequential mode (i.e., in a one-dimensional manner).

[0017] The above description briefly presents the features of certain embodiments of the present invention, so that those skilled in the art to which the present invention belongs can more fully understand the various aspects of the present disclosure. Those skilled in the art to which the present invention belongs can understand that they can easily use the present disclosure as a basis to design or change other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. It should be understood that, in addition to the steps whose order has been specifically described, the steps mentioned in the flowchart of the present application method can be adjusted according to actual needs, and can even be executed simultaneously or partially simultaneously. In addition, hardware, software or firmware can be used to implement the above-mentioned units, modules or methods according to the needs of the designer. Those skilled in the art to which the present invention belongs should also understand that these equal implementations still belong to the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made to them without departing from the spirit and scope of the present disclosure.

[0018]

Explanation of symbols

[0019] 100: System

[0020] 101: Image Processor

[0021] 102: Compression Engine

[0022] 104: Control unit

[0023] 106: Memory

[0024] 108: Display

[0025] 302, 304: Virtual storage space

[0026] F: Image frame

[0027] FC: compressed image frame

[0028] X, Y: direction.

Claims

1. A method for storing an image frame in a memory, the method comprising: receiving the image frame; Dividing the image frame into M data block rows along a first direction; Dividing each of the M data block columns into N data blocks along a second direction perpendicular to the first direction; Performing a compression operation on each of the M*N data blocks to generate M*N compressed data blocks; as well as storing N compressed data blocks corresponding to the first data block row of the M data block rows and N compressed data blocks corresponding to the (P+1)th data block row of the M data block rows in a continuous storage space of the memory, Where M, N and P are integers, and M>1, N>0 and P <M, Furthermore, the space allocated to each compressed data block row is not continuous with the space allocated to the adjacent compressed data block row, and each compressed data block row is followed by a dummy storage space along the first direction.

2. An image processor for storing image frames in a memory, the image processor comprising: A compression engine, configured to receive the image frame, divide the image frame into M columns of data blocks along a first direction, divide each column of the M columns of data blocks into N data blocks along a second direction perpendicular to the first direction, and perform a compression operation on each of the M*N data blocks to generate M*N compressed data blocks; and a control unit for storing the N compressed data blocks corresponding to the first data block row of the M data block rows and the N compressed data blocks corresponding to the (P+1)th data block row of the M data block rows in a continuous storage space of the memory, Where M, N and P are integers, and M>1, N>0 and P <M, And among them, The space allocated to each compressed data block row is not continuous with the space allocated to an adjacent compressed data block row, and each compressed data block row is followed by a dummy storage space along the first direction. 3 . The image processor as claimed in claim 2 , wherein the widths of the M*N data blocks along the first direction are the same, and the lengths of the M*N data blocks along the second direction are the same. 4 . The image processor of claim 3 , wherein the widths of the M*N compressed data blocks along the first direction are the same, and the lengths of at least two of the M*N compressed data blocks along the second direction are different.

5. The image processor of claim 4 , wherein the control unit is further configured to store k*N compressed data blocks of a first group of data block rows corresponding to the M rows of data block rows in a continuous storage space of the memory, wherein the first group of data block rows includes the (n*P+1)th row of data block rows, where 0≤n≤k, and n and k are integers.

6. The image processor of claim 5, wherein the control unit is further configured to store the N compressed data blocks corresponding to the second row of the M rows of data block rows and the N compressed data blocks corresponding to the (P+2)th row of the M rows of data block rows in a continuous storage space of the memory.

7. The image processor of claim 6, wherein the control unit is further configured to store k*N compressed data blocks of a second group of data block rows corresponding to the M rows of data block rows in a continuous storage space of the memory, wherein the second group of data block rows includes the (n*P+2)th row of data row.

8. The image processor as claimed in claim 7, wherein the control unit is further configured to separate the continuous storage space corresponding to the k*N compressed data blocks of the first group of data block rows from the continuous storage space corresponding to the k*N compressed data blocks of the second group of data block rows by using a virtual storage space in the memory. 9 . The image processor as claimed in claim 5 , wherein the control unit is further configured to allocate the k*N compressed data blocks of the first group of data block rows corresponding to the M rows of data block rows at consecutive addresses of the memory. 10 . The image processor as claimed in claim 7 , wherein the control unit is further configured to allocate the k*N compressed data blocks of the second group of data block rows corresponding to the M rows of data block rows at consecutive addresses of the memory.

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