Packaging structure and manufacturing method thereof

Abstract

The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a bridge, an intermediate substrate, a first reconfiguration structure layer, a second reconfiguration structure layer and a plurality of chips. The bridge includes a silicon substrate, a reconfiguration circuit layer and a plurality of bridge pads. The intermediate substrate includes an intermediate layer, a plurality of conductive through holes, a plurality of first pads and a plurality of second pads. The bridge is buried in the intermediate layer, and the bridge pad is flush with the upper surface. The first reconfiguration structure layer is arranged on the upper surface of the intermediate substrate and is electrically connected to the first pad and the bridge pad of the bridge. The second reconfiguration structure layer is arranged on the lower surface of the intermediate substrate and is electrically connected to the second pad. The chip is arranged on the first reconfiguration structure layer and is electrically connected to the first reconfiguration structure layer. The chips are electrically connected to each other through the bridge. The packaging structure of the present invention has better structural reliability and is particularly suitable for flat surfaces for flip-chip chip bonding.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a packaging structure and a manufacturing method thereof. Background Art

[0002] The key to heterogeneous chiplet integration lies in the electrical connection between the two chips. Currently, Intel's uses the Embedded Multi-DieInterconnect Bridge (EMIB) to connect the two chips to achieve partial or local high-density interconnection. However, the problem encountered by the above technology is that the bridge must be embedded in the organic substrate through lamination technology, so the surface needs to be flat enough for subsequent flip-chip packaging of the chip. Summary of the invention

[0003] The present invention is directed to a packaging structure with better structural reliability, and is particularly suitable for a flat surface for flip-chip bonding.

[0004] The present invention also provides a method for manufacturing a packaging structure, which is used to manufacture the above packaging structure.

[0005] According to an embodiment of the present invention, a packaging structure includes a bridge, an intermediate substrate, a first reconfiguration structure layer, a second reconfiguration structure layer and a plurality of chips. The bridge includes a silicon substrate, a reconfiguration circuit layer and a plurality of bridge pads. The reconfiguration circuit layer is configured on the silicon substrate. The bridge pad is configured on the reconfiguration circuit layer and is electrically connected to the reconfiguration circuit layer. The intermediate substrate includes an intermediate layer, a plurality of conductive vias, a plurality of first pads and a plurality of second pads. The intermediate layer has an upper surface and a lower surface opposite to each other. The conductive vias penetrate the intermediate layer and are respectively connected to the first pad on the upper surface and the second pad on the lower surface. The bridge is buried in the intermediate layer, and the bridge pad is cut flush with the upper surface. The first reconfiguration structure layer is configured on the upper surface of the intermediate substrate and is electrically connected to the first pad and the bridge pad of the bridge. The second reconfiguration structure layer is configured on the lower surface of the intermediate substrate and is electrically connected to the second pad. The chip is configured on the first reconfiguration structure layer and is electrically connected to the first reconfiguration structure layer. The chips are electrically connected to each other through the bridge.

[0006] In the packaging structure according to the embodiment of the present invention, the packaging structure further comprises a plurality of chip pads disposed on the first reconfiguration structure layer and electrically connected to the first reconfiguration structure layer. The chip is electrically connected to the first reconfiguration structure layer and the bridge member through the chip pads.

[0007] In the packaging structure according to an embodiment of the present invention, the above-mentioned packaging structure also includes a plurality of copper pillars, a plurality of solders and a plurality of solder balls. The copper pillars are respectively configured on the chip. The solders are respectively configured on the copper pillars, wherein the copper pillars are respectively located between the chip and the solders. The chip is electrically connected to the bridge through the copper pillars and the solder. The solder balls are configured on the chip, wherein the chip is electrically connected to the first reconfiguration structure layer through the solder balls.

[0008] In the packaging structure according to the embodiment of the present invention, the packaging structure further comprises a plurality of solder ball pads and a plurality of solder balls. The solder ball pads are arranged on the second reconfiguration structure layer and are electrically connected to the second reconfiguration structure layer. The solder balls are respectively arranged on the solder ball pads.

[0009] According to an embodiment of the present invention, a method for manufacturing a packaging structure includes the following steps. A bridge is provided. The bridge includes a silicon substrate, a reconfiguration circuit layer and a plurality of bridge pads. The reconfiguration circuit layer is configured on the silicon substrate, and the bridge pad is configured on the reconfiguration circuit layer and is electrically connected to the reconfiguration circuit layer. The bridge is embedded in an intermediate substrate. The intermediate substrate includes an intermediate layer, a plurality of conductive vias, a plurality of first pads and a plurality of second pads. The intermediate layer has an upper surface and a lower surface opposite to each other. The conductive vias penetrate the intermediate layer and are respectively connected to the first pad located on the upper surface and the second pad located on the lower surface. The bridge pad is cut flush with the upper surface. A first reconfiguration structure layer is formed on the upper surface of the intermediate substrate. The first reconfiguration structure layer is electrically connected to the first pad and the bridge pad of the bridge. A second reconfiguration structure layer is formed on the lower surface of the intermediate substrate. The second reconfiguration structure layer is electrically connected to the second pad. Multiple chips are configured on the first reconfiguration structure layer. The chips are electrically connected to the first reconfiguration structure layer, and the chips are electrically connected to each other through bridges.

[0010] In the method for manufacturing a package structure according to an embodiment of the present invention, the step of embedding the bridge member in the interposer substrate comprises: disposing the bridge member on a temporary substrate, wherein the bridge pad faces the temporary substrate. Forming an interposer on the temporary substrate, wherein the interposer covers the bridge member. Removing the temporary substrate to expose the upper surface of the interposer. Forming a plurality of through holes penetrating the interposer. Forming a conductive through hole, a first pad, and a second pad on the interposer. The conductive through holes are respectively located in the through holes and connect the first pad and the second pad.

[0011] In the method for manufacturing a packaging structure according to an embodiment of the present invention, the method for manufacturing the packaging structure further includes: after forming a first reconfiguration structure layer on the upper surface of the intermediate substrate, forming a plurality of chip pads on the first reconfiguration structure layer and electrically connecting to the first reconfiguration structure layer.

[0012] In the manufacturing method of the packaging structure according to the embodiment of the present invention, before the above-mentioned configuration chip is placed on the first reconfiguration structure layer, it also includes: forming a plurality of copper pillars on the chip respectively. Forming a plurality of solders on the copper pillars respectively, wherein the copper pillars are located between the chip and the solders, and the chip is electrically connected to the bridge through the copper pillars and the solders. Forming a plurality of solder balls on the chip, wherein the chip is electrically connected to the first reconfiguration structure layer through the solder balls.

[0013] In the method for manufacturing a package structure according to an embodiment of the present invention, the method for manufacturing the package structure further includes: after forming a second reconfiguration structure layer on the lower surface of the intermediate substrate, forming a plurality of solder ball pads on the second reconfiguration structure layer and electrically connecting the second reconfiguration structure layer. Forming a plurality of solder balls on the solder ball pads respectively.

[0014] In the method for manufacturing a packaging structure according to an embodiment of the present invention, the bridge member is formed by individual wafer cutting.

[0015] Based on the above, in the design of the packaging structure of the present invention, the bridge component having the reconfiguration circuit layer and the bridge pad is embedded in the intermediate substrate, and the bridge pad is flush with the upper surface of the intermediate layer, so that the first reconfiguration structure layer subsequently formed on the intermediate substrate can have better flatness. In addition, when the chip is subsequently bonded to the first reconfiguration structure layer in a flip-chip manner, in addition to each chip being electrically connected to the external circuit through the first reconfiguration structure layer, the intermediate substrate and the second reconfiguration circuit layer, the two chips can also be electrically connected to each other through the bridge component to achieve partial (partial or local) high-density interconnection. In short, the packaging structure of the present invention can have better structural reliability (due to flatness) and interconnection density between chips in a more cost-effective manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 1J is a schematic diagram of a method for manufacturing a packaging structure according to an embodiment of the present invention.

[0017] Description of Reference Numerals

[0018] 10: wafer;

[0019] 20: Temporary substrate;

[0020] 22: release film;

[0021] 100: packaging structure;

[0022] 110: bridge member;

[0023] 112: silicon substrate;

[0024] 114: reconfigure the circuit layer;

[0025] 116: bridging pad;

[0026] 120: intermediate substrate;

[0027] 121: upper surface;

[0028] 122: Intermediary layer;

[0029] 123: lower surface;

[0030] 124: conductive through hole;

[0031] 125: through hole;

[0032] 126: first pad;

[0033] 128: second pad;

[0034] 130: copper column;

[0035] 135: solder;

[0036] 137: solder ball;

[0037] 140: first reconfiguration structure layer;

[0038] 150: second reconfiguration structure layer;

[0039] 160: chip pad;

[0040] 165: solder ball pad;

[0041] 170: solder ball;

[0042] 180: Chip. DETAILED DESCRIPTION

[0043] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0044] Figures 1A to 1J FIG. 1 is a schematic diagram of a method for manufacturing a packaging structure according to an embodiment of the present invention. Figure 1A It is shown in a simple top view. Figures 1B to 1J It is shown in a cross-sectional view.

[0045] Regarding the method for manufacturing the packaging structure of this embodiment, first, please refer to Figure 1A and Figure 1B, providing a bridge 110. The bridge 110 includes a silicon substrate 112, a reconfiguration circuit layer 114, and a plurality of bridge pads 116. The reconfiguration circuit layer 114 is disposed on the silicon substrate 112, and the bridge pad 116 is disposed on the reconfiguration circuit layer 114 and electrically connected to the reconfiguration circuit layer 114. Here, the bridge 110 is specifically formed by singulation of the wafer 10, wherein the reconfiguration circuit layer 114 is manufactured using a 64-nanometer process technology, and the number of circuit layers of the reconfiguration circuit layer 114 is 2 to 4 layers, and the minimum pitch of the circuit is 0.4 microns. Preferably, the bridge 110 has a size of 3 mm x 3 mm, which means that the size is very small.

[0046] Next, please refer to Figure 1H , the bridge element 110 is embedded in the interposer substrate 120. The interposer substrate 120 includes an interposer layer 122, a plurality of conductive vias 124, a plurality of first pads 126, and a plurality of second pads 128. The interposer layer 122 has an upper surface 121 and a lower surface 123 opposite to each other. The conductive vias 124 penetrate the interposer layer 122 and are respectively connected to the first pads 126 located on the upper surface 121 and the second pads 128 located on the lower surface 123. In particular, the bridge pads 116 of the bridge element 110 are substantially flush with the upper surface 121 of the interposer layer 122.

[0047] In detail, the steps of embedding the bridge element 110 in the intermediate substrate 120 are as follows: Figure 1C The bridge member 110 is disposed on the temporary substrate 20, wherein the bridge pad 116 faces the temporary substrate 20. Here, a release film 22 is also disposed on the temporary substrate 20, wherein the temporary substrate 20 is, for example, a circular or rectangular glass substrate or a steel substrate, and the bridge member 110 is positioned on the temporary substrate 20 in a face-down manner through the release film 22.

[0048] Next, please refer to Figure 1D , an intermediary layer 122 is formed on the temporary substrate 20, wherein the intermediary layer 122 covers the bridge 110, and the material of the intermediary layer 122 is, for example, Ajinomoto Build-up Film (ABF) or Epoxy Molding Compound (EMC), but is not limited thereto.

[0049] Next, please refer to Figure 1E , remove the temporary substrate 20 and the release film 22 to expose the upper surface 121 of the intermediary layer 122 .

[0050] Next, please refer to Figure 1FA plurality of through holes 125 penetrating the intermediary layer 122 are formed by laser drilling, wherein the through holes 125 penetrate the intermediary layer 122 and connect the upper surface 121 and the lower surface 123 , and the through holes 125 are located on both sides of the bridge 110 .

[0051] Next, please refer to Figure 1G , the interposer 122 is turned over so that the upper surface 121 of the interposer 122 faces upward. At this time, the bridge 110 faces upward, and the bridge pad 116 of the bridge 110 is still flush with the upper surface 121 of the interposer 122 .

[0052] Next, please refer to Figure 1H , a conductive through hole 124, a first pad 126 and a second pad 128 are formed on the interposer 122 by electroplating, wherein the conductive through hole 124 is respectively located in the through hole 125, and two opposite ends of the conductive through hole 124 are respectively connected to the first pad 126 and the second pad 128.

[0053] Next, please refer to Fig. 1I , forming a first reconfiguration structure layer 140 on the upper surface 121 of the interposer substrate 120 , wherein the first reconfiguration structure layer 140 is electrically connected to the first pad 126 and the bridge pad 116 of the bridge element 110 .

[0054] Next, please refer to Fig. 1I , forming a second reconfiguration structure layer 150 on the lower surface 123 of the interposer substrate 120 , wherein the second reconfiguration structure layer 150 is electrically connected to the second pad 128 .

[0055] Here, the formation order of the first reconfiguration structure layer 140 and the second reconfiguration structure layer 150 is not limited. For example, the first reconfiguration structure layer 140 may be formed first, and then the second reconfiguration structure layer 150; or, the second reconfiguration structure layer 150 may be formed first, and then the first reconfiguration structure layer 140; or, the first reconfiguration structure layer 140 and the second reconfiguration structure layer 150 may be formed at the same time.

[0056] Afterwards, please refer to Fig. 1I , a plurality of chip pads 160 are formed on the first reconfiguration structure layer 140 and electrically connected to the first reconfiguration structure layer 140. Next, a plurality of solder ball pads 165 are formed on the second reconfiguration structure layer 150 and electrically connected to the second reconfiguration structure layer 150. Afterwards, a plurality of solder balls 170 are formed on the solder ball pads 165, respectively. Here, the order of forming the chip pads 160 and the solder ball pads 165 is not limited.

[0057] Finally, please refer to Figure 1J, multiple chips 180 are configured on the first reconfiguration structure layer 140, wherein the chips 180 are electrically connected to the first reconfiguration structure layer 140, and the chips 180 are electrically connected to each other through the bridge 110. Here, the chip 180 can be a chip of different types, which is not limited here. Further, before configuring the chip 180 on the first reconfiguration structure layer 140, it also includes forming a plurality of copper pillars 130 respectively on the chip 180. Then, a plurality of solders 135 are formed on the copper pillars 130 respectively, wherein the copper pillars 130 are located between the chip 180 and the solders 135. Next, a plurality of solder balls 137 are formed on the chip 180, wherein the chip 180 is electrically connected to the first reconfiguration structure layer 140 through the solder balls 137, and the chip 180 is electrically connected to the bridge 110 through the copper pillars 130 and the solders 135. At this point, the production of the packaging structure 100 has been completed.

[0058] In terms of structure, please refer to Figure 1J The packaging structure 100 includes a bridge 110, an intermediate substrate 120, a first reconfiguration structure layer 140, a second reconfiguration structure layer 150 and a chip 180. The bridge 110 includes a silicon substrate 112, a reconfiguration circuit layer 114 and a bridge pad 116. The reconfiguration circuit layer 114 is configured on the silicon substrate 112. The bridge pad 116 is configured on the reconfiguration circuit layer 114 and is electrically connected to the reconfiguration circuit layer 114. The intermediate substrate 120 includes an intermediate layer 122, a conductive via 124, a first pad 126 and a second pad 128. The intermediate layer 122 has an upper surface 121 and a lower surface 123 opposite to each other. The conductive via 124 penetrates the intermediate layer 122 and is respectively connected to the first pad 126 located on the upper surface 121 and the second pad 128 located on the lower surface 123. The bridge 110 is embedded in the interposer 120, and the bridge pad 116 is flush with the upper surface 121. The first reconfiguration structure layer 140 is disposed on the upper surface 121 of the interposer substrate 120, and is electrically connected to the first pad 126 and the bridge pad 116 of the bridge 110. The second reconfiguration structure layer 150 is disposed on the lower surface 123 of the interposer substrate 120, and is electrically connected to the second pad 128. The chip 180 is disposed on the first reconfiguration structure layer 140, and is electrically connected to the first reconfiguration structure layer 140. The chips 180 are electrically connected to each other through the bridge 110.

[0059] Furthermore, in the present embodiment, the package structure 100 further includes a chip pad 160, a solder ball pad 165 and a solder ball 170. The chip pad 160 is disposed on the first reconfiguration structure layer 140 and is electrically connected to the first reconfiguration structure layer 140. The chip 180 can be electrically connected to the first reconfiguration structure layer 140 and the bridge 110 through the chip pad 160. The solder ball pad 165 is disposed on the second reconfiguration structure layer 150 and is electrically connected to the second reconfiguration structure layer 150. The solder balls 170 are respectively disposed on the solder ball pads 165, wherein the package structure 100 can be electrically connected to an external circuit (such as a printed circuit board) through the solder balls 170.

[0060] In addition, the package structure 100 of the present embodiment further includes copper pillars 130, solder 135 and solder balls 137. The copper pillars 130 are respectively configured on the chips 180. The solders 135 are respectively configured on the copper pillars 130, wherein the copper pillars 130 are respectively located between the chips 180 and the solders 135. The chip 180 is electrically connected to the bridge 110 through the copper pillars 130 and the solder 135. The solder balls 137 are configured on the chip 180, wherein the chip 180 is electrically connected to the first reconfiguration structure layer 140 through the solder balls 137.

[0061] In short, in this embodiment, the bridge 110 is first packaged face-down and embedded in the intermediate substrate 120. After the bridge 110 is packaged, there is no need for grinding and electroplating of copper pillars. Therefore, the packaging structure 100 of this embodiment has the advantages of simple process and low cost. Furthermore, since the bridge pad 116 of the bridge 110 is flush with the upper surface 121 of the intermediate layer 122, the first reconfiguration structure layer 140 subsequently formed on the intermediate substrate 120 can have better flatness. In addition, when the chip 180 is subsequently bonded to the first reconfiguration structure layer 140 in a flip-chip manner, each chip 180 can be electrically connected to the external circuit through the first reconfiguration structure layer 140, the intermediate substrate 120 and the second reconfiguration circuit layer 150. In addition, the two chips 180 can also be electrically connected to each other through the bridge 110 to achieve partial (or local) high-density interconnection. In other words, the package structure 100 of the present embodiment can have better surface flatness and interconnection density between chips in a more cost-effective manner.

[0062] In summary, in the design of the packaging structure of the present invention, the bridge component having the reconfiguration circuit layer and the bridge pad is embedded in the intermediate substrate, and the bridge pad is flush with the upper surface of the intermediate layer, so that the first reconfiguration structure layer subsequently formed on the intermediate substrate can have better flatness. In addition, when the chip is subsequently bonded to the first reconfiguration structure layer in a flip-chip manner, each chip can be electrically connected to the external circuit through the first reconfiguration structure layer, the intermediate substrate and the second reconfiguration circuit layer. In addition, the two chips can also be electrically connected to each other through the bridge component to achieve partial (partial or local) high-density interconnection. In short, the packaging structure of the present invention can have better surface flatness and interconnection density between chips in a more cost-effective manner.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging structure, characterized in that: include: A bridge component, comprising a silicon substrate, a reconfiguration circuit layer and a plurality of bridge pads, wherein the reconfiguration circuit layer is configured on the silicon substrate, and the plurality of bridge pads are configured on the reconfiguration circuit layer and electrically connected to the reconfiguration circuit layer; An interposer substrate, comprising an interposer layer, a plurality of conductive vias, a plurality of first pads, and a plurality of second pads, wherein the interposer layer has an upper surface and a lower surface opposite to each other, the plurality of conductive vias penetrate the interposer layer and are respectively connected to the plurality of first pads on the upper surface and the plurality of second pads on the lower surface, wherein the bridge member is embedded in the interposer layer, and the plurality of bridge pads are flush with the upper surface; A first reconfiguration structure layer is disposed on the upper surface of the intermediate substrate and is electrically connected to the plurality of first pads and the plurality of bridge pads of the bridge member; A second reconfiguration structure layer is disposed on the lower surface of the intermediate substrate and is electrically connected to the plurality of second pads; as well as A plurality of chips are disposed on the first reconfiguration structure layer and electrically connected to the first reconfiguration structure layer, wherein the plurality of chips are electrically connected to each other through the bridge component.

2. The packaging structure according to claim 1, characterized in that: Also includes: A plurality of chip pads are disposed on the first reconfiguration structure layer and electrically connected to the first reconfiguration structure layer, wherein the plurality of chips are electrically connected to the first reconfiguration structure layer and the bridge component through the plurality of chip pads.

3. The packaging structure according to claim 1, characterized in that: Also includes: A plurality of copper pillars are respectively arranged on the plurality of chips; a plurality of solders, respectively disposed on the plurality of copper pillars, wherein the plurality of copper pillars are respectively located between the plurality of chips and the plurality of solders, and the plurality of chips are electrically connected to the bridge member through the plurality of copper pillars and the plurality of solders; as well as A plurality of solder balls are arranged on the plurality of chips, wherein the plurality of chips are electrically connected to the first reconfiguration structure layer through the plurality of solder balls.

4. The packaging structure according to claim 1, characterized in that: Also includes: A plurality of solder ball pads are disposed on the second reconfiguration structure layer and are electrically connected to the second reconfiguration structure layer; as well as A plurality of solder balls are respectively disposed on the plurality of solder ball pads.

5. A method for manufacturing a packaging structure, characterized in that: include: Providing a bridge component, the bridge component comprising a silicon substrate, a reconfiguration circuit layer and a plurality of bridge pads, wherein the reconfiguration circuit layer is configured on the silicon substrate, and the plurality of bridge pads are configured on the reconfiguration circuit layer and electrically connected to the reconfiguration circuit layer; The bridge component is embedded in an interposer substrate, the interposer substrate includes an interposer layer, a plurality of conductive vias, a plurality of first pads, and a plurality of second pads, the interposer layer has an upper surface and a lower surface opposite to each other, the plurality of conductive vias penetrate the interposer layer and are respectively connected to the plurality of first pads on the upper surface and the plurality of second pads on the lower surface, and the plurality of bridge pads are flush with the upper surface; forming a first reconfiguration structure layer on the upper surface of the interposer substrate, wherein the first reconfiguration structure layer is electrically connected to the plurality of first pads and the plurality of bridge pads of the bridge element; forming a second reconfiguration structure layer on the lower surface of the interposer substrate, wherein the second reconfiguration structure layer is electrically connected to the plurality of second pads; as well as A plurality of chips are arranged on the first reconfiguration structure layer, wherein the plurality of chips are electrically connected to the first reconfiguration structure layer, and the plurality of chips are electrically connected to each other through the bridge component.

6. The method for manufacturing a packaging structure according to claim 5, characterized in that: The step of embedding the bridge component in the intermediate substrate includes: Disposing the bridge member on a temporary substrate, wherein the plurality of bridge pads face the temporary substrate; forming the intermediary layer on the temporary substrate, wherein the intermediary layer covers the bridge component; removing the temporary substrate to expose the upper surface of the interposer; forming a plurality of through holes penetrating the interposer; and The plurality of conductive vias, the plurality of first pads and the plurality of second pads are formed on the interposer, wherein the plurality of conductive vias are respectively located in the plurality of vias and connect the plurality of first pads and the plurality of second pads.

7. The method for manufacturing a packaging structure according to claim 5, characterized in that: Also includes: After forming the first reconfiguration structure layer on the upper surface of the interposer substrate, a plurality of chip pads are formed on the first reconfiguration structure layer and electrically connected to the first reconfiguration structure layer.

8. The method for manufacturing a packaging structure according to claim 5, characterized in that: Before configuring the plurality of chips on the first reconfiguration structure layer, the method further includes: forming a plurality of copper pillars respectively on the plurality of chips; forming a plurality of solders respectively on the plurality of copper pillars, wherein the plurality of copper pillars are located between the plurality of chips and the plurality of solders, and the plurality of chips are electrically connected to the bridge member through the plurality of copper pillars and the plurality of solders; and A plurality of solder balls are formed on the plurality of chips, wherein the plurality of chips are electrically connected to the first reconfiguration structure layer through the plurality of solder balls.

9. The method for manufacturing a packaging structure according to claim 5, characterized in that: Also includes: After forming the second reconfiguration structure layer on the lower surface of the interposer substrate, a plurality of solder ball pads are formed on the second reconfiguration structure layer and electrically connected to the second reconfiguration structure layer; as well as A plurality of solder balls are respectively formed on the plurality of solder ball pads.

10. The method for manufacturing a packaging structure according to claim 5, characterized in that: The bridge member is formed by cutting the wafer into individual pieces.

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