Display panel and display device

Abstract

The embodiment of the present application provides a display panel and a display device, wherein the display panel includes a fan-out line and a power signal line, wherein the power signal line has an opening; in a direction perpendicular to the plane where the display panel is located, the fan-out line includes M fan-out line groups arranged in sequence along a first direction; the i-1th fan-out line group includes a fan-out line with a length of L i‑1 The fan-out line of the i-th fan-out line group includes a fan-out line of length L i The fan-out line of the i+1th fan-out line group includes a fan-out line of length L i+1 The fan-out line, L i‑1 >L i >L i+1 ; length is L i‑1 The overlap area between the fan-out line and the power signal line is S i‑1 , length L i The overlap area between the fan-out line and the power signal line is S i , length L i+1 The overlap area between the fan-out line and the power signal line is S i+1 , S i‑1 ≥S i ≥S i+1 , 2≤i≤M‑1. The embodiments of the present application can improve the packaging effect and display effect of the display panel.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular, relates to a display panel and a display device. Background Art

[0002] With the development of display technology, the types of display panels are becoming more and more extensive. For example, the types of display panels may include liquid crystal display panels (LCD), organic light emitting diode (OLED) display panels, sub-millimeter light emitting diode (Mini LED) display panels, and micro light emitting diode (Micro LED) display panels.

[0003] However, current display panels have problems with poor packaging effect and / or display effect. Summary of the invention

[0004] The embodiments of the present application provide a display panel and a display device, which can improve the packaging effect and display effect of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display panel, the display panel includes a display area and fan-out lines and power signal lines located in a non-display area, the power signal line includes an opening overlapping with at least part of the fan-out lines; in a direction perpendicular to the plane where the display panel is located, the fan-out lines overlapping with the power signal lines include M fan-out line groups arranged in sequence along a first direction, each fan-out line group includes at least one fan-out line, and M is a positive integer; among the M fan-out line groups, the i-1th fan-out line group is located on a side of the i-th fan-out line group away from the display area, and the i+1th fan-out line group is located on a side of the i-th fan-out line group close to the display area; the i-1th fan-out line group includes a fan-out line group with a length of L i-1 The fan-out line of the i-th fan-out line group includes a fan-out line of length L i The fan-out line of the i+1th fan-out line group includes a fan-out line of length L i+1 The fan-out line, L i-1 >L i >L i+1 ; In the direction perpendicular to the plane where the display panel is located, the length is L i-1 The overlap area between the fan-out line and the power signal line is S i-1 , length L i The overlap area between the fan-out line and the power signal line is S i , length L i+1 The overlap area between the fan-out line and the power signal line is S i+1 , S i-1 ≥S i ≥S i+1, where 2≤i≤M-1.

[0006] In a second aspect, an embodiment of the present application provides a display device, and the display device includes a display panel provided in the first aspect.

[0007] The display panel and display device of the embodiments of the present application, on the one hand, are provided with openings on the power signal lines, which can release the stress generated in the packaging process and improve the packaging effect of the display panel; on the other hand, by adjusting the overlapping relationship between the fan-out lines and the openings on the power signal lines, the overlapping areas of the fan-out lines and the power signal lines in the i-1th fan-out line group, the i-th fan-out line group and the i+1th fan-out line group are made the same or decrease successively, so that the capacitive impedance generated between the fan-out lines and the power signal lines in the i-1th fan-out line group, the i-th fan-out line group and the i+1th fan-out line group is the same or transitions smoothly, avoiding sudden changes in the capacitive impedance generated between the fan-out lines and the power signal lines at different positions or adjacent positions, thereby improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0009] Figure 1 A schematic top view of at least a portion of a display panel provided in an embodiment of the present application;

[0010] Figure 2 Another schematic top view of at least a portion of a display panel provided in an embodiment of the present application;

[0011] Figure 3 A partial top view schematic diagram of a display panel provided in an embodiment of the present application;

[0012] Figure 4 Another partial top view schematic diagram of a display panel provided in an embodiment of the present application;

[0013] Figure 5 A schematic diagram of another partial top view of a display panel provided in an embodiment of the present application;

[0014] Figure 6 A schematic diagram of another partial top view of a display panel provided in an embodiment of the present application;

[0015] Figure 7 A schematic top view of an opening on a power signal line in a display panel provided in an embodiment of the present application;

[0016] Figure 8A schematic diagram of another partial top view of a display panel provided in an embodiment of the present application;

[0017] Fig. 9 Another schematic top view of an opening on a power signal line in a display panel provided by an embodiment of the present application;

[0018] Fig.10 A schematic diagram of another partial top view of a display panel provided in an embodiment of the present application;

[0019] Fig.11 A schematic diagram of another partial top view of a display panel provided in an embodiment of the present application;

[0020] Fig.12 A schematic diagram of another partial top view of a display panel provided in an embodiment of the present application;

[0021] Fig.13 A schematic diagram of another partial top view of a display panel provided in an embodiment of the present application;

[0022] Fig.14 A schematic diagram of another partial top view of a display panel provided in an embodiment of the present application;

[0023] Fig.15 A schematic diagram of another partial top view of a display panel provided in an embodiment of the present application;

[0024] Fig.16 A schematic diagram of another partial top view of a display panel provided in an embodiment of the present application;

[0025] Fig.17 A schematic diagram of another partial top view of a display panel provided in an embodiment of the present application;

[0026] Fig.18 for Fig.17 A schematic cross-sectional view of the display panel shown in line AA';

[0027] Fig.19 for Fig.17 Another schematic cross-sectional view of the display panel along the line AA' is shown;

[0028] Fig. 20 A partial cross-sectional schematic diagram of a display area in a display panel provided in an embodiment of the present application;

[0029] Fig.21 is a schematic diagram of capacitance impedance variation curves of fan-out lines at different positions of a display panel when the overlapping relationship between the fan-out lines and the openings on the power signal lines is not adjusted;

[0030] Fig. 22A schematic diagram of capacitance impedance variation curves of fan-out lines at different positions of a display panel after adjusting the overlapping relationship between the fan-out lines and the openings on the power signal lines;

[0031] Fig.23 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0033] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0034] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0035] Since there may be process errors in the processing of the display panel, such as errors that occur during etching, the embodiments of the present application are described in accordance with idealized shapes or positional relationships when introducing the shape of the opening or the positional relationship between different devices. It is easy to understand that as long as the shape of the opening in practice is similar to the shape of the opening mentioned in the embodiments of the present application, it can be understood as belonging to the shape of the opening mentioned in the embodiments of the present application. For example, a rectangle includes a rounded rectangle. The verticality in the embodiments of the present application includes the verticality under the processing error allowed, and the parallelism in the embodiments of the present application includes the parallelism under the processing error allowed.

[0036] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0037] In the embodiment of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure, and the first node, the second node and the third node are not actual circuit units.

[0038] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0039] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the prior art:

[0040] As mentioned above, the inventors of the present application have discovered that the display panel has technical problems of poor packaging effect and / or display effect.

[0041] In order to solve the above technical problems, the inventors of this application first studied and analyzed the root causes of the above technical problems. The specific research and analysis process is as follows:

[0042] The inventors of the present application have discovered that stress is generated in the display panel during the process of setting the frame sealing glue (i.e., the packaging process). On the one hand, the generated stress cannot be released, which will cause the frame sealing glue to deform, and then cause the packaging to fail, resulting in poor packaging effect of the display panel; on the other hand, the generated stress will be applied to the power signal line that overlaps with the frame sealing glue in a direction perpendicular to the plane of the display panel, causing damage or even breakage of the power signal line, thereby resulting in poor display effect of the display panel.

[0043] In view of the above research findings of the inventors, the embodiments of the present application provide a display panel and a display device, which can improve the packaging effect and display effect of the display panel.

[0044] like Figure 1 As shown, the display panel 20 provided in the embodiment of the present application may include a display area AA and a non-display area NA, and the non-display area NA may include a step area NA1 located on one side of the display area AA. In the step area NA1, a fan-out line 201 and a power signal line 202 are provided. The fan-out line 201 may be connected to the data signal line in the display area AA for transmitting the data signal Vdata. The power signal line 202 may include a first power signal line PVDD and / or a second power signal line PVEE. An opening k1 is provided on the power signal line 202 (i.e., the first power signal line PVDD and / or the second power signal line PVEE). The opening k1 may be at least located at the portion where the power signal line 202 overlaps with the packaging area 100. The opening k1 provided on the power signal line 202 can release the stress generated during the packaging process, prevent the deformation of the frame sealant, and enhance the packaging effect of the display panel. In addition, the stress generated during the packaging process can be prevented from damaging the power signal line 202.

[0045] In addition, in order to reduce the size of the step area NA1 and achieve a narrow step, the inclination amplitude of the fan-out line 201 can be set to be larger, and most of the fan-out line 201 can overlap with the vertical part structure 202 s of the power signal line 202 .

[0046] The inventors of the present application further discovered that, in a direction perpendicular to the plane where the display panel 20 is located, the fan-out lines 201 at different positions or adjacent positions may overlap with openings k1 of different numbers or areas on the power signal line 202, which may cause a sudden change in the overlapping area between the fan-out lines 201 at different positions or adjacent positions and the power signal line 202 (the first power signal line PVDD and / or the second power signal line PVEE), thereby causing a sudden change in the coupling capacitance generated between the fan-out lines 201 at different positions or adjacent positions and the power signal line 202, resulting in irregular changes in the load of the fan-out lines 201, causing mura phenomenon to occur in the display panel, such as vertical stripes appearing in the display panel.

[0047] Furthermore, on the basis of improving the packaging effect of the display panel, the embodiment of the present application designs the overlapping relationship between the fan-out line and the opening on the power signal line, so that the load of the fan-out line changes monotonically, thereby improving the display effect of the display panel.

[0048] Specifically, by adjusting the overlapping relationship between the fan-out line and the opening on the power signal line, such as adjusting the position and / or size of the opening on the power signal line, or adjusting the routing method of the fan-out line, the overlapping area between the fan-out line and the power signal line in multiple adjacent fan-out line groups is made the same or decreases successively, so that the capacitive impedance generated between the fan-out line and the power signal line in multiple adjacent fan-out line groups is made the same or transitions smoothly, avoiding sudden changes in the capacitive impedance generated between the fan-out line and the power signal line at different positions or adjacent positions, thereby improving or even eliminating the mura phenomenon of the display panel on the basis of improving the packaging effect of the display panel, thereby improving the display effect of the display panel.

[0049] Combine the following Figure 2 and Figure 3 The display panel provided in the embodiment of the present application is introduced in detail.

[0050] First of all, it should be noted that the above Figure 1 And the following Figure 2 The structure of the display panel 20 of the embodiment of the present application is only illustrative and does not constitute a limitation on the embodiment of the present application. Figure 1 or Figure 2 The shapes and routing methods of the first power signal line PVDD, the second power signal line PVEE and the fan-out line 201 can be changed at will, and the number and position of the binding pads in the display panel 20 and the number and position of the driving chips can be changed at will.

[0051] Combination Figure 2 and Figure 3 As shown, the display panel 20 provided in the embodiment of the present application includes a display area AA and a fan-out line 201 and a power signal line 202 located in a non-display area NA. Exemplarily, the non-display area NA may include a step area NA1 located on one side of the display area AA, and the fan-out line 201 and the power signal line 202 may be set in the step area NA1. The fan-out line 201 can be connected to the data signal line in the display area AA for transmitting the data signal Vdata. The power signal line 202 may include a first power signal line PVDD and / or a second power signal line PVEE. It can be understood that the first power signal line PVDD can be used to provide a positive voltage signal, such as providing a voltage signal of 4.6V or other positive voltage values. The second power signal line PVEE can be used to provide a negative voltage signal, such as providing a voltage signal of -4.6V or other negative voltage values.

[0052] The power signal line 202 includes an opening k1 that overlaps with at least part of the fan-out line 201. The opening k1 can, for example, release the stress generated during the packaging process, thereby preventing the power signal line 202 from breaking due to stress. It should be noted that, unless otherwise specified, the "overlap" in the embodiment of the present application refers to the overlap between different components in a direction perpendicular to the plane where the display panel 20 is located. That is, the power signal line 202 includes an opening k1 that overlaps with at least part of the fan-out line 201 in a direction perpendicular to the plane where the display panel 20 is located. Among them, the plane where the display panel 20 is located may include the light-emitting surface (display surface) or the backlight surface of the display panel 20. In addition, it should be noted that the opening k1 is not limited to the first part 202a of the power signal line 202 that overlaps with the packaging area 100, and can also be located on the power signal line 202 other than the first part 202a, such as the opening k1 can also be located in the second part 202b of the power signal line 202. The embodiment of the present application does not limit the distribution position of the opening k1.

[0053] Continue to see Figure 3 In a direction perpendicular to the plane where the display panel 20 is located, the fan-out line 201 overlapping the power signal line 202 includes M fan-out line groups P arranged in sequence along the first direction X, each fan-out line group P includes at least one fan-out line 201, and M is a positive integer. For ease of illustration, the M fan-out line groups P in the figure are respectively represented by P1 to P M For example, P1 represents the first fan-out line group P, P i represents the i-th fan-out line group P, P M represents the Mth fan-out line group P. Exemplarily, the "fan-out line 201 overlapping with the power signal line 202" here may specifically be a fan-out line 201 overlapping with the portion (e.g., the first portion 202a) where the opening k1 on the power signal line 202 is distributed. In addition, each fan-out line group P includes at least one fan-out line 201, which can be understood as each fan-out line group P including one fan-out line 201 or multiple fan-out lines 201. For example, Figure 3 The exemplary embodiment shows that each fan-out line group P includes three fan-out lines 201. Figure 4 It is exemplarily shown that each fan-out line group P includes one fan-out line 201. It is easy to understand that each fan-out line group P may also include other numbers of fan-out lines 201 other than one or three, such as two fan-out lines 201, 10 fan-out lines 201, or other numbers of fan-out lines 201. Moreover, the numbers of fan-out lines 201 in different fan-out line groups P may be the same or different, and this is not limited in the embodiments of the present application.

[0054] Among the M fan-out line groups P, the i-1th fan-out line group P is located on the side of the i-th fan-out line group P away from the display area AA, and the i+1th fan-out line group P is located on the side of the i-th fan-out line group P close to the display area AA. Among them, the i-th fan-out line group P is any fan-out line group P among the M fan-out line groups P, 2≤i≤M-1. For example, when i=2, the first fan-out line group P is located on the side of the second fan-out line group P away from the display area AA, and the third fan-out line group P is located on the side of the second fan-out line group P close to the display area AA. The i-1th fan-out line group P includes a fan-out line group P with a length of L i-1 The fan-out line 201 of the i-th fan-out line group P includes a length of L i The fan-out line 201 of the i+1th fan-out line group P includes a length of L i+1 Fan-out line 201, L i-1 >L i >L i+1 .

[0055] It should be noted that, when each fan-out line group P includes multiple fan-out lines 201, the lengths of the multiple fan-out lines 201 in the fan-out line group P may be the same or different. Taking the i-1th fan-out line group P as an example, when the i-1th fan-out line group P includes multiple fan-out lines 201, the lengths of the multiple fan-out lines 201 in the i-1th fan-out line group P may be the same, for example, all L i-1 Of course, the lengths of the plurality of fan-out lines 201 in the i-1th fan-out line group P may also be different. When the lengths of the plurality of fan-out lines 201 in the i-1th fan-out line group P are different, for example, the average length of the plurality of fan-out lines 201 in the i-1th fan-out line group P may be L i-1 For example, the length of the longest fan-out line 201 in the i-1th fan-out line group P may be L i-1 For example, the length of the shortest fan-out line 201 in the i-1th fan-out line group P may be L i-1 . The same applies to the i-th fan-out line group P and the i+1-th fan-out line group P. In some embodiments, for example, the length of the shortest fan-out line 201 in the i-1-th fan-out line group P may be greater than the length of the longest fan-out line 201 in the i-th fan-out line group P, and the length of the shortest fan-out line 201 in the i-th fan-out line group P may be greater than the length of the longest fan-out line 201 in the i+1-th fan-out line group P. In an embodiment of the present application, the length of the fan-out line 201 may refer to the total length of the fan-out line 201 in the step area NA1. For example, the length of the fan-out line 201 may refer to the length of the fan-out line 201 from the connection point between the fan-out line 201 and the data signal line to the binding pad to which the fan-out line 201 is bound.

[0056] In the direction perpendicular to the plane where the display panel is located, the length is L i-1 The overlapping area of ​​the fan-out line 201 (i.e., the fan-out line 201 in the i-1th fan-out line group P) and the power signal line 202 is S i-1 , length L i The overlapping area of ​​the fan-out line 201 (i.e., the fan-out line 201 in the i-th fan-out line group P) and the power signal line 202 is S i , length L i+1 The overlapping area of ​​the fan-out line 201 (i.e., the fan-out line 201 in the i+1th fan-out line group P) and the power signal line 202 is S i+1 , S i-1 ≥S i ≥S i+1 .

[0057] It is easy to understand that, in the direction perpendicular to the plane where the display panel is located, as the overlapping area between the fan-out line 201 and the opening k1 increases, the overlapping area between the fan-out line 201 and the power signal line 202 will decrease. Therefore, by adjusting the overlapping relationship between the fan-out line 201 and the opening k1 on the power signal line 202, the overlapping area between the fan-out line 201 and the power signal line 202 in the i-1th fan-out line group P, the i-th fan-out line group P and the i+1th fan-out line group P can satisfy S i-1 ≥S i ≥S i+1 .

[0058] In some specific embodiments, the overlapping areas of the fan-out lines 201 and the power signal lines 202 in the i-1th fan-out line group P, the i-th fan-out line group P, and the i+1th fan-out line group P may satisfy S i-1 =S i =S i+1 That is, the overlapping areas of the fan-out lines 201 and the power signal lines 202 in the i-1th fan-out line group P, the i-th fan-out line group P, and the i+1th fan-out line group P are the same. In this way, the capacitive impedance generated between the fan-out lines 201 and the power signal lines 202 in the i-1th fan-out line group P, the i-th fan-out line group P, and the i+1th fan-out line group P can be made the same, thereby avoiding sudden changes in the capacitive impedance generated between the fan-out lines and the power signal lines at different positions or adjacent positions, thereby improving or even eliminating the mura phenomenon of the display panel.

[0059] Here, it should be noted that, affected by material factors, the fan-out line 201 itself has impedance. For the sake of distinction, it is referred to here as resistance impedance. It is easy to understand that the resistance impedance of the fan-out line 201 will increase as the length of the fan-out line increases. Therefore, the resistance impedance of the fan-out line 201 in the i-1th fan-out line group P, the i-th fan-out line group P and the i+1th fan-out line group P is different, such as decreasing in sequence. For ease of understanding, the resistance impedance of the fan-out line in the i-1th fan-out line group P is represented by R1, the resistance impedance of the fan-out line in the i-th fan-out line group P is represented by R2, and the resistance impedance of the fan-out line in the i+1th fan-out line group P is represented by R3. Due to L i-1 >L i >L i+1 , so R1>R2>R3. When R1, R2 and R3 change smoothly, the human eye usually cannot observe the mura phenomenon of the display panel, which can be regarded as no mura phenomenon. Since the capacitive impedance Rc generated between the fan-out line 201 and the power signal line 202 in the i-1th fan-out line group P, the i-th fan-out line group P and the i+1th fan-out line group P is the same, R1+Rc>R2+Rc>R3+Rc, that is, the total impedance (the sum of the resistance impedance and the capacitance impedance) of the fan-out line 201 in multiple adjacent fan-out line groups P still changes smoothly, so the human eye cannot observe the mura phenomenon of the display panel.

[0060] In some other specific embodiments, the overlapping areas of the fan-out lines 201 and the power signal lines 202 in the i-1th fan-out line group P, the i-th fan-out line group P, and the i+1th fan-out line group P may satisfy S i-1 >S i >S i+1 That is, the overlapping areas of the fan-out lines 201 and the power signal lines 202 in the i-1th fan-out line group P, the i-th fan-out line group P, and the i+1th fan-out line group P are reduced successively. In this way, the capacitive impedance generated between the fan-out lines 201 and the power signal lines 202 in the i-1th fan-out line group P, the i-th fan-out line group P, and the i+1th fan-out line group P can be smoothly transitioned, avoiding sudden changes in the capacitive impedance generated between the fan-out lines and the power signal lines at different positions or adjacent positions, thereby improving or even eliminating the mura phenomenon of the display panel.

[0061] For ease of understanding, the resistance impedance of the fan-out line in the i-1th fan-out line group P is represented by R1, the resistance impedance of the fan-out line in the i-th fan-out line group P is represented by R2, and the resistance impedance of the fan-out line in the i+1th fan-out line group P is represented by R3. At the same time, the capacitive impedance generated between the fan-out line 201 in the i-1th fan-out line group P and the power signal line 202 is represented by Rc1, the capacitive impedance generated between the fan-out line 201 in the i-th fan-out line group P and the power signal line 202 is represented by Rc2, and the capacitive impedance generated between the fan-out line 201 in the i+1th fan-out line group P and the power signal line 202 is represented by Rc3. Due to the overlapping area S i-1 >S i >S i+1 , so Rc1>Rc2>Rc3, that is, the capacitance impedance changes steadily. i-1 >L i >L i+1 , so R1>R2>R3. Therefore, the total impedance of the fan-out line 201 satisfies R1+Rc1>R2+Rc2>R3+Rc3, that is, the total impedance (the sum of the resistance impedance and the capacitance impedance) of the fan-out line 201 in the adjacent plurality of fan-out line groups P changes smoothly, so the human eye cannot observe the mura phenomenon of the display panel.

[0062] In the display panel 10 of the embodiment of the present application, the overlapping areas of the fan-out lines 201 and the power signal lines 202 in the adjacent multiple fan-out line groups P are the same or decrease successively, so that the capacitive impedance generated between the fan-out lines 201 and the power signal lines 202 in the adjacent multiple fan-out line groups P is the same or transitions smoothly, avoiding sudden changes in the capacitive impedance generated between the fan-out lines 201 and the power signal lines 202 at different positions or adjacent positions, thereby improving or even eliminating the mura phenomenon of the display panel.

[0063] The display panel 10 is described below in conjunction with some embodiments of the present application.

[0064] Continue to see Figure 2 and Figure 3In some specific embodiments, optionally, among the M fan-out line groups P, the lengths of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P decrease successively. That is, the lengths of the fan-out lines 201 in the M fan-out line groups P change monotonically. In the direction perpendicular to the plane where the display panel 20 is located, the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P have the same overlapping area with the power signal line 202. For example, when the overlapping lengths L of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P and the power signal line 202 are equal, the overlapping lengths or overlapping areas of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P and at least one opening k1 can be equal, so that the overlapping areas of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P and the power signal line 202 are the same. The overlapping length may be a minimum distance in the second direction Y, and the second direction Y intersects with the first direction X.

[0065] like Figure 4 As shown, when the overlapping lengths L between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the power signal line 202 are not equal, the overlapping lengths or overlapping areas between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and at least one opening k1 can also be made equal, so that the overlapping areas between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the power signal line 202 are the same.

[0066] In this way, since the overlapping areas of the fan-out lines 201 and the power signal lines 202 in the 1st fan-out line group P to the Mth fan-out line group P are the same, the capacitive impedances generated between the fan-out lines 201 and the power signal lines 202 in the 1st fan-out line group P to the Mth fan-out line group P are the same, thereby avoiding sudden changes in the capacitive impedances generated between the fan-out lines and the power signal lines at different positions or adjacent positions, so that the total impedance (the sum of the resistance impedance and the capacitance impedance) of the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P changes smoothly, thereby improving or even eliminating the mura phenomenon of the display panel.

[0067] like Figure 5 As shown, in some other specific embodiments, optionally, Figure 3 or Figure 4 The embodiment shown is different in that, in a direction perpendicular to the plane where the display panel 20 is located, the overlapping areas of the fan-out lines 201 and the power signal lines 202 in the first fan-out line group P to the Mth fan-out line group P gradually decrease.

[0068] In this way, since the overlapping areas of the fan-out lines 201 and the power signal lines 202 in the 1st fan-out line group P to the Mth fan-out line group P decrease successively, the capacitive impedance generated between the fan-out lines 201 and the power signal lines 202 in the 1st fan-out line group P to the Mth fan-out line group P changes smoothly, avoiding sudden changes in the capacitive impedance generated between the fan-out lines and the power signal lines at different positions or adjacent positions, so that the total impedance of the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P changes smoothly, thereby improving or even eliminating the mura phenomenon of the display panel.

[0069] In the embodiment of the present application, the shape, area and / or position of the opening k1 can be flexibly adjusted according to actual conditions to achieve the purpose of making the overlapping area of ​​the fan-out lines 201 and the power signal lines 202 in the plurality of fan-out line groups P the same or changing smoothly. For ease of understanding, the following is an explanation in conjunction with some examples of the shape, area and / or position of the opening k1.

[0070] like Figure 6 As shown, according to some embodiments of the present application, optionally, the power signal line 202 may include Q openings k1, and the Q openings k1 may extend along the first direction X, where Q is a positive integer. Exemplarily, Q may be an integer of 1 or greater than 1. In a direction perpendicular to the plane where the display panel 20 is located, the fan-out lines 201 in the M fan-out line groups P may overlap with the Q openings k1. It should be noted that at least partial overlap of the fan-out line 201 with the opening k1 can be understood as overlap, for example, if the fan-out line 201 overlaps only one corner of the opening k1, it can be understood as the fan-out line 201 overlapping with the opening k1. Along the direction from the i+1th fan-out line group P to the i-1th fan-out line group P, the width w of the opening k1 remains unchanged. Among them, the width w of the opening k1 can be the minimum distance of the opening k1 along the second direction Y, and the second direction Y intersects with the first direction X. The minimum distance can be understood as the minimum straight-line distance, or the vertical distance. For example, when the shape of the opening k1 is a rectangle, and the first side and the second side of the rectangle are perpendicular to the extension direction of the fan-out line 201, the width w of the opening k1 may be the length of the third side or the fourth side of the rectangle, wherein the third side of the rectangle is perpendicular to the first side, and the fourth side of the rectangle is opposite to the third side of the rectangle.

[0071] exist Figure 6In the embodiment shown, since the fan-out lines 201 in the M fan-out line groups P overlap with the Q openings k1 at the same time, and the widths of the Q openings k1 remain unchanged, the overlapping areas of the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the Q openings k1 can be the same. In the case where the overlapping lengths L of the fan-out lines 201 and the power signal lines 202 in the 1st fan-out line group P to the Mth fan-out line group P are equal, if the first portion 202a of the power signal line 202 that overlaps with the packaging area is rectangular, the overlapping areas of the fan-out lines 201 and the power signal lines 202 in the 1st fan-out line group P to the Mth fan-out line group P can be the same, thereby improving or even eliminating the display unevenness (mura) phenomenon of the display panel. In addition, the long strip opening shape is more conducive to adjusting the overlapping area of ​​the fan-out lines 201 and the power signal lines 202, and facilitating the implementation of the solution.

[0072] Continue to see Figure 6 According to some embodiments of the present application, optionally, in a direction perpendicular to the plane where the display panel 20 is located, the fan-out line 201 in the M fan-out line group P may overlap with the first part b1 of the Q openings k1. The first part b1 may be understood as at least a part of the opening k1, for example, the first part b1 may be the middle part of the opening k1. Of course, in some examples, the first part b1 may also be the entire opening k1, that is, the entire opening k1 may be the first part b1, and the embodiments of the present application are not limited to this. It is worth noting that in a direction perpendicular to the plane where the display panel 20 is located, the shape of the first part b1 of the opening k1 may include a first figure whose width remains unchanged. Combined with Figure 7 As shown, the first figure T1 includes but is not limited to a rectangle, a wave or a sawtooth shape. It should be noted that the shapes of the other parts of the opening k1 except the first part b1 can be any shape, such as a circle, a rectangle, a triangle or an irregular shape.

[0073] In this way, since the fan-out lines 201 in the M fan-out line groups P overlap with the first parts b1 of the Q openings k1 at the same time, and the first part b1 of the openings k1 is a first pattern with a constant width, the overlapping areas of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P and the Q openings k1 can be the same. In the case where the overlapping lengths L of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P and the power signal line 202 are equal, such as when the first part 202a of the power signal line 202 overlapping with the packaging area is rectangular, the overlapping areas of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P and the power signal line 202 can be the same, thereby improving or even eliminating the mura phenomenon of the display panel.

[0074] like Figure 8As shown, according to other embodiments of the present application, optionally, Figure 6 The embodiment shown is different in that the width w of the opening k1 can be gradually reduced along the direction from the i+1th fan-out line group P to the i-1th fan-out line group P. The width w of the opening k1 can be the minimum distance of the opening k1 along the second direction Y, which intersects the first direction X.

[0075] exist Figure 8 In the illustrated embodiment, since the fan-out lines 201 in the M fan-out line groups P overlap with the Q openings k1 at the same time, and the widths of the Q openings k1 gradually change, the overlapping areas of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P and the Q openings k1 can be gradually increased. In the case where the overlapping lengths L of the fan-out lines 201 and the power signal line 202 in the first fan-out line group P to the M-th fan-out line group P are equal, if the first portion 202a of the power signal line 202 overlapping the packaging area is rectangular, the overlapping areas of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P and the power signal line 202 can be gradually reduced, so that the total impedance (the sum of the resistance impedance and the capacitance impedance) of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P changes smoothly, thereby improving or even eliminating the mura phenomenon of the display panel. In addition, the long strip opening shape is more conducive to adjusting the overlapping area between the fan-out line 201 and the power signal line 202, which facilitates the implementation of the solution.

[0076] Combination Figure 4 As shown, when the overlapping lengths L of the fan-out lines 201 and the power signal lines 202 in the first fan-out line group P to the M-th fan-out line group P are not equal, such as when the first portion 202a of the power signal line 202 overlapping the packaging area is an inverted trapezoid, by gradually increasing the overlapping areas of the fan-out lines 201 and the Q openings k1 in the first fan-out line group P to the M-th fan-out line group P, the overlapping areas of the fan-out lines 201 and the power signal lines 202 in the first fan-out line group P to the M-th fan-out line group P can be made the same or gradually reduced, so that the total impedance (the sum of the resistance impedance and the capacitance impedance) of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P changes smoothly, thereby improving or even eliminating the mura phenomenon of the display panel.

[0077] Continue to see Figure 8 According to some embodiments of the present application, optionally, in a direction perpendicular to the plane where the display panel 20 is located, the shape of the first part b1 of k1 may include a second pattern with a gradually decreasing width. Fig. 9As shown, the second shape T2 includes but is not limited to a trapezoid, a triangle or an arc. It should be noted that the shapes of the other parts of the opening k1 except the first part b1 can be any shape, such as a circle, a rectangle, a triangle or an irregular shape.

[0078] In this way, since the fan-out lines 201 in the M fan-out line groups P overlap with the first parts b1 of the Q openings k1 at the same time, and the first part b1 of the openings k1 is a second pattern with a gradually decreasing width, the overlapping area of ​​the fan-out lines 201 in the first fan-out line group P to the M fan-out line group P and the Q openings k1 can be gradually increased, so that the overlapping area of ​​the fan-out lines 201 in the first fan-out line group P to the M fan-out line group P and the power signal line 202 is the same or gradually decreases. In this way, the total impedance (the sum of the resistance impedance and the capacitance impedance) of the fan-out lines 201 in the first fan-out line group P to the M fan-out line group P can be made to change smoothly, thereby improving or even eliminating the mura phenomenon of the display panel.

[0079] like Figure 6 As shown, according to some embodiments of the present application, optionally, the shape of the first part b1 of the opening k1 can be a rectangle. In a direction perpendicular to the plane where the display panel 20 is located, the first part b1 of the opening k1 includes a first side a1 and a second side a2 relative to each other, and the extension direction of the first side a1 and the second side a2 can be perpendicular to the extension direction of the fan-out line 201. For example, the extension direction of the first side a1 and the second side a2 is a first direction X, the extension direction of the fan-out line 201 is a second direction Y, and the first direction X and the second direction Y can be perpendicular. It is easy to understand that in some other examples, the first side of the first part b1 of the opening k1 can also be Figure 6 The second side of the first part b1 of the opening k1 may also be Figure 6 At this time, the extension direction of the first side d1 and the second side d2 may be parallel to the extension direction of the fan-out line 201 .

[0080] In this way, when the shape of the first part b1 of the opening k1 is a rectangle, the extension direction of a pair of sides of the first part b1 is perpendicular to the extension direction of the fan-out line 201, and the extension direction of the other pair of sides is parallel to the extension direction of the fan-out line 201, thereby ensuring that the overlapping areas of the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the Q openings k1 are the same, which is beneficial to the adjustment of the overlapping area between the fan-out line 201 and the power signal line 202 and facilitates the implementation of the solution.

[0081] Combination Figure 7 and Fig. 9As shown, it is easy to understand that when the shape of the first part b1 of the opening k1 is wavy or sawtooth, the extension direction of the first side d1 and the second side d2 relative to the wavy or sawtooth shape can be parallel to the extension direction of the fan-out line. When the shape of the first part b1 of the opening k1 is a trapezoid, the extension direction of the first side d1 (upper base) and the second side d2 (lower base) relative to the trapezoid can be parallel to the extension direction of the fan-out line. When the shape of the first part b1 of the opening k1 is a triangle, the extension direction of the first side d1 of the triangle can be parallel to the extension direction of the fan-out line. When the shape of the first part b1 of the opening k1 is an arc, the extension direction of the straight side d1 of the arc can be parallel to the extension direction of the fan-out line. As a result, it can be beneficial to adjust the overlapping area of ​​the fan-out line 201 and the power signal line 202, and facilitate the implementation of the solution.

[0082] like Fig.10 As shown, according to some embodiments of the present application, optionally, the power signal line 202 may include P openings k1, the P openings k1 may extend along a first direction X, and the P openings k1 may be arranged in sequence along a second direction Y intersecting the first direction X, and P is a positive integer. Exemplarily, P ≥ 2. Along the second direction Y, the area or length of at least part of the P openings k1 may gradually decrease. It should be noted that, in some examples, the area or length of the P openings k1 may gradually decrease. In other examples, the area or length of part of the P openings k1 may gradually decrease, while the area or length of another part of the openings k1 remains unchanged.

[0083] like Fig.11 As shown, according to other embodiments of the present application, optionally, Fig.10 The embodiment shown is different in that the area or length of at least some of the P openings k1 may gradually increase along the second direction Y. For example, the area or length of the P openings k1 may gradually increase, or only the area or length of some of the P openings k1 may gradually increase.

[0084] In this way, since the area or length of at least part of the P openings k1 gradually decreases or increases along the second direction, the number of openings k1 that the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P can overlap can be different, so that the overlapping area between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the power signal line 202 can be different, such as decreasing successively.

[0085] exist Fig.10 or Fig.11In the illustrated embodiment, the first portion 202a of the power signal line 202 may be rectangular. The extension direction of the first side A1 and the second side A2 relative to the first portion 202a may intersect with the extension direction of the fan-out lines 201 in the M fan-out line groups P. Without considering the opening k1, the overlap length L of the fan-out lines 201 in the first fan-out line group P to the M fan-out line group P and the first portion 202a of the power signal line 202 is equal. Therefore, when the number of the openings k1 overlapped by the fan-out lines 201 in the first fan-out line group P to the M fan-out line group P is different, the overlap area of ​​the fan-out lines 201 in the first fan-out line group P to the M fan-out line group P and the power signal line 202 may be reduced successively, so that the capacitance impedance and the total impedance (the sum of the resistance impedance and the capacitance impedance) of the fan-out lines 201 in the first fan-out line group P to the M fan-out line group P change smoothly, thereby improving or even eliminating the mura phenomenon of the display panel.

[0086] like Fig.12 As shown, according to some other embodiments of the present application, optionally, the first portion 202a of the power signal line 202 may be in an inverted trapezoidal shape. Without considering the opening k1, the overlapping lengths L between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the first portion 202a of the power signal line 202 are not equal, for example, the overlapping lengths L between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the first portion 202a of the power signal line 202 increase sequentially. In this way, when the number of openings k1 overlapped by the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P decreases successively, the overlapping areas of the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the power signal line 202 can be the same or decrease successively, so that the capacitive impedance and the total impedance (the sum of the resistive impedance and the capacitive impedance) of the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P change smoothly, thereby improving or even eliminating the mura phenomenon of the display panel.

[0087] Continue to see Fig.10 In some specific embodiments, optionally, along the direction from the i+1th fan-out line group P to the i-1th fan-out line group P, the width w of the opening k1 remains unchanged. The width w of the opening k1 may be the minimum distance of the opening k1 along the second direction Y, and the second direction Y intersects the first direction X.

[0088] Continue to see Fig.10 According to some embodiments of the present application, optionally, in a direction perpendicular to the plane where the display panel 20 is located, the shape of the first portion b1 of the opening k1 may include a first pattern with a constant width. Figure 7As shown, the first figure T1 includes but is not limited to a rectangle, a wave or a sawtooth shape. It should be noted that the shapes of the other parts of the opening k1 except the first part b1 can be any shape, such as a circle, a rectangle, a triangle or an irregular shape.

[0089] In this way, since the number of openings k1 overlapped by the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P is different, and the first part b1 of the opening k1 is a first figure with a constant width, the overlapping areas of the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the openings k1 can be different, such as increasing successively, thereby making the overlapping areas of the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the power signal line 202 decrease successively.

[0090] like Fig.13 As shown, according to other embodiments of the present application, optionally, Fig.10 The embodiment shown is different in that the width w of the opening k1 can be gradually reduced along the direction from the i+1th fan-out line group P to the i-1th fan-out line group P. The width w of the opening k1 can be the minimum distance of the opening k1 along the second direction Y, which intersects the first direction X.

[0091] exist Fig.13 In the illustrated embodiment, since the numbers of openings k1 overlapped by the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P are different and the widths of the openings k1 gradually change, the overlapping areas between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the openings k1 can gradually increase, thereby causing the overlapping areas between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the power signal lines 202 to decrease successively. When the overlapping length L of the fan-out line 201 and the power signal line 202 in the first fan-out line group P to the Mth fan-out line group P is equal, if the first part 202a of the power signal line 202 overlapping the packaging area is rectangular, the overlapping area of ​​the fan-out line 201 and the power signal line 202 in the first fan-out line group P to the Mth fan-out line group P can be gradually reduced, so that the total impedance (the sum of the resistance impedance and the capacitance impedance) of the fan-out line 201 in the first fan-out line group P to the Mth fan-out line group P changes smoothly, thereby improving or even eliminating the mura phenomenon of the display panel. In addition, the long strip opening shape is more conducive to adjusting the overlapping area of ​​the fan-out line 201 and the power signal line 202, which facilitates the implementation of the solution.

[0092] Combination Fig.12As shown, when the overlapping lengths L of the fan-out lines 201 and the power signal lines 202 in the first fan-out line group P to the M-th fan-out line group P are not equal, such as when the first portion 202a of the power signal line 202 overlapping the packaging area is an inverted trapezoid, by gradually increasing the overlapping areas of the fan-out lines 201 and the openings k1 in the first fan-out line group P to the M-th fan-out line group P, the overlapping areas of the fan-out lines 201 and the power signal lines 202 in the first fan-out line group P to the M-th fan-out line group P can be made the same or gradually reduced, so that the total impedance (the sum of the resistance impedance and the capacitance impedance) of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P changes smoothly, thereby improving or even eliminating the mura phenomenon of the display panel.

[0093] Continue to see Fig.13 According to some embodiments of the present application, optionally, in a direction perpendicular to the plane where the display panel 20 is located, the shape of the first part b1 of k1 may include a second pattern with a gradually decreasing width. Fig. 9 As shown, the second shape T2 includes but is not limited to a trapezoid, a triangle or an arc. It should be noted that the shapes of the other parts of the opening k1 except the first part b1 can be any shape, such as a circle, a rectangle, a triangle or an irregular shape.

[0094] like Fig.10 and Fig.12 As shown, according to some embodiments of the present application, optionally, the shape of the first portion b1 of the opening k1 may be a rectangle. In a direction perpendicular to the plane where the display panel 20 is located, the first portion b1 of the opening k1 includes a first side a1 and a second side a2 opposite to each other, and the extension direction of the first side a1 and the second side a2 may be perpendicular to the extension direction of the fan-out line 201. It is easy to understand that in other examples, the first side of the first portion b1 of the opening k1 may also be Fig.10 and Fig.12 The second side of the first part b1 of the opening k1 may also be Fig.10 and Fig.12 At this time, the extension direction of the first side d1 and the second side d2 may be parallel to the extension direction of the fan-out line 201 .

[0095] In this way, when the shape of the first part b1 of the opening k1 is a rectangle, the extension direction of a pair of sides of the first part b1 is perpendicular to the extension direction of the fan-out line 201, and the extension direction of the other pair of sides is parallel to the extension direction of the fan-out line 201, which is beneficial to the adjustment of the overlapping area between the fan-out line 201 and the power signal line 202, and facilitates the implementation of the solution.

[0096] Continue to see Fig.10 , Fig.12 or Fig.13According to some embodiments of the present application, optionally, in a direction perpendicular to the plane where the display panel 20 is located, the number of openings k1 overlapped by the fan-out lines 201 in the 1st fan-out line group to the Mth fan-out line group may gradually increase.

[0097] In this way, since the number of openings k1 overlapped by the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P gradually increases, when the width of the first part b1 of the opening k1 remains unchanged or gradually decreases, the overlapping area between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the openings k1 can be increased successively, thereby making the overlapping area between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the power signal line 202 the same or decreasing successively.

[0098] like Fig.14 As shown, according to some embodiments of the present application, optionally, the power signal line 202 may include a plurality of openings k1 arranged in an array and having equal areas. It should be noted that, considering the area difference caused by process errors, the so-called equal area can be that the area ratio of two openings k1 is greater than a preset threshold (such as 90% or other values), and the areas are considered equal. Among the M fan-out line groups P, the number of openings k1 overlapped by the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P is the same. For example, the number of openings k1 overlapped by the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P is n, and n is a positive integer.

[0099] It can be seen that in Fig.14 In the illustrated embodiment, the plurality of openings k1 on the power signal line 202 can still be arranged in an array or evenly distributed, and the routing of the fan-out line 201 is adjusted so that the number of openings k1 overlapped by the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P is the same. In this way, since the areas of the plurality of openings k1 are equal, the overlap areas of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P and the openings k1 are the same, so that the overlap areas of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P and the power signal line 202 can be the same or gradually reduced, so that the capacitance impedance and the total impedance (the sum of the resistance impedance and the capacitance impedance) of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P change steadily, thereby improving or even eliminating the mura phenomenon of the display panel.

[0100] like Fig.15 As shown, according to other embodiments of the present application, optionally, Fig.14The difference of the illustrated embodiment is that, among the M fan-out line groups P, the number of openings k1 overlapped by the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P may gradually increase.

[0101] It can be seen that in Fig.15 In the illustrated embodiment, the plurality of openings k1 on the power signal line 202 can still be arranged in an array or evenly distributed, and by adjusting the routing of the fan-out line 201, the number of openings k1 overlapped by the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P gradually increases. In this way, since the areas of the plurality of openings k1 are equal, the overlapping areas of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P and the openings k1 gradually increase, so that the overlapping areas of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P and the power signal line 202 can be made the same or gradually reduced, so that the capacitance impedance and the total impedance (the sum of the resistance impedance and the capacitance impedance) of the fan-out lines 201 in the first fan-out line group P to the M-th fan-out line group P change steadily, thereby improving or even eliminating the mura phenomenon of the display panel.

[0102] like Fig.14 or Fig.15 As shown, in some specific embodiments, optionally, the fan-out line 201 may include a first sub-fan-out line 201a extending along a first direction X and a second sub-fan-out line 201b extending along a second direction Y. In a direction perpendicular to the plane where the display panel is located, the first sub-fan-out line 201a and / or the second sub-fan-out line 201b overlap with at least one opening k1. That is, by adjusting the routing mode of the fan-out line 201, the first sub-fan-out line 201a can overlap with at least one opening k1, or the second sub-fan-out line 201b can overlap with at least one opening k1, or even the first sub-fan-out line 201a and the second sub-fan-out line 201b can overlap with different openings k1 at the same time, so that the overlapping area of ​​the fan-out line 201 in the 1st fan-out line group P to the Mth fan-out line group P and the power signal line 202 is the same or gradually decreases. It should be noted that the first sub-fan-out line 201a may also extend in directions other than the first direction X, and the second sub-fan-out line 201b may also extend in directions other than the second direction Y, which is not limited in the present application. In addition, in some embodiments, the fan-out line 201 may also include a third sub-fan-out line to an n-th sub-fan-out line, where n is an integer greater than or equal to 3. The extension direction of the third sub-fan-out line to the n-th sub-fan-out line may be the same as or different from the extension direction of the first sub-fan-out line 201a or the second sub-fan-out line 201b.

[0103] like Fig.16As shown, according to some other embodiments of the present application, optionally, the power signal line 202 may include a plurality of openings k1 arranged in an array, and the plurality of openings k1 are arranged into N rows of openings along the first direction X, and each opening row includes at least one opening k1. Along a second direction Y intersecting the first direction X, at least one opening k1 in the j-th row of openings is interlaced with at least one opening k1 in the j+1-th row of openings. The j-th row of openings is any row of openings in the N rows of openings, 1<j≤N-1, and j and N are both positive integers. In a direction perpendicular to the plane where the display panel is located, each fan-out line group P in the M fan-out line groups P overlaps with a row of openings.

[0104] In this way, since each fan-out line group P corresponds to a row of openings, by adjusting the area and / or number of openings k1 in the row of openings corresponding to each fan-out line group P, the overlapping area between the fan-out line 201 in the first fan-out line group P to the Mth fan-out line group P and the openings k1 can be made the same or gradually increase, and then the overlapping area between the fan-out line 201 in the first fan-out line group P to the Mth fan-out line group P and the power signal line 202 can be made the same or gradually decrease, so that the capacitance impedance and the total impedance (the sum of the resistance impedance and the capacitance impedance) of the fan-out line 201 in the first fan-out line group P to the Mth fan-out line group P change smoothly, thereby improving or even eliminating the mura phenomenon of the display panel. In addition, the staggered openings are conducive to the adjustment of the overlapping area between the fan-out line 201 and the power signal line 202, which facilitates the implementation of the solution.

[0105] Continue to see Fig.16 Optionally, the areas of multiple openings k1 in the N rows of openings can be equal. It should be noted that, considering the area difference caused by process errors, the so-called equal area can be that the area ratio of two openings k1 is greater than a preset threshold (such as 90% or other values), which can be regarded as equal area. In this way, since the areas or sizes of multiple openings k1 in the N rows of openings are equal, it is only necessary to adjust the number of openings k1 in the opening row corresponding to each fan-out line group P to achieve the adjustment of the overlapping area between the fan-out line 201 and the power signal line 202, which is convenient for the design and detection of the overlapping area between the fan-out line 201 and the power signal line 202.

[0106] Continue to see Fig.16 According to some embodiments of the present application, optionally, the Nth opening row is located on the side of the 1st opening row close to the display area AA, and the number of openings k1 in the 1st opening row to the Nth opening row may be the same. That is, the number of openings k1 overlapped by the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P may be the same.

[0107] In this way, the overlapping areas between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the opening k1 can be made the same, and further, the overlapping areas between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the power signal line 202 can be made the same or gradually reduced, so that the capacitive impedance and the total impedance (the sum of the resistive impedance and the capacitive impedance) of the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P change smoothly, thereby improving or even eliminating the mura phenomenon of the display panel.

[0108] like Fig.17 As shown, according to other embodiments of the present application, optionally, Fig.16 The embodiment shown is different in that the number of openings k1 in the first opening row to the Nth opening row can be increased sequentially. That is, the number of openings k1 overlapped by the fan-out lines 201 in the first fan-out line group P to the Mth fan-out line group P can be increased sequentially.

[0109] In this way, the overlapping area between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the opening k1 can be gradually increased, so that the overlapping area between the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P and the power signal line 202 can be made the same or gradually reduced, so that the capacitive impedance and the total impedance (the sum of the resistive impedance and the capacitive impedance) of the fan-out lines 201 in the 1st fan-out line group P to the Mth fan-out line group P change smoothly, thereby improving or even eliminating the mura phenomenon of the display panel.

[0110] Continue to see Figures 14 to 17 According to some embodiments of the present application, the opening k1 may optionally include an arbitrary polygonal opening or a circular opening. The arbitrary polygonal opening includes, but is not limited to, a triangular opening, a rectangular opening, a trapezoidal opening, a parallelogram opening, a pentagonal opening, or an N-gonal opening, where N is an integer greater than 5. The circular opening includes, but is not limited to, an arc opening of any angle, such as a 90° arc opening (quarter circle), a 180° arc opening (semicircle), or a 360° arc opening (full circle).

[0111] like Fig.16 or Fig.17As shown, according to some embodiments of the present application, optionally, the opening k1 may be a rectangular opening. In a direction perpendicular to the plane where the display panel is located, the rectangular opening includes a first side a1 and a second side a2 that are opposite to each other. The extension direction of the first side a1 and the second side a2 of the rectangular opening is perpendicular to the extension direction of the fan-out line 201. For example, the extension direction of the first side a1 and the second side a2 of the rectangular opening is a first direction X, the extension direction of the fan-out line 201 is a second direction Y, and the first direction X and the second direction Y may be perpendicular. It is easy to understand that in some other examples, the first side of the rectangular opening may also be Fig.15 or Fig.16 The second side of the rectangular opening can also be Fig.16 or Fig.17 At this time, the extension direction of the first side d1 and the second side d2 of the rectangular opening may be parallel to the extension direction of the fan-out line 201 .

[0112] In this way, when the shape of the first part b1 of the opening k1 is a rectangle, the extension direction of a pair of sides of the first part b1 is perpendicular to the extension direction of the fan-out line 201, and the extension direction of the other pair of sides is parallel to the extension direction of the fan-out line 201, which is beneficial to the adjustment of the overlapping area between the fan-out line 201 and the power signal line 202, and facilitates the implementation of the solution.

[0113] The following describes the film layer distribution of the fan-out lines and the power signal lines in conjunction with some embodiments of the present application.

[0114] like Fig.18 As shown, according to some embodiments of the present application, the display panel 20 may optionally include a stacked substrate 01, a first metal layer M1, a second metal layer MC and a third metal layer M2, and an insulating layer located between any adjacent metal layers. For example, in a direction perpendicular to the plane where the display panel 20 is located, a gate insulating layer GI is provided between the first metal layer M1 and the substrate 01, a capacitor insulating layer IMD is provided between the second metal layer MC and the first metal layer M1, and an interlayer dielectric layer ILD is provided between the third metal layer M2 and the second metal layer MC. Fig.18 In the illustrated embodiment, the fan-out line 201 may be located in the first metal layer M1 and the second metal layer MC, and the power signal line 202 may be located in the third metal layer M2. When the fan-out line 201 is located in the first metal layer M1 and the second metal layer MC, one of any two adjacent fan-out lines 201 may be located in the first metal layer M1, and the other fan-out line 201 may be located in the second metal layer MC. In this way, on the one hand, the fan-out lines 201 can be arranged more closely in the first direction X, saving wiring space; on the other hand, by setting any two adjacent fan-out lines 201 in different metal layers, the insulating layer between different layers can be used to shield the signal, thereby reducing the signal interference between adjacent fan-out lines 201.

[0115] Of course, in some other embodiments, the fan-out line 201 may be located only in the first metal layer M1. In some other embodiments, the fan-out line 201 may be located only in the second metal layer MC. When the fan-out line 201 is located in the second metal layer MC, since the second metal layer MC is usually a Ti / Al / Ti metal stack with low impedance, the resistance drop (IR-drop) on the fan-out line 201 can be reduced.

[0116] like Fig.19 As shown, according to other embodiments of the present application, optionally, Fig.18 The difference from the embodiment shown is that the display panel 20 may further include a fourth metal layer M3, which is located on the side of the third metal layer M2 away from the substrate 01. The power signal line 202 may be located on at least one of the third metal layer M2 and the fourth metal layer M3. Fig.19 In the illustrated embodiment, the power signal line 202 may be located in both the third metal layer M2 and the fourth metal layer M3. In a direction perpendicular to the plane where the display panel 20 is located, the power signal line 202 located in the third metal layer M2 may at least partially overlap with the power signal line 202 located in the fourth metal layer M3, and the power signal line 202 located in the third metal layer M2 may be electrically connected to the power signal line 202 located in the fourth metal layer M3 through a via (not shown in the figure).

[0117] It is easy to understand that when the display panel 20 includes the fourth metal layer M3 , the fan-out line 201 may be located in the first metal layer M1 and the second metal layer MC, or the fan-out line 201 may be located only in the first metal layer M1 or the second metal layer MC.

[0118] For ease of understanding, the above-mentioned film layers are introduced below in conjunction with a partial cross-sectional schematic diagram of a display area of ​​an OLED display panel.

[0119] like Fig. 20As shown, according to some embodiments of the present application, optionally, the display panel 20 may include a stacked substrate 01, a buffer layer 02, a first metal layer M1, a second metal layer MC and a third metal layer M2. An active layer b is provided between the first metal layer M1 and the buffer layer 02. An insulating layer is provided between any adjacent metal layers and between the active layer b and the first metal layer M1. Exemplarily, a gate insulating layer GI is provided between the first metal layer M1 and the active layer b, a capacitor insulating layer IMD is provided between the second metal layer MC and the first metal layer M1, and an interlayer dielectric layer ILD is provided between the third metal layer M2 and the second metal layer MC. In addition, the display panel 20 may further include a planarization layer PLN, a pixel definition layer PDL, and the light-emitting element may include a stacked anode RE, a light-emitting layer OM and a cathode SE. The display panel 20 may include a thin film transistor T and a storage capacitor. The active region of the thin film transistor T may be located in the active layer b, the gate of the thin film transistor T may be located in the first metal layer M1, and the source and / or drain of the thin film transistor T may be located in the third metal layer M2. The first electrode plate of the storage capacitor may be located on the first metal layer M1 , and the second electrode plate of the storage capacitor may be located on the second metal layer MC.

[0120] Fig.21 The capacitance impedance variation curves of the fan-out lines at different positions of the display panel are shown when the overlapping relationship between the fan-out lines and the openings on the power signal lines is not adjusted. Fig. 22 The capacitance impedance variation curves of the fan-out lines at different positions of the display panel after adjusting the overlapping relationship between the fan-out lines and the openings on the power signal lines are shown. Fig.21 and Fig. 22 The horizontal axis represents, for example, different positions in the display panel, and the vertical axis represents, for example, capacitance impedance. Fig.21 As shown, when the overlapping relationship between the fan-out lines and the openings on the power signal lines is not adjusted, in the direction perpendicular to the plane where the display panel is located, the overlapping area of ​​the fan-out lines and the power signal lines at different or adjacent positions suddenly changes, which in turn causes a sudden change in the capacitance impedance generated between the fan-out lines and the power signal lines at different or adjacent positions, causing the display panel to have a mura phenomenon, such as vertical stripes appearing in the display panel. Fig. 22 As shown, by comparison, by adjusting the overlapping relationship between the fan-out line and the opening on the power signal line, such as adjusting the position and / or size of the opening on the power signal line, or adjusting the routing method of the fan-out line, the overlapping area between the fan-out line and the power signal line in the adjacent multiple fan-out line groups is reduced successively, so that the capacitive impedance generated between the fan-out line and the power signal line in the adjacent multiple fan-out line groups is smoothly transitioned, avoiding sudden changes in the capacitive impedance generated between the fan-out line and the power signal line at different positions or adjacent positions, thereby improving or even eliminating the mura phenomenon of the display panel.

[0121] Based on the display panel 20 provided in the above embodiment, the present application also provides a display device, including the display panel provided in the present application. Fig.23 , Fig.23 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig.23 The provided display device 1000 includes the display panel 20 provided by any of the above embodiments of the present application. Fig.23 In the embodiment, a mobile phone is used as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the array substrate provided in the embodiment of the present application. For details, reference can be made to the specific description of the array substrate in the above embodiments, and this embodiment will not be repeated here.

[0122] It should be understood that the specific structure of the pixel circuit and the layout structure of the display panel provided in the drawings of the embodiments of the present application are only examples and are not intended to limit the present application. In addition, the above embodiments provided in the present application can be combined with each other if there is no contradiction.

[0123] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a fan-out line and a power signal line located in a non-display area, wherein the power signal line includes an opening overlapping at least a portion of the fan-out line; In a direction perpendicular to the plane where the display panel is located, the fan-out line overlapping the power signal line includes M fan-out line groups arranged in sequence along a first direction, each of the fan-out line groups includes at least one fan-out line, and M is a positive integer; Among the M fan-out line groups, the i-1th fan-out line group is located on the side of the i-th fan-out line group away from the display area, and the i+1th fan-out line group is located on the side of the i-th fan-out line group close to the display area; the i-1th fan-out line group includes a fan-out line group with a length of L i-1 The fan-out line of the i-th fan-out line group includes a length of L i The fan-out line of the i+1th fan-out line group includes a length of L i+1 The fan-out line, L i-1 >L i >L i+1 ; In the direction perpendicular to the plane where the display panel is located, the length is L i-1 The overlapping area of ​​the fan-out line and the power signal line is S i-1 , the length is L i The overlapping area of ​​the fan-out line and the power signal line is S i , the length is L i+1 The overlapping area of ​​the fan-out line and the power signal line is S i+1 , S i-1 ≥S i ≥S i+1 , where 2≤i≤M-1.

2. The display panel according to claim 1, characterized in that: In the M fan-out line groups, the lengths of the fan-out lines in the first fan-out line group to the Mth fan-out line group decrease in sequence; In a direction perpendicular to the plane where the display panel is located, the fan-out lines in the first fan-out line group to the Mth fan-out line group have the same overlapping area with the power signal line; Or, in a direction perpendicular to the plane where the display panel is located, the overlapping areas between the fan-out lines in the first fan-out line group to the Mth fan-out line group and the power signal lines gradually decrease.

3. The display panel according to claim 1, characterized in that: The power signal line includes Q openings, the Q openings extend along the first direction, and Q is a positive integer; In a direction perpendicular to the plane where the display panel is located, the fan-out lines in the M fan-out line groups all overlap with the Q openings; Along the direction from the (i+1)th fan-out line group to the (i-1)th fan-out line group, the width of the opening remains unchanged or gradually decreases.

4. The display panel according to claim 3, characterized in that: In a direction perpendicular to the plane where the display panel is located, the fan-out lines in the M fan-out line groups overlap with first parts of the Q openings; In a direction perpendicular to the plane where the display panel is located, the shape of the first part of the opening includes a first figure with a constant width or a second figure with a gradually decreasing width, the first figure includes a rectangle, a wave or a sawtooth shape, the second figure includes a trapezoid, a triangle or an arc, the width is the minimum distance of the opening along the second direction, and the second direction intersects with the first direction.

5. The display panel according to claim 1, characterized in that: The power signal line includes P openings, the P openings extend along the first direction, and the P openings are arranged in sequence along a second direction intersecting the first direction, and P is a positive integer; Along the second direction, the area or length of at least some of the P openings gradually decreases or gradually increases.

6. The display panel according to claim 5, characterized in that: Along the direction from the (i+1)th fan-out line group to the (i-1)th fan-out line group, the width of the opening remains unchanged or gradually decreases.

7. The display panel according to claim 6, characterized in that: In a direction perpendicular to the plane where the display panel is located, the shape of the first part of the opening includes a first figure with a constant width or a second figure with a gradually decreasing width, the first figure includes a rectangle, a wave or a sawtooth shape, and the second figure includes a trapezoid, a triangle or an arc.

8. The display panel according to claim 5, characterized in that: In a direction perpendicular to the plane where the display panel is located, the number of the openings overlapped by the fan-out lines in the 1st fan-out line group to the Mth fan-out line group gradually increases.

9. The display panel according to claim 3 or 6, characterized in that: The first portion of the opening is rectangular in shape, and in a direction perpendicular to the plane where the display panel is located, the first portion includes a first side and a second side opposite to each other, and an extension direction of the first side and the second side is perpendicular or parallel to an extension direction of the fan-out line.

10. The display panel according to claim 1, characterized in that: The power signal line includes a plurality of openings arranged in an array and having equal areas; In the M fan-out line groups, the numbers of the openings overlapped by the fan-out lines in the first fan-out line group to the Mth fan-out line group are the same or gradually increase.

11. The display panel according to claim 1, characterized in that: The power signal line includes a plurality of openings arranged in an array, the plurality of openings are arranged into N rows of openings along the first direction, and each row of openings includes at least one opening; Along a second direction intersecting the first direction, at least one of the openings in the j-th row of openings is interlaced with at least one of the openings in the j+1-th row of openings, 1<j≤N-1; In a direction perpendicular to the plane where the display panel is located, each of the M fan-out line groups overlaps with a row of the opening rows.

12. The display panel according to claim 11, characterized in that: Areas of the plurality of openings in the N rows of openings are equal.

13. The display panel according to claim 11, characterized in that: The Nth row of openings is located at a side of the 1st row of openings close to the display area, and the numbers of the openings in the 1st row of openings to the Nth row of openings are the same or increase sequentially.

14. The display panel according to claim 10 or 11, characterized in that: The opening includes any polygonal opening or a circular opening.

15. The display panel according to claim 10 or 11, characterized in that: The opening is a rectangular opening, and in a direction perpendicular to the plane where the display panel is located, the rectangular opening includes a first side and a second side opposite to each other, and the extension direction of the first side and the second side is perpendicular to the extension direction of the fan-out line, Alternatively, an extension direction of the first side and the second side is parallel to an extension direction of the fan-out line.

16. The display panel according to claim 1, characterized in that: The fan-out line includes a first sub-fan-out line extending along the first direction and a second sub-fan-out line extending along the second direction. In a direction perpendicular to the plane where the display panel is located, the first sub-fan-out line and / or the second sub-fan-out line overlaps with at least one of the openings.

17. The display panel according to claim 1, characterized in that: The display panel comprises a substrate, a first metal layer, a second metal layer and a third metal layer which are stacked, and an insulating layer located between any adjacent metal layers; The fan-out line is located in at least one of the first metal layer and the second metal layer, and the power signal line is located in the third metal layer.

18. The display panel according to claim 1, characterized in that: The display panel comprises a substrate, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are stacked, and an insulating layer located between any adjacent metal layers; The fan-out line is located in at least one of the first metal layer and the second metal layer, and the power signal line is located in at least one of the third metal layer and the fourth metal layer.

19. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1-18.

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