A packaging structure and a method for forming the same

Abstract

The present disclosure discloses a packaging structure, comprising: a logic chip; a plurality of core chips, wherein the plurality of core chips are stacked on the logic chip in sequence along a vertical direction; wherein the plurality of core chips include a first core chip and a second core chip interconnected by a hybrid bonding component, wherein the hybrid bonding component includes: a first contact pad located on the surface of the first core chip; a second contact pad located on the surface of the second core chip; the first contact pad and the second contact pad are bonded to each other. By adopting a hybrid bonding process technology between the plurality of core chips, hybrid bonding stacking is achieved, the number of micro-bumps of the packaging structure is reduced, the signal transmission speed of the packaging structure is increased, the thermal resistance of the packaging structure is reduced, and the integration of the packaging structure is increased.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a packaging structure and a method for forming the same. Background Art

[0002] As people's requirements for electronic products develop towards miniaturization and multifunctionality, packaging is also developing towards high density and high integration, and integrated circuit products are also developing from two-dimensional to three-dimensional. Three-dimensional packaging is a promising way to meet these requirements. It has the advantages of reducing packaging volume and increasing circuit reliability, thereby realizing the integration of a system or a function in a three-dimensional structure. Therefore, it is very meaningful to develop new packaging processes to package chips with different functions as a whole to reduce the total size of the chip package, which is also a technical problem that needs to be solved urgently.

[0003] However, the performance of the current packaging structure is still insufficient, and how to optimize the performance of the packaging structure is a technical problem that needs to be solved urgently at this stage. Summary of the invention

[0004] An embodiment of the present disclosure provides a packaging structure, including: a logic chip; a plurality of core chips, wherein the plurality of core chips are stacked in sequence on the logic chip along a vertical direction; wherein the plurality of core chips include a first core chip and a second core chip interconnected by a hybrid bonding component, wherein the hybrid bonding component includes: a first contact pad located on the surface of the first core chip; a second contact pad located on the surface of the second core chip; a first dielectric layer located on the periphery of the first contact pad and a second dielectric layer located on the periphery of the second contact pad; the first contact pad and the second contact pad are contact-bonded, and the first dielectric layer and the second dielectric layer are contact-bonded.

[0005] In some embodiments, the first contact pad is formed on the active surface of the first core chip, the second contact pad is formed on the active surface of the second core chip, and the active surface of the first core chip is bonded to the active surface of the second core chip; wherein the active surface is the side of the core chip where the device layer is formed.

[0006] In some embodiments, the first contact pad is formed on the active surface of the first core chip, the second contact pad is formed on the inactive surface of the second core chip, and the active surface of the first core chip is bonded to the inactive surface of the second core chip; wherein the active surface is the side of the core chip forming the device layer, and the inactive surface is the opposite side of the active surface.

[0007] In some embodiments, the logic chip and a core chip adjacent to the logic chip are interconnected via a first bonding component, and the first bonding component includes: a third contact pad located on the surface of the logic chip; and a fourth contact pad located on the surface of the core chip adjacent to the logic chip; wherein the third contact pad and the fourth contact pad are in contact and bonded to each other.

[0008] In some embodiments, the packaging structure also includes: a first through hole and a second through hole respectively located in the first dielectric layer and the second dielectric layer; the first contact pad and the second contact pad are respectively formed in the first through hole and the second through hole; wherein, there is a gap area between the side wall of the first contact pad and the side wall of the first through hole; and / or, there is a gap area between the side wall of the second contact pad and the side wall of the second through hole.

[0009] In some embodiments, the gap region is filled with an insulating material, and the Young's modulus of the insulating material is smaller than the Young's modulus of the first dielectric layer and the second dielectric layer.

[0010] In some embodiments, the packaging structure further includes: a packaging compound, wherein the packaging compound is located above the logic chip and covers the plurality of core chips.

[0011] In some embodiments, the Young's modulus of the first dielectric layer and the second dielectric layer is less than the Young's modulus of the potting compound.

[0012] In some embodiments, the first contact pad and the second contact pad are made of different materials.

[0013] A method for forming a packaging structure is also provided in an embodiment of the present disclosure, including: providing a logic chip, a first core chip, and a second core chip; respectively arranging a first contact pad and a second contact pad on the surfaces of the first core chip and the second core chip, as well as a first dielectric layer located outside the first contact pad and a second dielectric layer located outside the second contact pad; stacking the first core chip and the second core chip in sequence on the logic chip so that the first contact pad and the second contact pad are butted against each other; performing a bonding process so that the first contact pad and the second contact pad, and the first dielectric layer and the second dielectric layer are bonded to each other to form a hybrid bonding component.

[0014] In some embodiments, a first contact pad and a second contact pad are respectively arranged on the surface of the first core chip and the second core chip, as well as a first dielectric layer located outside the first contact pad and a second dielectric layer located outside the second contact pad, including: forming a first dielectric layer and a second dielectric layer on the first core chip and the second core chip, respectively; etching the first dielectric layer and the second dielectric layer to form a first through hole and a second through hole, respectively; forming a first contact pad and a second contact pad in the first through hole and the second through hole, respectively.

[0015] In some embodiments, a top surface of the first contact pad is higher than a surface of the first dielectric layer, and a top surface of the second contact pad is lower than a surface of the second dielectric layer.

[0016] In some embodiments, after forming the first contact pad and the second contact pad in the first through hole and the second through hole respectively, the method further includes: etching the first contact pad to form a gap region between the side wall of the first contact pad and the side wall of the first through hole; and / or etching the second contact pad to form a gap region between the side wall of the second contact pad and the side wall of the second through hole.

[0017] In some embodiments, after forming the gap region, the method further includes: depositing an insulating material, the insulating material filling the gap region, the Young's modulus of the insulating material being smaller than the Young's modulus of the first dielectric layer and the second dielectric layer.

[0018] In some embodiments, the bonding temperature of the bonding process is less than 200 degrees Celsius.

[0019] In some embodiments, the bonding process uses an alternating annealing process.

[0020] The present invention adopts hybrid bonding process technology between multiple core chips to achieve hybrid bonding stacking, reduce the number of micro-bumps in the packaging structure, increase the signal transmission speed of the packaging structure, reduce the thermal resistance of the packaging structure, and improve the integration of the packaging structure.

[0021] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1a is a cross-sectional schematic diagram of a packaging structure according to an embodiment of the present disclosure;

[0024] Figure 1b is a cross-sectional schematic diagram of a packaging structure of another embodiment of the present disclosure;

[0025] Figure 2a In one embodiment of the present disclosure Figure 1a An enlarged schematic diagram of the hybrid bonding part within the dotted box in FIG.

[0026] Figure 2b In another embodiment of the present disclosure Figure 1a An enlarged schematic diagram of the hybrid bonding part within the dotted box in FIG.

[0027] Figure 3a is a cross-sectional schematic diagram of a packaging structure of another embodiment of the present disclosure;

[0028] Figure 3b is a cross-sectional schematic diagram of a packaging structure of another embodiment of the present disclosure;

[0029] Figure 4a is a cross-sectional schematic diagram of a packaging structure of another embodiment of the present disclosure;

[0030] Figure 4b is a cross-sectional schematic diagram of a packaging structure of another embodiment of the present disclosure;

[0031] Figure 5 is a flow chart of a method for forming a packaging structure according to an embodiment of the present disclosure;

[0032] Figure 6a-6h The figure is a schematic diagram of the structure of a packaging structure in a formation process according to an embodiment of the present disclosure.

[0033] Reference numerals:

[0034] 110-logic chip; 120-core chip; 121-first core chip; 122-second core chip; 130-hybrid bonding part; 131-first contact pad; 131-1-top surface of the first contact pad; 132-second contact pad; 132-1-top surface of the second contact pad; 133-third contact pad; 134-fourth contact pad; 135-first dielectric layer; 135-1-surface of the first dielectric layer; 136-second dielectric layer; 136-1-surface of the second dielectric layer; 137-gap area; 137-1-first through hole; 137-2-second through hole; 138-insulating material; 140-packaging compound; 150-through hole; 160-copper pillar bump. DETAILED DESCRIPTION

[0035] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0036] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0037] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0038] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] Micro-bump technology is a process used in early three-dimensional stacking, mainly used in package stacking and low-density chip stacking. This technology uses the vertical direction of TSV, that is, the signal and power transmission between the active surface and the inactive surface of the chip. The signal is then transmitted to the next layer through the micro-metal bump to achieve three-dimensional interconnection between layers. In this technology, it is necessary to fill the gap between layers with filling materials. If micro-metal bumps are used to achieve three-dimensional stacking, the following problems may arise: the parasitic capacitance and inductance of the micro-metal bumps are large, which limits the signal propagation speed; since the thermal conductivity of the filling material is much lower than that of silicon, it limits the heat transfer from the inside of the chip to the outside, causing severe heat dissipation problems; the pitch of the micro-metal bump is usually greater than 30 microns, which is very easy to cause bridging, cold soldering and other problems after increasing the density, and cannot meet the requirements of high-density three-dimensional interconnection.

[0041] Based on this, the present disclosure provides a packaging structure, as shown in the attached Figure 1a and attached Figure 2a As shown, attached Figure 2a In one embodiment of the present disclosure, Figure 1aThe enlarged schematic diagram of the hybrid bonding part in the dotted box, the packaging structure includes: a logic chip 110; a plurality of core chips 120, the plurality of core chips 120 are stacked on the logic chip 110 in sequence along the vertical direction; wherein the plurality of core chips 120 include a first core chip 121 and a second core chip 122 interconnected by a hybrid bonding part 130, the hybrid bonding part 130 includes: a first contact pad 131 located on the surface of the first core chip; a second contact pad 132 located on the surface of the second core chip; a first dielectric layer 135 located on the periphery of the first contact pad and a second dielectric layer 136 located on the periphery of the second contact pad; the first contact pad 131 and the second contact pad 132 are contact-bonded, and the first dielectric layer 135 and the second dielectric layer 136 are contact-bonded. The vertically stacked core chips 120 can be interconnected through a plurality of through holes 150, for example, through silicon vias (TSV). The logic chip 110 and the core chip 120 adjacent to the logic chip can be interconnected through copper pillar bumps 160. The material of the first contact pad 131 or the second contact pad 132 includes, but is not limited to, an alloy formed by one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene or carbon nanotubes. The material of the first dielectric layer 135 or the second dielectric layer 136 includes, but is not limited to, silicon oxide, spin-on silicon glass, silicon nitride, silicon oxynitride, silicon carbonitride, aluminum oxide, amorphous silicon, silicon carbide or aluminum nitride. In a specific embodiment, the material of the first dielectric layer 135 or the second dielectric layer 136 is spin-on silicon glass, which has good filling ability and good compatibility with the core chip. In other embodiments, as shown in the attached Figure 1b As shown, the first core chip 121 or the second core chip 122 can be interconnected with other core chips 120 through copper pillar bumps 160 (Copper Pillar Bump).

[0042] The logic chip 110 may be one or more processors configured to communicate with a plurality of core chips 120 so as to access data from the core chips 120 and store data in the plurality of core chips 120. The logic chip 110 includes, but is not limited to, a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a central processing unit (CPU), or other known electronic circuits used as processors. The core chip includes a dynamic random access memory (DRAM) memory chip.

[0043] although Figure 1a-1b Only two and four core chips are shown, respectively, and any other number of core chips may be included in other embodiments, such as 8, 16, 32, and 64 core chips.

[0044] Traditionally, multiple core chips are generally interconnected by micro-bumps, which have high signal delay and large parasitic capacitance. Interconnected micro-metal bumps are prone to cold solder joints, resulting in short circuits, while adjacent micro-metal bumps are prone to bridging. Insulating materials need to be filled between adjacent micro-metal bumps, and insulating materials with low thermal conductivity will limit the heat dissipation of the packaging structure. The present invention adopts hybrid bonding process technology between multiple core chips to achieve hybrid bonding stacking, reduce the number of micro-bumps in the packaging structure, increase the signal transmission speed of the packaging structure, and reduce the thermal resistance of the packaging structure.

[0045] In some embodiments, the packaging structure further includes: a packaging compound 140, the packaging compound 140 is located above the logic chip 110 and covers the multiple core chips 120. The material of the packaging compound 140 can be, for example, epoxy resin, phenolic resin, polyimide, silica gel or spin-coated silicon glass, etc. The packaging compound can protect the packaging structure from external dust, moisture and mechanical impact, and improve the reliability of the packaging structure.

[0046] In some embodiments, as shown in the attached Figure 2a As shown, attached Figure 2a In one embodiment of the present disclosure, Figure 1a The enlarged schematic diagram of the hybrid bonding part in the dotted frame, the packaging structure also includes: a first through hole and a second through hole respectively located in the first dielectric layer 135 and the second dielectric layer 136; the first contact pad 131 and the second contact pad 132 are respectively formed in the first through hole and the second through hole; wherein, there is a gap area 137 between the side wall of the first contact pad and the side wall of the first through hole; and / or, there is a gap area 137 between the side wall of the second contact pad and the side wall of the second through hole. By designing the contact pads of the upper and lower core chips, a gap is reserved between the contact pad and the dielectric layer to reduce the strong binding of the dielectric layer on the contact pad, so that the first contact pad and the second contact pad have sufficient deformation space when bonding, reducing or avoiding bonding defects, preventing dielectric spacing delamination, and improving yield. At the same time, since sufficient deformation space is reserved in the lateral direction, a metal reserve margin of the contact pad can be set in the longitudinal direction. For example, the top surface of the contact pad is designed to be higher than the surface of the dielectric layer, so that the first contact pad is in full contact with the second contact pad, avoiding bonding defects (gaps or voids between metals) and achieving hybrid bonding under low temperature conditions. In some embodiments, the width of the top of the gap area 137 is greater than the width of the bottom of the gap area 137 (not shown in the figure), wherein the top of the gap area 137 refers to the end of the gap area 137 away from the core chip, and the bottom refers to the end of the gap area 137 close to the core chip. By setting the above different widths, bonding defects can be further reduced.

[0047] In some embodiments, the Young's modulus of the first dielectric layer 135 and the second dielectric layer 136 is smaller than the Young's modulus of the packaging compound 140. Exemplarily, the material of the first dielectric layer 135 or the second dielectric layer 136 may be spin-on silicon glass (SOG), which has a relatively small Young's modulus and relatively good ductility, thereby reducing packaging stress.

[0048] In some embodiments, as shown in the attached Figure 2b As shown, the gap region 137 is filled with an insulating material 138, and the Young's modulus of the insulating material 138 is smaller than that of the first dielectric layer 135 and the second dielectric layer 136. In actual operation, the insulating material may be an organic polymer, such as synthetic rubber, synthetic fiber, polyethylene, polyvinyl chloride, etc., or may be spin-coated silicon glass. Since the thermal conductivity of the gap region is poor and chip fatigue is easily caused, an insulating material with good ductility is provided in the gap region as a buffer layer, so that the contact pad is deformed after metal bonding and adheres to the insulating layer dielectric layer, which can reduce the gap and improve the bonding quality. In some embodiments, the insulating material 138 may include two parts, such as a lower insulating material and an upper insulating material, and the Young's modulus of the lower insulating material is smaller than that of the upper insulating material, wherein the lower insulating material is closer to the first core chip 121 or the second core chip 122 than the upper insulating material. By setting the Young's modulus of the lower insulating material to be smaller than that of the upper insulating material, the deformation caused by the metal bonding can be further buffered, the gap can be reduced, and the bonding quality can be improved.

[0049] In some embodiments, the first contact pad and the second contact pad are made of different materials. In conventional technology, the materials for metal bonding are often the same, but when the bonding temperature is low or there are depressions on the metal surface, the metal expansion of the contact pad is insufficient, resulting in gaps between the metals, which in turn leads to bonding defects. By setting contact pads of different materials and utilizing the difference in thermal expansion coefficients of different materials, the expansion degree of the contact pad during bonding can be flexibly and accurately controlled, thereby improving the controllability of the bonding process and reducing the formation of gaps.

[0050] In some embodiments, as shown in the attached Figure 1a and attached Figure 1bAs shown, the first contact pad 131 is formed on the active surface of the first core chip 121, and the second contact pad 132 is formed on the active surface of the second core chip 122, and the active surface of the first core chip 121 is bonded to the active surface of the second core chip 122; wherein the active surface is the side of the core chip 120 where the device layer (not shown in the figure) is formed. For ease of understanding, the arrow in the figure points from the non-active surface of the core chip 120 to the active surface of the core chip 120, and the non-active surface is the opposite side of the active surface. By bonding the active surfaces of multiple core chips to the active surfaces, the device layers of the core chips are close, the transmission path of the signals between the core chips is shortened, and the transmission speed can be increased. In actual operation, the first core chip 121 and the second core chip 122 can be hybrid bonded first, and then the hybrid-bonded core chip 120 can be bonded to the logic chip 110. In this process, the active surface of the first core chip 121 is bonded to the active surface of the second core chip 122 . Due to the symmetric structure, the stress distribution is more uniform, thereby improving the bonding quality.

[0051] In some embodiments, as shown in the attached Figure 3a and attached Figure 3b As shown, the first contact pad 131 is formed on the active surface of the first core chip 121, and the second contact pad 132 is formed on the inactive surface of the second core chip 122. The active surface of the first core chip 121 is bonded to the inactive surface of the second core chip 122; wherein the active surface is the side of the core chip 120 forming the device layer (not shown in the figure), and the inactive surface is the opposite side of the active surface. Under this packaging structure, the active surfaces of the core chip 120 are all facing one side. Compared with the method of bonding the active surfaces of multiple core chips to the active surfaces, this solution does not require additional flipping of the core chip, which simplifies the mounting process of the core chip.

[0052] In some embodiments, as shown in the attached Figure 4a and attached Figure 4b As shown, the adjacent core chips 120 are interconnected through the hybrid bonding element 130. Figure 1b and attached Figure 3b In the described scheme, the core chip after hybrid bonding is interconnected with the adjacent core chip through copper pillar bumps. Compared with micro-metal bumps, copper pillar bumps can improve integration and have advantages such as low resistance, but the bonding performance still cannot meet the needs of the application end. In this embodiment, adjacent core chips 120 are interconnected by hybrid bonding, which can further reduce the number of micro-metal bumps in the stacked structure and improve the signal transmission speed between the core chips in the stacked structure.

[0053] In some embodiments, as shown in the attached Figure 4a and attached Figure 4bAs shown, the logic chip 110 and the core chip 120 adjacent to the logic chip are interconnected through a first bonding component, and the first bonding component includes: a third contact pad 133 located on the surface of the logic chip; a fourth contact pad 134 located on the surface of the core chip adjacent to the logic chip; wherein the third contact pad 133 and the fourth contact pad 134 are in contact and bonded to each other. In some other embodiments, the first bonding component also includes: a third dielectric layer (not marked in the figure) located outside the third contact pad and a fourth dielectric layer (not marked in the figure) located outside the fourth contact pad; the third dielectric layer and the fourth dielectric layer are in contact and bonded. The core chip and the logic chip are interconnected through hybrid bonding, which further reduces the number of micro-bumps in the packaging structure, can improve the signal transmission speed between the core chip and the logic chip, and reduce the thermal resistance of the packaging structure.

[0054] The present disclosure also provides a method for forming a packaging structure. Figure 5 , the method comprising:

[0055] Step 501: providing a logic chip, a first core chip and a second core chip;

[0056] Step 502: Disposing a first contact pad and a second contact pad, and a first dielectric layer located around the first contact pad and a second dielectric layer located around the second contact pad on surfaces of the first core chip and the second core chip respectively;

[0057] Step 503: stacking the first core chip and the second core chip in sequence on the logic chip so that the first contact pad and the second contact pad are butted against each other;

[0058] Step 504: performing a bonding process so that the first contact pad and the second contact pad, and the first dielectric layer and the second dielectric layer are bonded to each other to form a hybrid bonding component.

[0059] The following is combined with Figure 6a-6h The method for forming the semiconductor structure provided in the embodiment of the present disclosure is described in detail.

[0060] First, as attached Figure 6a As shown, step 501 is performed to provide a logic chip 110, a first core chip 121, and a second core chip 122; the logic chip 110 includes but is not limited to a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a central processing unit (CPU), or other known electronic circuits used as processors. The first core chip 121 or the second core chip 122 includes a dynamic random access memory (DRAM) memory chip.

[0061] Next, as attached Figure 6b-6d As shown, step 502 is performed to respectively arrange a first contact pad 131 and a second contact pad 132, and a first dielectric layer 135 located at the periphery of the first contact pad and a second dielectric layer 136 located at the periphery of the second contact pad on the surfaces of the first core chip 121 and the second core chip 122. The material of the first contact pad 131 or the second contact pad 132 includes, but is not limited to, an alloy formed by one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene or carbon nanotubes.

[0062] Specifically, first of all, as shown in the attached Figure 6b , a first dielectric layer 135 and a second dielectric layer 136 are formed on the first core chip 121 and the second core chip 122, respectively. Here, the formation process of the first dielectric layer 135 and the second dielectric layer 136 includes but is not limited to a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process or a combination thereof. The material of the first dielectric layer 135 or the second dielectric layer 136 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, aluminum oxide, amorphous silicon, silicon carbide or aluminum nitride.

[0063] Next, as attached Figure 6c As shown, the first dielectric layer 135 and the second dielectric layer 136 are etched to form a first through hole 137-1 and a second through hole 137-2, respectively. Here, the size and shape of the through hole can be determined as needed. The etching process includes wet etching or dry etching, for example, high density plasma (HDP) etching or reactive ion etching (RIE).

[0064] Then, as attached Figure 6d As shown, a first contact pad 131 and a second contact pad 132 are formed in the first through hole 137-1 and the second through hole 137-2, respectively. The formation process of the first contact pad 131 and the second contact pad 132 may be, for example, physical vapor deposition (PVD) or chemical vapor deposition (CVD). In actual operation, a first contact pad material layer and a second contact pad material layer may be deposited on the first dielectric layer and the second dielectric layer, respectively, and the first contact pad material layer and the second contact pad material layer are planarized to form the first contact pad and the second contact pad, and the planarization process may be, for example, chemical mechanical polishing (CMP).

[0065] In one embodiment, the top surface 131-1 of the first contact pad is higher than the surface 135-1 of the first dielectric layer, and the top surface 132-1 of the second contact pad is lower than the surface 136-1 of the second dielectric layer. When performing the planarization process, due to the different polishing rates of the dielectric layer and the contact pad, the metal surface often causes depressions, and even local over-polishing is easily caused, resulting in serious dishing defects. At this time, when performing the bonding process, the dielectric layers first contact with each other, while the metals have not yet contacted each other due to the depressions or there are contact gaps. If the bonding temperature is not high enough, the insufficient expansion of the metal leads to the existence of gaps between the metals, which in turn leads to bonding defects. In this solution, the contact pads are designed so that the top surface of one of the contact pads is higher than the surface of the dielectric layer. The metal reserve margin of the contact pad can ensure that the contact pads are fully in contact during bonding, thereby improving the bonding quality. In actual operation, a first contact pad material layer may be deposited above the first dielectric layer, and the first contact pad material layer covering the surface of the first dielectric layer may be etched through a mask, and the contact pad material layer in the first through hole may be retained, so that the top surface 131-1 of the first contact pad is higher than the surface 135-1 of the first dielectric layer. In other embodiments, after performing a planarization process to form the first contact pad, the first dielectric layer may be etched, so that the top surface 131-1 of the first contact pad is higher than the surface 135-1 of the first dielectric layer. The formation method that the top surface 132-1 of the second contact pad is lower than the surface 136-1 of the second dielectric layer may be a butterfly defect caused by a planarization process, or may be formed by etching the second contact pad design.

[0066] In one embodiment, as shown in the attached Figure 6e As shown, after forming the first contact pad 131 and the second contact pad 132 in the first through hole 137-1 and the second through hole 137-2 respectively, the method further includes: etching the first contact pad so that a gap region 137 is formed between the sidewall of the first contact pad and the sidewall of the first through hole; and / or etching the second contact pad so that a gap region 137 is formed between the sidewall of the second contact pad and the sidewall of the second through hole. By reserving a gap between the contact pad and the dielectric layer to reduce the strong binding of the dielectric layer on the contact pad, the first contact pad and the second contact pad have sufficient deformation space when bonding, reducing or avoiding bonding defects, preventing dielectric spacing delamination, and improving yield. In other embodiments, a gap region may be formed between the first contact pad and the first dielectric layer by etching a portion of the first dielectric layer, and / or a gap region may be formed between the second contact pad and the second dielectric layer by etching a portion of the second dielectric layer.

[0067] In one embodiment, as shown in the attached Figure 6fAs shown, after the gap region 137 is formed, the method further includes: depositing an insulating material 138, the insulating material 138 is filled in the gap region 137, and the Young's modulus of the insulating material is less than that of the first dielectric layer 135 and the second dielectric layer 136. In actual operation, the insulating material can be an organic polymer, such as synthetic rubber, synthetic fiber, polyethylene, polyvinyl chloride, etc. Since the gap region has poor thermal conductivity and is prone to chip fatigue, an insulating material with good ductility is provided in the gap region as a buffer layer, so that the contact pad is deformed after metal bonding and adheres to the insulating layer and dielectric layer, which can reduce the gap and improve the bonding quality.

[0068] Next, as attached Figure 6g As shown, step 503 is performed to stack the first core chip 121 and the second core chip 122 in sequence on the logic chip 110, so that the first contact pad 131 and the second contact pad 132 are docked. It should be noted that the logic chip and the core chip adjacent to the logic chip can be interconnected through a copper pillar bump (Copper Pillar Bump) (not shown in the figure). In other embodiments, the logic chip and the core chip adjacent to the logic chip can be interconnected through a hybrid bonding part. Optionally, before docking the first contact pad 131 and the second contact pad 132, the first core chip 121 or the second core chip 122 can also be subjected to surface activation treatment, and the treatment method includes plasma surface treatment, ion or atomic surface treatment, etc., to remove surface particles and oxide layer to ensure the bonding interface performance.

[0069] Finally, as attached Figure 6h As shown, step 504 is executed to perform a bonding process, so that the first contact pad 131 and the second contact pad 132, the first dielectric layer 135 and the second dielectric layer 136 are bonded to each other to form a hybrid bonded component 130. The bonding temperature and pressure are determined according to the materials of the dielectric layer and the contact pad, and the corresponding pressure has a corresponding relationship with the required temperature, which is consistent with the conventional bonding temperature and pressure, and will not be described in detail here.

[0070] In some embodiments, the bonding temperature of the bonding process is less than 200 degrees Celsius. By designing the contact pads of the upper and lower core chips, the contact pads of one layer are higher than the dielectric layer, and the metal reserve margin of the contact pads can ensure that the contact pads are fully in contact during bonding, and there is no need to apply high temperature to expand the contact pad metal, so that bonding at low temperature can be achieved, so that the packaging structure has little thermal damage and the thermal budget is reduced.

[0071] In some embodiments, the bonding process uses an alternating annealing process. An alternating annealing process refers to an annealing method that alternates the annealing temperature back and forth, such as alternating annealing back and forth at two temperatures of 150 degrees Celsius and 180 degrees Celsius. Through alternating multiple annealing, multiple melting and bonding can reduce internal voids (gaps or voids between metals) and improve the internal uniformity of the hybrid bonded parts. In another embodiment, the alternating annealing process includes a first temperature and a second temperature, wherein the first temperature is less than 200 degrees Celsius and the second temperature is greater than 200 degrees Celsius. For example, the first temperature is 100°C, 125°C, 150°C or 175°C, and the second temperature is 225°C, 250°C, 275°C, 300°C, 400°C, 500°C or 600°C. Low temperature can reduce thermal damage to the packaging structure and reduce the thermal budget, but there may be insufficient expansion of the bonded contact pad metal and bonding defects. High temperature can make the contact pad fully contact during bonding, but it may cause thermal damage. By adopting a high and low temperature alternating annealing process, the bonding quality can be effectively improved while reducing thermal damage.

[0072] In summary, the present invention realizes hybrid bonding stacking by adopting hybrid bonding process technology between multiple core chips, reduces the number of micro-bumps in the packaging structure, improves the signal transmission speed of the packaging structure, reduces the thermal resistance of the packaging structure, and improves the integration of the packaging structure.

[0073] It should be noted that the packaging structure and the method of forming the same provided by the embodiments of the present disclosure can be applied to any integrated circuit including the structure, including but not limited to vertical integration of processed integrated circuits, and used for 3D SOC, micro-pad packaging, low-cost and high-efficiency replacement of flip-chip bonding, wafer-level packaging, thermal management, unique device structures (such as metal substrate devices). Applications further include but are not limited to integrated circuits (such as back-illuminated image sensors), RF front-ends, micro-electromechanical structures (MEMS) (including but not limited to pico-projectors and gyroscopes), 3D stacked memory (including but not limited to hybrid memory blocks), high-bandwidth memory, DIRAM, 2.5D (including but not limited to FPGA tilted on an insert), and products using these circuits (including but not limited to mobile phones and other mobile devices, laptops, servers).

[0074] The technical features in the technical solutions described in the embodiments can be combined arbitrarily without conflict. Those skilled in the art can change the order of the steps of the above-mentioned formation method without departing from the protection scope of the present disclosure. The steps in the embodiments of the present disclosure can be performed simultaneously or in sequence without conflict.

[0075] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A packaging structure, characterized in that: include: Logic chips; A plurality of core chips, wherein the plurality of core chips are stacked on the logic chip in sequence along a vertical direction; wherein the plurality of core chips include a first core chip and a second core chip interconnected by a hybrid bonding component, wherein the hybrid bonding component includes: a first contact pad located on a surface of the first core chip; a second contact pad located on the surface of the second core chip; a first dielectric layer located at the periphery of the first contact pad and a second dielectric layer located at the periphery of the second contact pad; The first contact pad and the second contact pad are in contact and bonding, and the first dielectric layer and the second dielectric layer are in contact and bonding; The packaging structure further includes: a packaging compound, the packaging compound being located above the logic chip and covering the plurality of core chips; The Young's modulus of the first dielectric layer and the second dielectric layer is smaller than the Young's modulus of the potting compound.

2. The packaging structure according to claim 1, characterized in that: The first contact pad is formed on the active surface of the first core chip, and the second contact pad is formed on the active surface of the second core chip. The active surface of the first core chip is bonded to the active surface of the second core chip; wherein the active surface is the side of the core chip where the device layer is formed.

3. The packaging structure according to claim 1, characterized in that: The first contact pad is formed on the active surface of the first core chip, and the second contact pad is formed on the inactive surface of the second core chip, and the active surface of the first core chip is bonded to the inactive surface of the second core chip; wherein the active surface is the side of the core chip forming the device layer, and the inactive surface is the opposite side of the active surface.

4. The packaging structure according to claim 1, characterized in that: The logic chip and the core chip adjacent to the logic chip are interconnected via a first bonding component, wherein the first bonding component comprises: a third contact pad located on the surface of the logic chip; a fourth contact pad located on the core chip surface adjacent to the logic chip; The third contact pad and the fourth contact pad are in contact and bonded with each other.

5. The packaging structure according to claim 1, characterized in that: Also includes: A first through hole and a second through hole are respectively located in the first dielectric layer and the second dielectric layer; the first contact pad and the second contact pad are respectively formed in the first through hole and the second through hole; wherein a gap area is provided between the side wall of the first contact pad and the side wall of the first through hole; and / or a gap area is provided between the side wall of the second contact pad and the side wall of the second through hole.

6. The packaging structure according to claim 5, characterized in that: The gap region is filled with an insulating material, and the Young's modulus of the insulating material is smaller than the Young's modulus of the first dielectric layer and the second dielectric layer.

7. The packaging structure according to claim 1, characterized in that: The first contact pad and the second contact pad are made of different materials.

8. A method for forming a packaging structure, characterized in that: include: Providing a logic chip, a first core chip, and a second core chip; A first contact pad and a second contact pad as well as a first dielectric layer located at the periphery of the first contact pad and a second dielectric layer located at the periphery of the second contact pad are respectively arranged on the surfaces of the first core chip and the second core chip; The first core chip and the second core chip are sequentially stacked on the logic chip so that the first contact pad and the second contact pad are butted against each other; Performing a bonding process so that the first contact pad and the second contact pad, and the first dielectric layer and the second dielectric layer are bonded to each other to form a hybrid bonding component; A packaging compound is formed over the logic chip to cover the first core chip and the second core chip, and Young's modulus of the first dielectric layer and the second dielectric layer is smaller than Young's modulus of the packaging compound.

9. The forming method according to claim 8, characterized in that: A first contact pad and a second contact pad are respectively arranged on the surfaces of the first core chip and the second core chip, and a first dielectric layer located outside the first contact pad and a second dielectric layer located outside the second contact pad are respectively arranged, comprising: forming a first dielectric layer and a second dielectric layer on the first core chip and the second core chip respectively; Etching the first dielectric layer and the second dielectric layer to form a first through hole and a second through hole respectively; A first contact pad and a second contact pad are formed in the first through hole and the second through hole, respectively.

10. The forming method according to claim 9, characterized in that: A top surface of the first contact pad is higher than a surface of the first dielectric layer, and a top surface of the second contact pad is lower than a surface of the second dielectric layer.

11. The forming method according to claim 9, characterized in that: After forming the first contact pad and the second contact pad in the first through hole and the second through hole respectively, the method further includes: etching the first contact pad so that a gap region is formed between a sidewall of the first contact pad and a sidewall of the first through hole; and / or, The second contact pad is etched so that a gap region is formed between a sidewall of the second contact pad and a sidewall of the second through hole.

12. The forming method according to claim 11, characterized in that: After forming the void region, the method further comprises: An insulating material is deposited, where the insulating material fills the gap region, and a Young's modulus of the insulating material is smaller than that of the first dielectric layer and the second dielectric layer.

13. The forming method according to claim 8, characterized in that: The bonding temperature of the bonding process is less than 200 degrees Celsius.

14. The forming method according to claim 8, characterized in that: The bonding process adopts an alternating annealing process.

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