Transistor device and method of forming the same

Abstract

The present disclosure relates to a transistor device and a method of forming a transistor device. A transistor device can be provided, which includes: a substrate; a buffer layer disposed on the substrate; a source terminal, a drain terminal, and a gate terminal disposed on the buffer layer; a barrier layer disposed on the buffer layer; and a passivation layer disposed on the barrier layer. The gate terminal can be disposed laterally between the source terminal and the drain terminal, the barrier layer can include a recess that is laterally located between the gate terminal and the drain terminal, a portion of the gate terminal can be disposed on the passivation layer, and the passivation layer can extend into the recess of the barrier layer.

Description

Technical Field

[0001] The present disclosure generally relates to transistor devices and methods of forming transistor devices. Background Art

[0002] Transistor devices, such as high electron mobility transistor (HEMT) devices, are often used in high-frequency or high-power applications, such as high-frequency telecommunications and high-voltage power switching applications. A typical HEMT device generally includes two materials having different bandgaps, which are arranged adjacent to each other to form a heterojunction therebetween. Due to the different conduction band energies of these materials, electrons diffuse from the wide-bandgap material to the narrow-bandgap material to form a conductive channel generally referred to as a two-dimensional electron gas (2DEG) channel.

[0003] Typically, an HEMT device also includes a source electrode, a drain electrode, and a gate electrode disposed between the source electrode and the drain electrode. In operation, the HEMT device can be turned on by applying an appropriate gate voltage. For example, for a power switching application, the HEMT device can be switched from a high-voltage off state to a high-current on state. During this switching, the HEMT device generally passes through a semi-on state, in which the drain bias is high (e.g., about 600 V) and current begins to flow through the 2DEG channel. In this state, a high electric field is formed at the corner of the gate of the HEMT device, which may cause electrons to accelerate through the 2DEG channel. These electrons (also referred to as "hot electrons") will be trapped in the materials forming the heterojunction. This results in hot carrier degradation, reduced reliability of the gate dielectric layer, reduced stability of the device threshold voltage (V th ) and reduced dynamic on-resistance (R on ).

[0004] Therefore, it is desirable to provide an improved transistor device having a reduced gate corner electric field and reduced hot electron generation and trapping. Summary of the Invention

[0005] According to various non-limiting embodiments, there is provided a transistor device including: a substrate; a buffer layer disposed on the substrate; a source terminal, a drain terminal, and a gate terminal disposed on the buffer layer, wherein the gate terminal can be laterally disposed between the source terminal and the drain terminal; a blocking layer disposed on the buffer layer, wherein the blocking layer can include a recess laterally located between the gate terminal and the drain terminal; and a passivation layer disposed on the blocking layer, wherein a portion of the gate terminal can be disposed on the passivation layer, and wherein the passivation layer can extend into the recess of the blocking layer.

[0006] According to various non - limiting embodiments, a method of forming a transistor device is provided. The method includes: providing a substrate; forming a buffer layer over the substrate; forming a source terminal, a drain terminal, and a blocking layer over the buffer layer, wherein the blocking layer may include a recess; forming a passivation layer over the blocking layer, wherein the passivation layer may extend into the recess of the blocking layer; and forming a gate terminal over the buffer layer, wherein the gate terminal may be laterally disposed between the source terminal and the drain terminal, wherein a portion of the gate terminal may be disposed over the passivation layer, and wherein the recess of the blocking layer may be laterally disposed between the gate terminal and the drain terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the drawings, like reference numerals generally refer to like parts throughout the different views. Additionally, the drawings are not necessarily to scale, but generally focus on illustrating the principles of the invention. Non - limiting embodiments of the invention will now be described only with reference to the following drawings, in which:

[0008] Figure 1 A simplified cross - sectional view of a transistor device according to various non - limiting embodiments is shown;

[0009] Figures 2A to 2D A simplified cross - sectional view of an example method of forming a Figure 1 transistor device according to various non - limiting embodiments is shown;

[0010] Figure 3 A simplified cross - sectional view of a transistor device according to alternative non - limiting embodiments is shown;

[0011] Figures 4A to 4D A simplified cross - sectional view of an example method of forming a Figure 3 transistor device according to various non - limiting embodiments is shown;

[0012] Figure 5 A simplified cross - sectional view of a transistor device according to alternative non - limiting embodiments is shown;

[0013] Figure 6 A simplified cross - sectional view of a transistor device according to alternative non - limiting embodiments is shown;

[0014] Figure 7 A simplified cross - sectional view of a Figure 1 transistor device in operation is shown;

[0015] Figures 8A to 8F Technical computer - aided design (TCAD) images are shown that illustrate the simulated electric field distributions within prior - art transistor devices and Figure 1 within the transistor device of the present invention;

[0016] Figures 9A to 9F show TCAD images that show the simulated concentration of hot carriers within prior art transistor devices and Figure 1 within the transistor device;

[0017] Figure 10A and Figure 10B respectively show Figure 1 the drain current - gate voltage curve and the drain current - drain voltage curve of the transistor device; and

[0018] Figure 11A and Figure 11B respectively show the drain current - gate voltage curve and the drain current - drain voltage curve of the prior art transistor device and Figure 1 the transistor device. DETAILED DESCRIPTION

[0019] Embodiments generally relate to transistor devices. More specifically, some embodiments relate to high electron mobility transistor (HEMT) devices. HEMT devices can be used in a variety of applications such as, but not limited to, high frequency telecommunications, high frequency computing, and high power switching applications (such as, but not limited to, power converters). In some non - limiting embodiments, the HEMT device can be used as a 200V or 650V enhancement mode HEMT device.

[0020] As used throughout this specification and the claims, approximating language may be applied to modify any quantitative representation that can permissibly vary without resulting in a change in the basic function associated with it. Thus, a value modified by terms such as "about," "approximately" or multiple terms is not limited to the precise value specified. In some cases, the approximating language can correspond to the precision of the instrument used to measure the value. Additionally, a direction is modified by one or more terms such as "substantially" meaning that the direction will be applied within the normal tolerances of the semiconductor industry. For example, "substantially parallel" means extending to a large extent in the same direction within the normal tolerances of the semiconductor industry, and "substantially perpendicular" means at an angle of 90 degrees plus or minus the normal tolerances of the semiconductor industry.

[0021] ​

[0022] The terms used herein are for the purpose of describing particular examples only and are not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprise" (and any form of comprise, such as "comprises" and "comprising"), "have" (and any form of have, such as "has" and "having"), "include" (and any form of include, such as "includes" and "including"), and "contain" (and any form of contain, such as "contains" and "containing") are open-ended linking verbs. Thus, a method or apparatus that "comprises", "has", "includes", or "contains" one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Similarly, a step of a method or an element of an apparatus that "comprises", "has", "includes", or "contains" one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Additionally, an apparatus or structure configured in a certain way is at least configured in this way, but may also be configured in ways not listed.

[0023] As used herein, when referring to two physical elements, the term "connected" means a direct connection between the two physical elements. However, the term "coupled" may mean a direct connection or a connection through one or more intermediate elements.

[0024] As used herein, the terms "may" and "may be" indicate the possibility of occurring within a set of circumstances; possessing a specified property, characteristic, or function; and / or qualifying another verb by expressing one or more of the ability, capacity, or possibility associated with the qualified verb. Thus, the use of "may" and "may be" indicates that the qualified term is clearly appropriate, capable, or suitable for the indicated ability, function, or use, taking into account that in some cases the qualified term may not be appropriate, capable, or suitable. For example, in some cases an event or ability may be expected, while in other cases the event or ability cannot occur - this distinction is captured by the terms "may" and "may be".

[0025] Figure 1A simplified cross-sectional view of a transistor device 100 in accordance with various non-limiting embodiments is shown. The transistor device 100 can be a high electron mobility transistor (HEMT) device. For example, the transistor device 100 can be a metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) device.

[0026] Referring Figure 1 , the transistor device 100 can include a substrate 102. The substrate 102 can be a semiconductor substrate. For example, the substrate 102 can include a semiconductor material such as, but not limited to, silicon (Si), sapphire, silicon carbide (SiC), poly-aluminum nitride (poly-AlN), or a combination thereof.

[0027] The transistor device 100 can further include a buffer layer 104 disposed over the substrate 102. The buffer layer 104 can be an epitaxial layer and can include a buffer material such as, but not limited to, gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or a combination thereof. The buffer layer 104 can have a first bandgap that ranges from about 3.4 eV (e.g., when the buffer layer 104 includes GaN) to about 6.2 eV (e.g., when the buffer layer 104 includes AlN). In a non-limiting embodiment, the buffer layer 104 can include GaN and the transistor device 100 can be a GaN MIS-HEMT device.

[0028] The transistor device 100 can further include a source terminal 106, a drain terminal 108, and a gate structure 150 disposed over the buffer layer 104. The gate structure can include a gate terminal 110 and a gate dielectric layer 112 disposed at least partially below the gate terminal 110. As Figure 1 shown, the gate terminal 110 can be disposed laterally between the source terminal 106 and the drain terminal 108. Each of the source terminal 106 and the drain terminal 108 can include an ohmic contact. Each ohmic contact can include a conductive material such as, but not limited to, titanium, titanium nitride, aluminum, or a combination thereof. The gate terminal 110 can also include a conductive material such as, but not limited to, polysilicon, titanium nitride, tantalum nitride, tungsten, aluminum, or a combination thereof. The gate dielectric layer 112 can include a dielectric material such as an oxide or a nitride material such as, but not limited to, aluminum oxide (Al2O3), silicon nitride (SiN), or a combination thereof.

[0029] The transistor device 100 may further include a barrier layer 114 disposed over the buffer layer 104. The barrier layer 114 may be an epitaxial layer and may include a barrier material such as, but not limited to, gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), or a combination thereof. The barrier layer 114 may have a second bandgap. In various non-limiting embodiments, the second bandgap of the barrier layer 114 may be between approximately 3.4 eV (e.g., when the barrier layer 114 includes GaN) and approximately 6.2 eV (e.g., when the barrier layer 114 includes AlN). The second bandgap of the barrier layer 114 may be different from (e.g., wider than) the first bandgap of the buffer layer 104. For example, the buffer layer 104 may include GaN (with a narrower bandgap), while the barrier layer 114 may include AlGaN (with a wider bandgap). In a non-limiting embodiment, a portion of the buffer layer 104 that is located below and in contact with the barrier layer 114 (e.g., a portion having a thickness of approximately 200 nm to approximately 1500 nm) may include GaN to allow the formation of a 2DEG conductive channel therein.

[0030] Reference Figure 1 , the barrier layer 114 may include a first barrier portion 114a, a second barrier portion 114b, and a gap 114G disposed laterally between the first barrier portion 114a and the second barrier portion 114b. The gate terminal 110 may be a recessed gate. In other words, the gate terminal 110 (along with the gate dielectric layer 112 therebelow) may partially extend into the gap 114G of the barrier layer 114. Specifically, the gate dielectric layer 112 may line the gap 114G of the barrier layer 114. Thus, the first barrier portion 114a of the barrier layer 114 may be disposed laterally between the source terminal 106 and the gate terminal 110, and the second barrier portion 114b of the barrier layer 114 may be disposed laterally between the drain terminal 108 and the gate terminal 110. As Figure 1 shown, the thickness of the first barrier portion 114a is substantially uniform; and a recess 114R may be disposed within the second barrier portion 114b. In other words, the barrier layer 114 may include a recess 114R that is laterally located between the gate terminal 110 and the drain terminal 108. The recess 114R may partially extend through the thickness of the barrier layer 114 such that a portion of the barrier layer 114 may be disposed below the recess 114R (specifically, vertically between the recess 114R and the buffer layer 104). Additionally, the recess 114R may contact the gate dielectric layer 112 and may extend laterally from the gate dielectric layer 112 in a direction toward the drain terminal 108. The length L of the recess 114R stepcan be between about 50 nm and about 600 nm (e.g., in some non-limiting embodiments, between about 100 nm and about 300 nm). The thickness T of the barrier layer 114 under the recess 114R barrier can be between about 3 nm and about 30 nm. The depth D of the recess 114R recess can be between about 5 nm and about 27 nm.

[0031] The transistor device 100 may further include a passivation layer 116 disposed over the barrier layer 114, the source terminal 106, and the drain terminal 108. The passivation layer 116 may be a dielectric layer including a dielectric material such as an oxide material or a nitride material. For example, the passivation layer 116 may include aluminum oxide (Al2O3), aluminum oxynitride (AlON), silicon dioxide (SiO2), silicon nitride (SiN x ) or a combination thereof.

[0032] Reference Figure 1 , the passivation layer 116 may include a first passivation segment 116a, a second passivation segment 116b, and a gap 116G disposed laterally between the first passivation segment 116a and the second passivation segment 116b. The first passivation segment 116a may be disposed over the source terminal 106 and the first barrier portion 114a; and the second passivation segment 116b may be disposed over the drain terminal 108 and the second barrier portion 114b. As Figure 1 shown, the passivation layer 116 (specifically, the second passivation segment 116b) may extend into the recess 114R of the barrier layer 114. Thus, a "step" may be formed within the passivation layer 116, and in some non-limiting embodiments, the passivation layer 116 may thus be referred to as a "stepped dielectric layer". The thickness T of the passivation layer 116 between the gate dielectric layer 112 over the recess 114R and the bottom surface of the recess 114R step can be between about 10 nm and about 500 nm.

[0033] The second passivation segment 116b may include a recess 116R over the recess 114R of the barrier layer 114, where the recess 116R may vertically overlap the recess 114R. As Figure 1 shown, the gate terminal 110 and the gate dielectric layer 112 may extend into both the gap 116G and the recess 116R of the passivation layer 116. Specifically, the gate dielectric layer 112 may line a portion of the recess 116R and a portion of the gap 116G. As Figure 1As shown, the sides of the gaps 114G, 116G facing the drain terminal 108 can be vertically aligned; while the sides of the gaps 114G, 116G facing the source terminal 106 can be laterally offset from each other. Specifically, the first blocking portion 114a can project laterally in the direction towards the gate terminal 110 beyond the first passivation segment 116a. However, depending on the manufacturing process, the gaps 114G, 116G can alternatively be vertically aligned along both sides.

[0034] As Figure 1 shown, the gate terminal 110 can be at least partially disposed above the passivation layer 116, where the gate dielectric layer 112 is disposed between the gate terminal 110 and the passivation layer 116. The gate terminal 110 can include a first portion 110a and a second portion 110b disposed above the passivation layer 116, where the first portion 110a can vertically overlap with the first blocking portion 114a of the blocking layer 114, and the second portion 110b can vertically overlap with the second blocking portion 114b of the blocking layer 114. Specifically, the second portion 110b of the gate terminal 110 can be disposed above (or in other words, vertically overlap with) the recess 114R of the blocking layer 114.

[0035] Figures 2A to 2D A simplified cross-sectional view showing a method of forming a transistor device 100 according to various non-limiting embodiments is illustrated. For clarity of illustration, some reference numerals have been omitted from Figures 2A to 2D it.

[0036] Referring Figure 2A thereto, the method can include providing a substrate 102 and forming a buffer layer 104 on the substrate 102. The method can further include forming a source terminal 106 and a drain terminal 108 on the buffer layer 104.

[0037] Referring Figures 2A to 2B thereto, the method can further include forming a blocking layer 114 on the buffer layer 104 and forming a passivation layer 116 on the blocking layer 114.

[0038] As Figure 2AAs shown, the method may include forming a barrier material layer 202 over the buffer layer 104 and forming a first trench 202T in the barrier material layer 202. The first trench 202T may extend partially through the thickness of the barrier material layer 202. Any method known to those skilled in the art may be used to form the first trench 202T. For example, the first trench 202T may be formed by etching the barrier material 202. The method may further include forming a passivation material layer 204 over the barrier material layer 202 and further over the source and drain terminals 106, 108. Due to the presence of the first trench 202T, the passivation material layer 204 may include a second trench 204T, where the second trench 204T may be narrower than the first trench 202T.

[0039] As Figure 2B shown, the method may further include forming a barrier layer 114 and a passivation layer 116 from the barrier material layer 202 and the passivation material layer 204, respectively. Specifically, the method may include removing a portion of the barrier material layer 202 and a portion of the passivation material layer 204 to form the barrier layer 114 and the passivation layer 116, respectively. Specifically, portions of the barrier material 202 and the passivation material 204 may be removed by etching or any other method known to those skilled in the art.

[0040] Referring Figure 2C to, the method may further include forming a gate dielectric layer 112 over the passivation layer 116. The gate dielectric layer 112 may be formed by depositing a dielectric material over the passivation layer 116 to line the surfaces of the passivation layer 116, the barrier layer 114, and the buffer layer 104.

[0041] Referring Figure 2D to, the method may further include forming a gate terminal 110 over the buffer layer 104. Any method known to those skilled in the art may be used to form the gate terminal 110. For example, the gate terminal 110 may be formed by depositing a conductive material over the gate dielectric layer 112 such that the conductive material may fill the gap 114G of the barrier layer 114, as well as the gap 116G and the recess 116R of the passivation layer 116. The conductive material may then be etched to form the gate terminal 110.

[0042] The above method sequence is for illustration only, and unless otherwise specifically stated, the method is not limited to the specific sequence described above.

[0043] Figure 3 A transistor device 300 is shown in accordance with an alternative non-limiting embodiment. The transistor device 300 may be similar to the transistor device 100, and thus, common features are labeled with the same reference numerals and need not be discussed.

[0044] Referring Figure 3, similar to transistor device 100, transistor device 300 may also include a blocking layer 114 having a recess 114R that is laterally located between the gate terminal 110 and the drain terminal 108. However, in transistor device 300, the recess 114R may extend completely through the thickness of the blocking layer 114. "Extend completely" means that the thickness T of the blocking layer 114 below the recess 114R barrier may be between about 0 nm and about 2 nm (due to possible manufacturing errors). In Figure 3 the illustrated non-limiting embodiment, the recess 114R may extend all the way to the buffer layer 104, and the thickness T of the blocking layer 114 below the recess 114R barrier may be about 0 nm (therefore, the thickness T barrier is not labeled in Figure 3 ). Additionally, transistor device 300 may further include another blocking layer 302 that is arranged to line the bottom surface of the recess 114R. As Figure 3 illustrated, the another blocking layer 302 may also line the side surfaces of the recess 114R and the top surfaces of the source terminal 106, the blocking layer 114, and the drain terminal 108. The another blocking layer 302 may be a thin layer. For example, the thickness T of the another blocking layer 302 fbarrier may be between about 0.5 nm and about 4 nm. The another blocking layer 302 may include a blocking material such as, but not limited to, aluminum nitride (AlN), aluminum oxynitride (AlON), or any other material having a fixed positive charge. Additionally, different from transistor device 100, the second passivation segment 116b of the passivation layer 116 may not include any recesses. Instead, the second passivation segment 116b may include a planar surface 116t (facing away from the blocking layer 114), where the planar surface 116t may partially vertically overlap with the recess 114R of the blocking layer 114. The thickness T of the passivation layer 116 between the gate dielectric layer 112 above the recess 114R and the bottom surface of the recess 114R step may be between about 10 nm and about 500 nm. The depth D of the recess 114R recess may be between about 5 nm and about 30 nm. The length L of the recess 114R recess may be similar to the length in device 100.

[0045] Figures 4A to 4D Shows a simplified cross-sectional view of an example method of manufacturing a transistor device 300 according to various non-limiting embodiments. For clarity of illustration, some reference numerals have been omitted from Figures 4A to 4D ).

[0046] Refer to Figure 4A, the method may include providing a substrate 102 and forming a buffer layer 104 over the substrate 102. The method may also include forming a source terminal 106 and a drain terminal 108 over the buffer layer 104.

[0047] Reference Figures 4A to 4B , the method may also include forming a barrier layer 114 over the buffer layer 104 and forming a passivation layer 116 over the barrier layer 114 in a manner similar to that described in the above reference Figures 2A to 2D . Specifically, as Figure 4A shown, a barrier material layer 202 may be formed over the buffer layer 104 and a first trench 202T may be formed within the barrier material layer 202. However, different from Figure 2A , the first trench 202T may extend completely through the thickness of the barrier material 202, and thus a barrier layer 114 including first and second barrier portions 114a, 114b may be formed. The method may also include forming a barrier material layer 402 over the barrier layer 114, the source terminal 106, and the drain terminal 108, and forming a passivation material layer 204 over the barrier material layer 402. The barrier material layer 402 may be formed using an atomic layer deposition (ALD) method or any other method known to those skilled in the art. Due to the presence of the first trench 202T, the passivation material layer 204 may include a second trench 204T that is narrower than the first trench 202T. As Figure 4B shown, the method may include forming another barrier layer 302 and a passivation layer 116 from the barrier material layer 402 and the passivation material layer 204, respectively. Specifically, the method may include removing a portion of the passivation material layer 204 and a portion of the barrier material layer 402 to form the passivation layer 116 and another barrier layer 302, respectively.

[0048] Reference Figure 4C and Figure 4D , the method may include forming a gate dielectric layer 112 over the passivation layer 116 and forming a gate terminal 110 over the buffer layer 104 in a manner similar to that described in reference Figure 2C and Figure 2D .

[0049] The above-described order of the method is for illustration only, and unless otherwise specifically stated, the method is not limited to the above-described specific order.

[0050] Figure 5 and Figure 6 show a transistor device 500 and a transistor device 600 according to alternative non-limiting embodiments, respectively. The transistor device 500 is similar to the transistor device 100, and the transistor device 600 is similar to the transistor device 300. Therefore, the common features are labeled with the same reference numerals and need not be discussed.

[0051] AsFigure 5 As shown, compared with the transistor device 100, the transistor device 500 may further include a metal layer 502 disposed on the passivation layer 116. Similarly, as Figure 6 shown, compared with the transistor device 300, the transistor device 600 may further include a metal layer 602 disposed on the passivation layer 116. Specifically, in each of the transistor devices 500, 600, the metal layers 502, 602 may be arranged to line the gate dielectric layer 112 (in other words, the metal layers 502, 602 may be disposed between the gate dielectric layer 112 and the gate terminal 110). Each metal layer 502, 602 together with the corresponding gate terminal 110 forms a dual-gate metal layer. For each of the metal layers 502, 602, at least a portion of the metal layers 502, 602 may vertically overlap with the recess 114R of the barrier layer 114. A portion of the metal layers 502, 602 that vertically overlaps with the recess 114R may extend over the passivation layer 116 and laterally extend beyond the recess 114R in the direction toward the drain region 108. The metal layer 502 of the device 500 may further extend into the recess 116R of the passivation layer 116, the gap 116G of the passivation layer 116, and the gap 114G of the barrier layer 114. Similarly, the metal layer 602 of the device 600 may further extend into the gap 116G of the passivation layer 116 and the gap 114G of the barrier layer 114. Each of the metal layers 502, 602 may have a low work function. For example, each of the metal layers 502, 602 may have a work function between approximately 4.2V and approximately 5.5V. In addition to the additional process of forming the metal layers 502, 602, the transistor devices 500, 600 may be fabricated in a manner similar to that of fabricating the transistor devices 100, 300 described above. For example, the metal layers 502, 602 may be formed by depositing a metal material on the gate dielectric layer 112 and etching the metal material. Then, the gate terminal 110 may be formed by depositing a conductive material on the gate dielectric layer 112 and the metal layers 502, 602 and etching the conductive material.

[0052] Figure 7 FIG. shows the transistor device 100 in operation. The transistor device 100 may be a normally-off transistor device operating in enhancement mode. Specifically, as Figure 7 shown, due to the spontaneous and piezoelectric polarization effects of the barrier material layer 114 and the buffer material layer 104, a 2DEG channel 702 may be formed near the interface between the barrier layer 114 and the buffer layer 104. However, since there is no barrier material in the gap 114G, a portion of the 2DEG channel 702 under the gate structure 150 may be depleted. In use, a positive gate voltage may be applied to the gate structure 150 such that the gate-drain bias may be greater than the threshold voltage V of the device 100 thUsing this positive gate voltage, a part of the 2DEG channel 702 can be formed under the gate structure 150, and current can flow through the 2DEG channel 702, thereby turning on the transistor device 100. To turn off the transistor device 100, a gate voltage lower than the threshold voltage can be applied. For example, the gate voltage can be 0V or a negative voltage.

[0053] By including the recess 114R in the blocking layer 114 of the transistor device 100, the thickness of the dielectric material (including the gate dielectric material and the passivation material) between the gate terminal 110 and the blocking layer 114 can be greater. When the transistor device 100 is in a semi-conducting state, this helps to reduce the electric field at the drain-side gate edge 150e of the gate structure 150. This in turn helps to suppress gate degradation and hot carrier generation in the transistor device 100. Therefore, the stability of the device 100 can be enhanced, and the threshold voltage V of the device 100 can be increased. th and the reliability of the gate edge 150e. In addition, the dynamic on-resistance R can also be enhanced. on performance, because the hot carriers trapped in the blocking material and the buffer material in the blocking layer 114 and the buffer layer 104 are reduced. In addition, since the gate degradation of the device 100 (caused by the high electric field at the drain-side gate edge 150e) can be suppressed, the off-state breakdown voltage (BV) can be increased. Therefore, the overall reliability of the transistor device 100 can be improved. The length L of the recess 114R can be changed step to adjust the electric field at the drain-side gate edge 150e of the gate structure 150 and the threshold voltage V of the transistor device 100. th The thickness T of the blocking layer 114 under the recess 114R in the transistor device 100 can be changed. barrier to adjust the carrier / electron density under the recess 114R (and thus adjust the threshold voltage V th to form a part of the 2DEG channel under the recess 114R).

[0054] The transistor devices 300, 500, 600 can operate in a manner similar to the above-described transistor device 100, except for the following: For the transistor devices 300 and 600, due to the presence of fixed positive charges in another blocking layer 302 (because there is no blocking material under the recess 114R in the blocking layer 114), a part of the 2DEG channel 702 can be formed under the recess 114R. The fixed positive charges can introduce electron carriers near the interface between another blocking layer 302 and the buffer layer 104. The thickness T of another blocking layer 302 that lines the bottom surface of the recess 114R in the transistor devices 300 / 600 can be changed. fbarrier to adjust the carrier / electron density under the recess 114R (and thus adjust the threshold voltage V). th(to form a part of the 2DEG channel below the recess 114R). As described above, each of the transistor devices 500, 600 may include a metal layer 502, 602 with a low work function located above the passivation layer 116. By changing the work function of the metal layer 502 / 602, the carrier density (and thus the threshold voltage V) below the second blocking portion 114b in the transistor devices 500 / 600 can be changed th (to form a part of the 2DEG channel 702 below the second blocking portion 114b).

[0055] Figures 8A to 8F Show technical computer-aided design (TCAD) images that show the simulated electric field distributions within the transistor device 100 and the prior art transistor device in a semi-conducting state, with a drain bias of 100V, a varying thickness T of the passivation layer 116 step and a varying length L of the recess 114R step . The prior art transistor device may be similar to the transistor device 100 but without the recess 114R (in other words, the second blocking portion 114b has a substantially uniform thickness). In Figures 8A to 8F , the intensity of each pixel indicates the electric field strength at the point in the prior art device or the transistor device 100 corresponding to the pixel in the image. Specifically, the higher the pixel intensity, the greater the electric field strength. For clarity of illustration, Figures 8A to 8E some reference numerals are omitted in

[0056] Specifically, Figures 8A to 8B respectively show the electric field distributions 802, 804 around the drain-side gate edge 150e in the transistor device 100 when the thickness T step is 80nm and 40nm respectively. Figure 8C Shows the electric field distribution 806 around the drain-side gate edge 150e in the prior art device. As Figures 8A to 8C shown, compared with the prior art transistor device, by including the recess 114R and the passivation layer 116 extending into the recess 114R, the electric field at the drain-side gate edge 150e can be reduced. As Figures 8A to 8C shown, when the thickness T step is 40nm, the electric field uniformity at the drain-side gate edge 150e is the highest.

[0057] Figures 8D to 8F respectively show the electric field distributions 808, 810, 812 around the drain-side gate edge 150e in the transistor device 100 when the length L of the recess 114R step is 100nm, 300nm and 500nm respectively. As Figures 8D to 8F shown, at the length L stepWhen it is between 100 nm and 300 nm, a sufficiently uniform electric field can be achieved around the drain-side gate edge 150e.

[0058] Figures 9A to 9F TCAD images are shown that illustrate the simulated concentrations of hot carriers (or impact ionization carriers) in a prior art transistor device (similar to the transistor device described above with reference to Figure 8C the transistor device) and in the transistor device 100 in a semi-conducting state, with a drain bias of approximately 100 V, a source current of approximately 10 mA / mm, and a varying thickness T of the passivation layer 116 step and a varying length L of the recess 114R step . In Figures 9A to 9F , the intensity of each pixel indicates the hot carrier concentration at the point in the prior art device or the transistor device 100 corresponding to the pixel in the image. Specifically, the higher the pixel intensity, the greater the hot carrier concentration. For clarity of illustration, Figures 9A to 9F some reference numerals are omitted in

[0059] Specifically, Figures 9A to 9B show respectively the hot carrier concentrations around the drain-side gate edge 150e in the transistor device 100 when the thickness T step is 80 nm and 40 nm respectively. Figure 9C shows the hot carrier concentration around the drain-side gate edge 150e in the prior art device. As Figures 9A to 9C shown, compared with the prior art transistor device, by including the recess 114R and the passivation layer 116 extending into the recess 114R, the hot carrier concentration at the drain-side gate edge 150e can be reduced.

[0060] Figures 9D to 9F show respectively the hot carrier concentrations around the drain-side gate edge 150e in the transistor device 100 when the length L of the recess 114R step is 100 nm, 300 nm, and 500 nm respectively. As Figures 9D to 9F shown, when the length L of the recess 114R step increases, the hot carrier concentration around the drain-side gate edge 150e will decrease.

[0061] Figure 10A and Figure 10B show respectively the drain current-gate voltage (ID-VG) curves 1002, 1004, 1006 (where the drain voltage VD = 1 V) and the drain current-drain voltage (ID-VD) curves 1008, 1010, 1012 (where the gate voltage VG = 7 V) for the transistor device 100 when the thickness T of the passivation layer 116 step is 40 nm. Specifically, inFigure 10A In it, the curves 1002, 1004, 1006 show the ID-VG relationships when the length L step is 100 nm, 300 nm, and 500 nm respectively; while in Figure 10B the curves 1008, 1010, 1012 show the ID-VD relationships when the length L step is 100 nm, 300 nm, and 500 nm respectively. As shown in Figure 10A and Figure 10B the on-resistance R on increases with the increase of L step . This may be because a part of the channel 702 under the recess 114R has lower conductivity than a part of the channel 702 under the non-recessed part of the blocking layer 114. Therefore, the larger L step is (in other words, the longer a part of the channel 702 under the recess 114R is), the higher the on-resistance R on is.

[0062] Figure 11A and Figure 11B show the drain current-gate voltage (ID-VG) curves 1102, 1104, 1106 (where the drain voltage (VD) = 1 V) and the drain current-drain voltage (ID-VD) curves 1108, 1110, 1112 (where the gate voltage VG = 7 V) for the prior art device (similar to the device described above with reference to Figure 8C ) and the transistor device 100 when the length L step of the recess 114R is 100 nm. Specifically, in Figure 11A the curve 1102 shows the ID-VG relationship of the prior art transistor device, and the curves 1104, 1106 show the ID-VG relationships of the transistor device 100 when the thickness T step of the passivation layer 116 is 40 nm and 80 nm respectively. Similarly, in Figure 11B the curve 1108 shows the ID-VG relationship of the prior art device, and the curves 1110, 1112 show the ID-VG relationships of the transistor device 100 when the thickness T step is 40 nm and 80 nm respectively. As shown in Figure 11A and Figure 11B the curves 1104, 1106 basically overlap with each other, and the curves 1110, 1112 basically overlap with each other. In other words, when the thickness T step is 40 nm and when the thickness T step is 80 nm, the on-resistance R on of the transistor device 100 is approximately the same. However, if the thickness T step is further increased, the on-resistance Ron May increase because of the larger T step May result in weaker gate control and fewer carriers in the channel 702 under the blocking layer 114.

[0063] The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the foregoing embodiments are illustrative in all respects and not restrictive of the invention described herein. Thus, the scope of the invention is indicated by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.

Claims

1. A transistor device, comprising: A substrate; A buffer layer disposed on the substrate; A source terminal, a drain terminal, and a gate terminal disposed on the buffer layer; Wherein the gate terminal is disposed laterally between the source terminal and the drain terminal, and wherein the source terminal and the drain terminal are directly disposed on the buffer layer; A barrier layer disposed on the buffer layer; wherein the barrier layer includes a recess laterally located between the gate terminal and the drain terminal, and wherein the barrier layer is laterally disposed between the source terminal and the drain terminal; And A passivation layer disposed on the barrier layer, wherein a portion of the gate terminal is disposed on the passivation layer; And Wherein the passivation layer extends into the recess of the barrier layer, and the passivation layer vertically and horizontally overlaps the barrier layer, Wherein, the barrier layer includes: A first barrier portion; A second barrier portion; and A gap laterally disposed between the first barrier portion and the second barrier portion, Wherein, a portion of the gate terminal extends into the gap of the barrier layer, such that the first barrier portion is laterally disposed between the source terminal and the portion of the gate terminal, and the second barrier portion is laterally disposed between the drain terminal and the portion of the gate terminal, and Wherein, the recess is disposed within the second barrier portion and is laterally adjacent to the portion of the gate terminal, and another portion of the gate terminal is disposed above the recess to overlap the recess.

2. The transistor device according to claim 1, wherein, The portion of the gate terminal is disposed above the recess of the barrier layer.

3. The transistor device according to claim 1, wherein, The recess partially extends through the thickness of the barrier layer.

4. The transistor device according to claim 1, wherein, The recess completely extends through the thickness of the barrier layer.

5. The transistor device according to claim 4, further comprising another barrier layer disposed to line the bottom surface of the recess.

6. The transistor device according to claim 1 further comprises: A metal layer disposed on the passivation layer; Wherein at least a portion of the metal layer vertically overlaps the recess of the barrier layer.

7. The transistor device according to claim 1, wherein The thickness of the first barrier portion is substantially uniform.

8. The transistor device according to claim 1 further comprises: A gate dielectric layer disposed at least partially under the gate terminal, wherein the gate dielectric layer lines the gap of the barrier layer.

9. The transistor device according to claim 8, wherein, The recess of the barrier layer laterally extends from the gate dielectric layer in a direction toward the drain terminal.

10. The transistor device according to claim 8 further comprises: A metal layer disposed between the gate dielectric layer and the gate terminal.

11. The transistor device according to claim 10, wherein, At least a portion of the metal layer vertically overlaps the recess of the barrier layer.

12. The transistor device according to claim 11, wherein, The metal layer further extends into the gap of the barrier layer.

13. The transistor device according to claim 1, wherein, The passivation layer includes a first passivation segment disposed on the first barrier portion, a second passivation segment disposed on the second barrier portion, and a gap laterally disposed between the first passivation segment and the second passivation segment.

14. The transistor device according to claim 13, wherein, The first barrier portion laterally protrudes beyond the first passivation segment in a direction toward the gate terminal.

15. The transistor device according to claim 13, wherein, The second passivation segment includes a recess that vertically overlaps the recess of the barrier layer.

16. The transistor device according to claim 13, wherein, The second passivation section includes a planar surface that is away from the barrier layer and partially vertically overlaps the recess of the barrier layer.

17. The transistor device according to claim 1, wherein, The transistor device is a high electron mobility transistor device.

18. The transistor device according to claim 1, wherein The second barrier portion includes a first end and a second end opposite the first end, the recess is disposed at the first end of the second barrier portion, the first end of the second barrier portion is disposed adjacent to the portion of the gate terminal, and the second end of the second barrier portion is disposed adjacent to the drain terminal.

19. A method of forming a transistor device, the method comprising: Providing a substrate; Forming a buffer layer over the substrate; Forming a source terminal, a drain terminal, and a barrier layer directly over the buffer layer, wherein the barrier layer includes a recess, and wherein the barrier layer is disposed laterally between the source terminal and the drain terminal; Forming a passivation layer over the barrier layer, wherein the passivation layer extends into the recess of the barrier layer, and the passivation layer vertically and horizontally overlaps the barrier layer; And Forming a gate terminal over the buffer layer, wherein the gate terminal is disposed laterally between the source terminal and the drain terminal, a portion of the gate terminal is disposed over the passivation layer, and the recess of the barrier layer is disposed laterally between the gate terminal and the drain terminal, wherein the barrier layer includes: A first barrier portion; A second barrier portion; and A gap disposed laterally between the first barrier portion and the second barrier portion, wherein a portion of the gate terminal extends into the gap of the barrier layer such that the first barrier portion is disposed laterally between the source terminal and the portion of the gate terminal, and the second barrier portion is disposed laterally between the drain terminal and the portion of the gate terminal, and wherein the recess is disposed within the second barrier portion and is disposed laterally adjacent to the portion of the gate terminal, and another portion of the gate terminal is disposed over the recess to overlap the recess.

20. The method according to claim 19, wherein, Forming the barrier layer over the buffer layer and forming the passivation layer over the barrier layer includes: Forming a barrier material layer over the buffer layer; Forming a first trench in the barrier material layer; Forming a passivation material layer over the barrier material layer, wherein the passivation material layer includes a second trench that is narrower than the first trench; and Forming the barrier layer and the passivation layer from the barrier material layer and the passivation material layer, respectively.

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