A dynamic aging device and method for a non-transparent bridge PCIe switching circuit

Abstract

The application discloses a kind of non-transparent bridge PCIe exchange circuit dynamic burn-in device and method, adopt root complex CPU, endpoint device, port mode configuration line, port interconnection bus and device state indication line, cover the physical layer of circuit, data link layer and transaction layer and non-transparent bridge address conversion and exchange function, so that circuit is carried out dynamic burn-in according to normal working frequency and bus interface rate during burn-in;The application does not need to be externally connected root complex CPU and numerous PCIe endpoint devices for each non-transparent bridge PCIe exchange circuit, and only one root complex CPU is needed on the whole burn-in board, the connection mode of root complex CPU greatly saves the cost of components on burn-in board;The application improves the density of burn-in device on the same area burn-in board because of the reduction of peripheral PCIe device, more circuits can be burn-in in the same burn-in high-temperature box, and test cost is saved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design and testing, specifically relating to a dynamic aging device and method for non-transparent (NT) bridge PCIe switching circuits. Background Technology

[0002] High-reliability, high-quality integrated circuits undergo aging tests during production to screen out or eliminate barely acceptable devices, ensuring the reliability of the circuits leaving the factory. Without aging tests, these defective devices will experience early fatal failures or premature lifespan failures during use. Additionally, some component users also conduct dynamic aging tests on purchased circuits to verify the quality of the batch. Dynamic aging tests require applying appropriate excitation and output load to the test circuit, making the circuit as close as possible to actual application, aging it at the actual operating frequency and interface speed.

[0003] In a PCIe system, PCIe switching circuits are used to interconnect multiple electronic components or modules. Non-transparent bridge PCIe switching circuits can connect two or more PCIe host systems, enabling applications such as system isolation and failover. A non-transparent bridge connects two independent host or intelligent I / O domains; the resources and addresses on one side are invisible to the CPU on the other side. The CPU on one side independently configures and controls its subsystems, and the address spaces of the two systems are completely independent. The non-transparent bridge uses an internal address translation mechanism to translate the addresses between the two sides.

[0004] Non-transparent bridge PCIe switching circuits typically have two or more PCIe ports. The number of ports and link width are configurable. Any one of the ports can be configured as an upstream port (USP) of the transparent bridge to connect to the root complex (RC). At least one of the ports can be configured as an NT port to connect to the RC of another system. The remaining ports are used as downstream ports (DSPs) to connect to endpoint devices. Two downstream ports of the same circuit or different circuits cannot be connected for communication. Figure 1 This is a schematic diagram of a typical application of a 5-port non-transparent bridge PCIe switching circuit with one transparent bridge port. Figure 1In this setup, the primary host CPU connects to the upstream port, the secondary host CPU connects to the NT port, and the remaining ports connect to endpoint devices. Due to the stringent electrical requirements and complex functions of PCIe, existing aging chambers cannot provide sufficient aging stimulus signals for PCIe switching circuits. To dynamically age domestically produced N-port non-transparent bridge PCIe switching circuits at their actual operating frequency and interface speed during the production process, several CPUs containing root complexes are provided, connected to the upstream and NT ports respectively, and several endpoint devices are provided, connected to the remaining downstream ports to provide aging stimulus and output load, according to typical application requirements. However, in mass production, aging M circuits requires N×M peripheral PCIe devices, including CPUs, as stimulus and load, resulting in high component costs and significantly reducing the density of PCIe switching circuits on the board, leading to high or even unacceptable testing costs. Summary of the Invention

[0005] The purpose of this invention is to provide a dynamic aging device and method for non-transparent bridge PCIe switching circuits to overcome the shortcomings of the prior art.

[0006] A dynamic aging device for a non-transparent bridge PCIe switching circuit includes a root complex CPU, endpoint devices, port mode configuration lines, port interconnect bus, and device status indicator lines.

[0007] The root complex CPU is connected to the upstream port of the first switching circuit in the series switching circuit. One downstream port of the first switching circuit is connected to the upstream port of its adjacent switching circuit. Another downstream port of the first switching circuit is connected to the non-transparent bridge port of its adjacent switching circuit. The non-transparent bridge port of the first switching circuit is connected to one downstream port of the tail switching circuit. The other downstream port of the tail switching circuit is connected to the endpoint device.

[0008] Multiple switching circuits are connected in series between the first switching circuit and the tail switching circuit. The upstream port of the current switching circuit is connected to one downstream port of the previous switching circuit connected in series, and the non-transparent bridge port of the current switching circuit is connected to another downstream port of the previous switching circuit connected in series.

[0009] The port mode configuration line connects to each switching circuit; the device status indicator line connects to the root complex CPU.

[0010] Furthermore, the port mode configuration line is used to configure the port mode of each switching circuit, and a PCIe link is established between any two device ports connected by the interconnect bus.

[0011] Furthermore, the root complex CPU is used to configure the relevant configuration registers in the non-transparent bridge PCIe switching circuit of the switching circuit, as well as the relevant configuration registers of the endpoint device. After configuration, a PCIe mature transaction transmission path without transaction address translation is formed between the root complex CPU, the switching circuit, and the endpoint device.

[0012] Furthermore, the root complex CPU is used to send refined transactions to the first switching circuit according to a preset transaction sending frequency and transaction, and to enable the refined transactions to pass through multiple serially connected switching circuits and endpoint devices.

[0013] Furthermore, the root complex CPU periodically and sequentially reads the fault registers of each port of all PCIe switching circuits via the PCIe link, and determines whether the circuit is working properly based on the value of the fault report bit in the fault register.

[0014] Furthermore, the root complex CPU is used to output the abnormal state of the aging switching circuit to the device status indicator line in a preset signal form and to indicate the number of the abnormal circuit through signal encoding.

[0015] Furthermore, the endpoint device is connected to the tail switch circuit via a port interconnect bus, serving as the load and energizer of a downstream port of the tail switch circuit.

[0016] Furthermore, the root complex CPU and endpoint devices employ application-specific integrated circuits (ASICs) or FPGA circuits.

[0017] A dynamic aging method for a non-transparent bridge PCIe switching circuit of a dynamic aging device includes the following steps:

[0018] S1, Power on all devices on the aging board and reset the root complex CPU device, the aging switching circuit and the endpoint device according to the maximum reset time required by the root complex CPU device, the aging switching circuit and the endpoint device.

[0019] S2, after power-on reset is canceled, the port mode configuration line will fix each PCIe switching circuit on the old board to the working mode of one upstream port, at least one downstream port and at least one non-transparent bridge port;

[0020] S3, completes the training and establishment of links based on each PCIe link on the port interconnect bus of multiple serially connected switching circuits of the root complex CPU device;

[0021] S4. After the training and establishment of each link are completed, the root complex CPU device configures the primary bus number, secondary bus number and subordinate bus number, memory base point register and memory limit register of each transparent bridge port of each PCIe switching circuit on the old board through the PCIe link.

[0022] S5, the root complex CPU device configures the BAR register and address translation register of the non-transparent bridge port of each PCIe switching circuit through the PCIe link. After configuration, it sends aging transactions sequentially through the series-connected switching circuits and endpoint devices to query the fault report registers inside all switching circuits and endpoint devices. Based on the query results, it determines whether the switching circuit is working properly. If the switching circuit is working properly and the aging time has not ended, aging continues until the required aging time is completed, and then power is cut off to end the aging process. If a switching circuit malfunctions, the root complex CPU continuously outputs the number of the malfunctioning switching circuit to the device status indicator line through a pin in a preset signal format and stops the periodic transmission of transactions. It outputs a device malfunction indicator signal and then cuts off the power to end the aging process.

[0023] Furthermore, when the root complex CPU and the endpoint devices are implemented by the same FPGA, the endpoint devices' reception and detection status of aging transactions are directly reported to the root complex CPU via internal signals within the FPGA.

[0024] Compared with the prior art, the present invention has the following beneficial technical effects:

[0025] This invention discloses a dynamic curing device for non-transparent bridge PCIe switching circuits. It employs a root complex CPU, endpoint devices, port mode configuration lines, port interconnect buses, and device status indicator lines, covering the physical layer, data link layer, and transaction layer of the circuit, as well as the address translation and switching functions of the non-transparent bridge. This allows the circuit to be dynamically cured at its normal operating frequency and bus interface speed during curing. This invention eliminates the need for external root complex CPUs and numerous PCIe endpoint devices for each non-transparent bridge PCIe switching circuit, requiring only one root complex CPU on the entire curing board. This connection method significantly reduces the cost of components on the curing board. Furthermore, the reduction in external PCIe devices increases the density of curing devices on the same curing board area, allowing more circuits to be cured in the same high-temperature curing chamber, thus saving on testing costs.

[0026] Each PCIe device in this invention is interconnected only with the nearest PCIe device, which physically enables short-distance, highly reliable transmission of the PCIe bus, reducing the difficulty of PCIe routing design on older PCBs.

[0027] By adopting the connection method of the root complex CPU, the old refining station of M N-port circuits can save N×M (e.g., 12×100=1200)-2 peripheral PCIe devices, simplifying the overall equipment structure and reducing costs. Attached Figure Description

[0028] Figure 1This is a schematic diagram of a typical application of an existing non-transparent bridge PCIe switching circuit.

[0029] Figure 2 This is a diagram illustrating the working mode configuration of the 48-channel non-transparent bridge PCIe switching circuit ports according to an embodiment of the present invention.

[0030] Figure 3 This is a schematic diagram of the dynamic aging device for a 48-channel non-transparent bridge PCIe switching circuit according to an embodiment of the present invention.

[0031] Figure 4 This is a block diagram of the root complex CPU implemented by FPGA in an embodiment of the present invention.

[0032] Figure 5 This is the output encoding of the device status indicator line in this embodiment of the invention after a fault in the switching circuit SW3. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] like Figure 3 As shown, the present invention provides a dynamic aging device for a non-transparent bridge PCIe switching circuit, comprising a root complex CPU, endpoint devices, port mode configuration lines, port interconnect buses, and device status indicator lines.

[0036] Specifically, the root complex CPU is connected to the upstream port of the first switching circuit; one downstream port of the first switching circuit is connected to the upstream port of the second switching circuit; another downstream port of the first switching circuit is connected to the non-transparent bridge port of the second switching circuit; the non-transparent bridge port of the first switching circuit is connected to one downstream port of the tail switching circuit; another downstream port of the tail switching circuit is connected to the endpoint device; multiple switching circuits are connected in series between the first switching circuit and the tail switching circuit; the upstream port of the current switching circuit is connected to one downstream port of the previous switching circuit connected in series; the non-transparent bridge port of the current switching circuit is connected to another downstream port of the previous switching circuit connected in series; multiple switching circuits are connected in series sequentially; port mode configuration lines are connected to each switching circuit; and device status indicator lines are connected to the root complex CPU.

[0037] The port mode configuration line is used to configure the port mode of each switching circuit, so that a designated port of the switching circuit is used as an upstream port, another designated port is used as a downstream port, and other ports are used as non-transparent bridge ports. Through the configuration of the port mode configuration line, a PCIe link can be successfully established between any two device ports connected by the interconnect bus.

[0038] The root complex CPU is used to configure the relevant configuration registers in the non-transparent bridge PCIe switching circuit of the switching circuit, and to configure the relevant configuration registers of the endpoint device. After configuration, a PCIe refined transaction transmission path that does not require transaction address translation is formed between the root complex CPU, the switching circuit, and the endpoint device. A PCIe refined transaction transmission path that requires multiple address translations is formed between the root complex CPU, the first switching circuit, the second switching circuit, ... up to the tail switching circuit, and then back to the first switching circuit.

[0039] The root complex CPU is used to send refined transactions to the first switching circuit according to a preset transaction sending frequency and transaction, and to make the refined transactions pass through the first switching circuit, the second switching circuit, ... until the tail switching circuit and the endpoint device.

[0040] The root complex CPU periodically and sequentially reads the fault registers of each port of all PCIe switching circuits via the PCIe link, and determines whether the circuit is working properly based on the value of the fault report bit in the fault register.

[0041] The root complex CPU is used to output the abnormal state of the aging switching circuit to the device status indicator line in a preset signal form and to indicate the number of the abnormal circuit through signal encoding.

[0042] The endpoint device is connected to the tail switching circuit via a port interconnect bus, serving as the load and excitation of a downstream port of the tail switching circuit.

[0043] The root complex CPU and endpoint devices are implemented using application-specific integrated circuits (ASICs) or FPGAs. They can be a single circuit or FPGA, or a single circuit or FPGA that simultaneously has the functions of both a root complex CPU and an endpoint device.

[0044] When the endpoint device is implemented using FPGA, the configuration of the port device by the root complex CPU is eliminated by using the method of internal logic to fix the bus number and BAR related configuration register values.

[0045] When the root complex CPU and endpoint devices are implemented by the same FPGA, the endpoint devices' reception and detection status of aging transactions are directly reported to the root complex CPU via internal signals within the FPGA.

[0046] The port interconnect bus, according to the electrical characteristics specified in the PCIe protocol, connects the root complex CPU and the upstream port of the first switching circuit, the downstream port of the first switching circuit and the upstream port of the second switching circuit, the downstream port of the first switching circuit and the non-transparent bridge port of the second switching circuit, the non-transparent bridge port of the first switching circuit and the downstream port of the tail switching circuit; it also connects the downstream port of the tail switching circuit and the endpoint device; the port interconnect bus connects the upstream ports, downstream ports and non-transparent bridge ports of other switching circuits.

[0047] This invention relates to a dynamic aging method for the non-transparent bridge PCIe switching circuit of the above system, specifically including the following steps:

[0048] S1, Power on all devices on the aging board and reset the root complex CPU device, the aging switching circuit and the endpoint device according to the maximum reset time required by the root complex CPU device, the aging switching circuit and the endpoint device.

[0049] S2, after power-on reset is canceled, the port mode configuration line will fix each PCIe switching circuit on the old board to the working mode of one upstream port, at least one downstream port and at least one non-transparent bridge port;

[0050] S3, subsequently, each PCIe link on the port interconnect bus between the root complex CPU device and the first switching circuit, between the first and second switching circuits and the tail switching circuit, between the tail switching circuit and the endpoint device, and between other switching circuits automatically completes the link training and establishment.

[0051] S4. After the training and establishment of each link are completed, the root complex CPU device configures the primary bus number, secondary bus number, subordinate bus number, memory base point register, and memory limit register of each transparent bridge port of each PCIe switching circuit on the old board through the PCIe link.

[0052] S5, the root complex CPU device configures the BAR register and address translation register of the non-transparent bridge port of each PCIe switching circuit through the PCIe link, so that the non-transparent bridge port of the PCIe switching circuit can send the received upstream port transaction to the peer switching circuit after internal address translation, and the downstream port of the peer switching circuit can route it to its non-transparent bridge port within its switching circuit; the non-transparent bridge port of the peer can then send this transaction to its peer switching circuit downstream port after address translation again; and so on, until the downstream port of the first switching circuit can receive the peer NT transaction and discard it;

[0053] S6, the root complex CPU sends aging transaction 1, which is routed through the upstream port of the first aging switching circuit to a downstream port of it, then routed to the upstream port of the second aging switching circuit and output from a downstream port of it; and so on, the aging transaction 1 is routed to the tail switching circuit and routed by the tail switching circuit to the endpoint device of its downstream port.

[0054] S7, the root complex CPU sends old transaction 2. This transaction is routed to its NT port via the upstream port of the first old switching circuit, then switched by the NT port of the first switching circuit to the downstream port of the tail switching circuit and routed to its NT port by the tail switching circuit; then switched by the NT port of the tail switching circuit to the switching circuit at the other end and routed to its NT port; and so on, the old transaction 2 is routed to the first switching circuit again; after receiving the old transaction 2 from the NT port at the other end after a series of forwarding and address translations, the first switching circuit does not perform routing, but simply discards it;

[0055] S8. Repeat steps (6) and (7) according to the preset number of cycles. The root complex CPU queries the fault report registers inside all switching circuits and endpoint devices in the order of first switching circuit, second switching circuit, tail switching circuit, and endpoint device. Based on the query results, determine whether the switching circuit is working properly. If the switching circuit is working properly and the aging time has not ended, go to step (6) to continue aging until the required aging time is completed and then power off to end the aging. If a certain switching circuit is malfunctioning, go to step (9).

[0056] S9, the root complex CPU continuously outputs the number of the abnormal switching circuit to the device status indicator line through the pin in a preset signal form and stops the periodic transmission of transactions.

[0057] S10, after the test monitoring personnel observe the device abnormality indication signal output by the device status indicator line, they cut off the power to end the aging process.

[0058] The example demonstrates the port configuration and operating mode configuration results for a non-transparent bridge PCIe switching circuit with 48 channels. Figure 2 As shown.

[0059] like Figure 2 As shown, the port mode configuration line of the dynamic aging device in this embodiment configures the 48-channel PCIe switching circuit into 4 ports, where port 0 is an NT port with 16 PCIe channels, port 1 is a downstream port with 16 PCIe channels, port 2 is a downstream port with 8 PCIe channels, and port 3 is an upstream port with 8 PCIe channels.

[0060] See Figure 3 As shown, the dynamic aging device in this embodiment includes a port mode configuration line, an FPGA circuit, a device status indicator line, and a port interconnect bus; wherein, the FPGA implements a root complex CPU and a PCIe endpoint device.

[0061] The root complex CPU is connected to the upstream port of the first switching circuit SW1 via an x8 PCIe link. The downstream port 2 of the first switching circuit SW1 and the upstream port 3 of the second switching circuit SW2 are connected via x8 PCIe links. The downstream port 2 of the second switching circuit SW2 and the upstream port 3 of the third switching circuit SW3 are connected via x8 PCIe links. The downstream port 2 of the third switching circuit SW3 and the upstream port 3 of the fourth switching circuit SW4 are connected via x8 PCIe links. The downstream port 2 of the fourth switching circuit SW4 and the upstream port 3 of the fifth switching circuit SW5 are connected via x8 PCIe links. The downstream port 2 of the fifth switching circuit SW5 and the upstream port 3 of the tail switching circuit SW6 are connected via x8 PCIe links. The downstream port 2 of the tail switching circuit SW6 is connected to the endpoint device.

[0062] In this embodiment, the downstream port 1 of the first switching circuit SW1 is connected to the non-transparent bridge port of the second switching circuit SW2. The downstream port 1 of the second switching circuit SW2 is connected to the non-transparent bridge port of the third switching circuit SW3. The downstream port 1 of the third switching circuit SW3 is connected to the non-transparent bridge port of the fourth switching circuit SW4. The downstream port 1 of the fourth switching circuit SW4 is connected to the non-transparent bridge port of the fifth switching circuit SW5. The downstream port 1 of the fifth switching circuit SW5 is connected to the non-transparent bridge port of the tail switching circuit SW6. The downstream port 1 of the tail switching circuit SW6 is connected to the non-transparent bridge port of the first switching circuit SW1.

[0063] The root complex CPU in the FPGA includes a physical layer module (PHY), an RC controller, and a configuration and detection module. The configuration and detection module of the root complex CPU can configure the primary bus number, secondary bus number, subordinate bus number, memory base point register, memory limit register, NT port BAR register, NT port address translation register, and other relevant registers of each port of the six switching circuits in the order of the first switching circuit SW1, the second switching circuit SW2, the third switching circuit SW3, the fourth switching circuit SW4, the fifth switching circuit SW5, and the tail switching circuit SW6 through the RC controller and the PHY module and their respective PCIe links.

[0064] See Figure 4 The endpoint device in the FPGA consists of a physical layer module (PHY), an endpoint controller, and a receiving module. The endpoint device in the FPGA can be configured by the root complex CPU through the PCIe bus. For further improvement, in this embodiment, the endpoint device in the FPGA omits the configuration by the root complex CPU by using a logic-fixed bus number of 13 and a logic-fixed BAR register specifying a BAR address range of 0x100000 to 0x1FFFFF.

[0065] The configuration and detection module in the root complex CPU controls the RC controller and physical layer module PHY in the root complex CPU to send a memory write refining transaction MWr1, which is aimed at the endpoint device, to the first switching circuit at a period of 2ms. The MWr1 refining transaction passes through the first switching circuit, the second switching circuit and finally to the tail switching circuit, and finally reaches the endpoint device.

[0066] Following the MWR1 transaction, the configuration and detection module in the root complex CPU immediately sends a memory write processing transaction MWR2, targeting the NT port, to the first switching circuit via the RC controller and physical layer module PHY in the root complex CPU. The MWR2 processing transaction is address-translated by the NT port of SW1 and then switched to the downstream port 1 of the tail switching circuit SW6. The switching circuit SW6 routes the processing transaction MWR2 received at port 1 to the NT port and, after address translation at the NT port, switches it to the peer device switching circuit SW5. The switching circuit SW5 routes the processing transaction MWR2 received at port 1 to the NT port and, after address translation at the NT port, switches it to the peer device switching circuit SW4. Similarly, this continues until the NT port of the switching circuit SW2 switches the processing transaction MWR2 to port 1 of the switching circuit SW1.

[0067] In this embodiment, there is only one device status indicator line, which is connected to the root complex CPU in the FPGA. After each 65536 sets of MWR1 and MWR2 aging transactions are completed, the root complex CPU sequentially reads the Uncorrectable Error Status (address 0xFB8h) of each port of the PCIe switching circuit via the PCIe link. It determines whether the circuit is functioning correctly based on whether the fault report bits such as Data Link Protocol Error Status, Poisoned TLP Status, Malformed TLP Status, and ECRC Error Status are set. When no abnormality occurs in the aging switching circuit, the root complex CPU drives the device status indicator signal to a high level. When a circuit malfunctions, it outputs 1 to 6 consecutive low pulse signals through the FPGA pins to the device status indicator line; the number of low pulses in the consecutive low pulses represents the number of the malfunctioning circuit. Figure 5 The fault report register of the switching circuit SW3 indicates the signal waveform of the device status indicator line after a fault.

[0068] In this embodiment, the root complex CPU configures the primary bus number of port 3, upstream of switching circuit SW1, as 1, the secondary bus number as 2, the subordinate bus number as 19, and the address range specified by the memory base point and limit register as 0x100000~0xDFFFFF; configures the primary bus number of port 2, downstream of switching circuit SW1, as 2, the secondary bus number as 3, the subordinate bus number as 18, and the address range specified by the memory base point and limit register as 0x100000~0xBFFFFF; configures the primary bus number of port 1, downstream of switching circuit SW1, as 2, the secondary bus number as 19, the subordinate bus number as 19, and the address range specified by the memory base point and limit register as 0xC00000~0xCFFFFF; and specifies the address range of the BAR register of port 0 of the old NT port as 0xD00000~0xDFFFFF, and the address range specified by the address translation register as 0x200000.

[0069] In this embodiment, the root complex CPU configures the primary bus number of port 3, upstream of switching circuit SW2, as 3, the secondary bus number as 4, the subordinate bus number as 18, and the address range specified by the memory base point and limit register as 0x100000~0xBFFFFF; configures the primary bus number of port 2, downstream of switching circuit SW2, as 4, the secondary bus number as 5, the subordinate bus number as 17, and the address range specified by the memory base point and limit register as 0x100000~0x9FFFFF; configures the primary bus number of port 1, downstream of switching circuit SW2, as 4, the secondary bus number as 18, the subordinate bus number as 18, and the address range specified by the memory base point and limit register as 0xA00000~0xAFFFFF; and specifies the address range of BAR register of port 0 of the old NT port as 0xB00000~0xBFFFFF, and the address range specified by the address translation register as 0xC00000.

[0070] In this embodiment, the root complex CPU configures the primary bus number of port 3, upstream of switching circuit SW3, as 5, the secondary bus number as 6, the subordinate bus number as 17, and the address range specified by the memory base point and limit register as 0x100000~0x9FFFFF; configures the primary bus number of port 2, downstream of switching circuit SW3, as 6, the secondary bus number as 7, the subordinate bus number as 16, and the address range specified by the memory base point and limit register as 0x100000~0x7FFFFF; configures the primary bus number of port 1, downstream of switching circuit SW3, as 6, the secondary bus number as 17, the subordinate bus number as 17, and the address range specified by the memory base point and limit register as 0x800000~0x8FFFFF; and specifies the address range of the BAR register of port 0 of the old NT port as 0x900000~0x9FFFFF, and the address range specified by the address translation register as 0xA00000.

[0071] In this embodiment, the root complex CPU configures the primary bus number of port 3, upstream of switching circuit SW4, as 7, the secondary bus number as 8, the subordinate bus number as 16, and the address range specified by the memory base point and limit register as 0x100000~0x7FFFFF; configures the primary bus number of port 2, downstream of switching circuit SW4, as 8, the secondary bus number as 9, the subordinate bus number as 15, and the address range specified by the memory base point and limit register as 0x100000~0x5FFFFF; configures the primary bus number of port 1, downstream of switching circuit SW4, as 8, the secondary bus number as 16, the subordinate bus number as 16, and the address range specified by the memory base point and limit register as 0x600000~0x6FFFFF; and specifies the address range of the BAR register of port 0 of the old NT port as 0x700000~0x7FFFFF, and the address range specified by the address translation register as 0x800000.

[0072] In this embodiment, the root complex CPU configures the primary bus number of port 3, upstream of switching circuit SW5, as 9, the secondary bus number as 10, the subordinate bus number as 15, and the address range specified by the memory base point and limit register as 0x100000~0x5FFFFF; configures the primary bus number of port 2, downstream of switching circuit SW5, as 10, the secondary bus number as 11, the subordinate bus number as 14, and the address range specified by the memory base point and limit register as 0x100000~0x3FFFFF; configures the primary bus number of port 1, downstream of switching circuit SW5, as 10, the secondary bus number as 15, the subordinate bus number as 15, and the address range specified by the memory base point and limit register as 0x400000~0x4FFFFF; and specifies the address range of the BAR register of port 0 of the old NT port as 0x500000~0x5FFFFF, and the address range specified by the address translation register as 0x600000.

[0073] In this embodiment, the root complex CPU configures the primary bus number of port 3, upstream of the switching circuit SW6, to 11, the secondary bus number to 12, the subordinate bus number to 14, and the address range specified by the memory base point and limit register to be 0x100000~0x3FFFFF; configures the primary bus number of port 2, downstream of the switching circuit, to 12, the secondary bus number to 13, the subordinate bus number to 13, and the address range specified by the memory base point and limit register to be 0x100000~0x1FFFFF; configures the primary bus number of port 1, downstream of the switching circuit, to 12, the secondary bus number to 14, the subordinate bus number to 14, and the address range specified by the memory base point and limit register to be 0x200000~0x2FFFFF; and specifies the address range of the BAR register of port 0 of the old NT port to be 0x300000~0x3FFFFF, and the address range specified by the address translation register to be 0x400000.

[0074] The dynamic aging method for the non-transparent bridge PCIe switching circuit in this embodiment of the invention is as follows:

[0075] (1) Power on all components on the old refining board and / or provide power supply from the old refining machine to provide a 300ms power-on reset, resetting the root complex CPU device, endpoint devices and various switching circuits.

[0076] (2) After power-on reset is canceled, the port mode configuration line configures each 48-channel non-transparent bridge PCIe switching circuit as two x16 ports and two x8 ports. x16 port 0 is used as the NT upstream port, x16 port 1 is used as the downstream port, x8 port 2 is used as the downstream port, and x8 port 3 is used as the upstream port.

[0077] (3) Then as Figure 3 As shown, each PCIe link on the port interconnect bus between the root complex CPU device and the first switching circuit SW1, between the first switching circuit SW1 and the second switching circuit SW2 and the tail switching circuit SW6, between the tail switching circuit SW6 and the endpoint device, and between other switching circuits automatically completes link training and establishment with the maximum link width.

[0078] (4) After the training and establishment of each link are completed (wait 120ms after reset), the root complex CPU device configures the primary bus number, secondary bus number, subordinate bus number, memory base point register, and memory limit register of the transparent bridge ports (port 1, port 2, and port 3) of each PCIe switching circuit on the old board through the PCIe link; for example, the primary bus number of port 3 of switching circuit SW1 is configured as 1, the secondary bus number as 2, the subordinate bus number as 19, and the address range specified by the memory base point and limit registers is 0. x100000~0xDFFFFF; Port 2's primary bus number is configured as 2, secondary bus number as 3, subordinate bus number as 18, and the address range specified by the memory base point and limit register is 0x100000~0xBFFFFF; Port 1's primary bus number is configured as 2, secondary bus number as 19, subordinate bus number as 19, and the address range specified by the memory base point and limit register is 0xC000000~0xCFFFFF; The specific configurations of the various non-transparent bridge ports of other switching circuits are not detailed here;

[0079] (5) The root complex CPU device configures the BAR register and address translation register of port 0 of the non-transparent bridge port of each PCIe switching circuit through the PCIe link, so that port 0 of the PCIe switching circuit can send the received transaction from port 3 to the peer switching circuit after internal address translation, and the downstream port of the peer switching circuit can route it to its non-transparent bridge port 0 within its switching circuit; the non-transparent bridge port 0 of the peer can then send this transaction to its downstream port of the peer switching circuit after address translation again; and so on, until the downstream port 1 of the first switching circuit SW1 can receive the peer NT transaction and discard it; for example, the address range specified by the BAR register of port 0 of switching circuit SW1 is 0xD00000~0xDFFFFF, and the address range specified by the address translation register is 0x200000, so memory access transactions with addresses within the BAR range can be routed after address translation according to the configuration of the address translation register; the specific configuration of the BAR register and address translation register of the non-transparent bridge ports of other switching circuits will not be described here.

[0080] (6) The root complex CPU sends a memory write refining transaction MWR1 to the first switching circuit SW1 with a period of 2ms. The MWR1 refining transaction passes through the first switching circuit, the second switching circuit and finally the tail switching circuit, and finally reaches the end device.

[0081] (7) After sending the MWR1 transaction, the root complex CPU sends a memory write transaction MWR2 to the first switching circuit SW1 with the target address of the BAR register of the NT port of SW1. The MWR2 transaction is address-translated by the NT port of SW1 and then switched to the downstream port 1 of the switching circuit SW6. The switching circuit SW6 routes the MWR2 transaction received at port 1 to the NT port and, after address translation at the NT port, switches it to the peer device switching circuit SW5. The switching circuit SW5 routes the MWR2 transaction received at port 1 to the NT port and, after address translation at the NT port, switches it to the peer device switching circuit SW4. Similarly, this continues until the NT port of the switching circuit SW2 switches the MWR2 transaction to port 1 of the switching circuit SW1. Port 1 of SW1 will receive the MWR2 transaction and discard it.

[0082] (8) After repeating steps (6) and (7) 65536 times, the root complex CPU queries the uncorrectable error status (address 0xFB8h) inside all switching circuits and endpoint devices in the order of the first switching circuit, the second switching circuit, and so on, until the tail switching circuit and the endpoint device. Based on the query results, it determines whether the switching circuit is working properly. If the switching circuit is working properly and the aging time has not ended, go to step (6) to continue aging until the required aging time is completed and then power off to end the aging. If a certain switching circuit is malfunctioning, go to step (9).

[0083] (9) The root complex CPU continuously outputs the number of the abnormal switching circuit to the device status indicator line through the pin in the form of a continuous low pulse signal and stops the periodic transmission of transactions.

[0084] (10) After the test monitoring personnel observe the device abnormality indication signal output by the device status indicator line, they cut off the power to end the aging process.

[0085] This invention provides a dynamic curing device and method for non-transparent bridge PCIe switching circuits. Functionally, it covers the physical layer, data link layer, and transaction layer of the circuit, as well as the address translation and switching functions of the non-transparent bridge. This allows the circuit to be dynamically cured at the normal operating frequency and bus interface speed during curing. This invention eliminates the need for an external root complex CPU and numerous PCIe endpoint devices for each non-transparent bridge PCIe switching circuit. Moreover, only one root complex CPU is needed on the entire curing board. The curing stations for M N-port circuits can save N×M (e.g., 12×100=1200)-2 external PCIe devices, greatly reducing the cost of components on the curing board. At the same time, the reduction of external PCIe devices increases the density of curing devices on the same curing board area, allowing more circuits to be cured in the same high-temperature curing chamber, thus saving on testing costs. In addition, each PCIe device (root complex, switching circuit and endpoint device) of the present invention is interconnected only with the nearest PCIe device, which can physically achieve short-distance and high-reliability transmission of the PCIe bus, reducing the difficulty of PCIe routing design on old PCBs.

Claims

1. A dynamic aging device for a non-transparent bridge (PCIe) switching circuit, the device comprising: a PCIe switch; a PCIe host bus interface; a PCIe device bus interface; a PCIe packet generator; and a PCIe packet processor. This includes the root complex CPU, endpoint devices, port mode configuration lines, port interconnect bus, and device status indicator lines. The root complex CPU is connected to the upstream port of the first switching circuit in the series switching circuit. One downstream port of the first switching circuit is connected to the upstream port of its adjacent switching circuit. Another downstream port of the first switching circuit is connected to the non-transparent bridge port of its adjacent switching circuit. The non-transparent bridge port of the first switching circuit is connected to one downstream port of the tail switching circuit. The other downstream port of the tail switching circuit is connected to the endpoint device. Multiple switching circuits are connected in series between the first switching circuit and the tail switching circuit. The upstream port of the current switching circuit is connected to one downstream port of the previous switching circuit connected in series, and the non-transparent bridge port of the current switching circuit is connected to another downstream port of the previous switching circuit connected in series. The port mode configuration line is connected to each switching circuit; the device status indicator line is connected to the root complex CPU. The port mode configuration line is used to configure the port mode of each switching circuit. A PCIe link is established between any two device ports connected by the interconnect bus. The root complex CPU is used to configure the relevant configuration registers in the non-transparent bridge PCIe switching circuit of the switching circuit, and to configure the relevant configuration registers of the endpoint devices. After configuration, a PCIe aging transaction transmission path without transaction address translation is formed between the root complex CPU, the switching circuit, and the endpoint devices. The root complex CPU is used to send aging transactions to the first switching circuit according to a preset transaction sending frequency and transaction, and to make the aging transactions pass through multiple serially connected switching circuits and endpoint devices. The root complex CPU periodically and sequentially reads the fault registers of each port of all PCIe switching circuits through the PCIe link, and determines whether the circuit is working properly based on the value of the fault report bit in the fault register.

2. The dynamic aging device of a non-transparent bridge (PCIe) switching circuit according to claim 1, wherein, The root complex CPU is used to output the abnormal status of the old switching circuit to the device status indicator line in a preset signal form and indicate the number of the abnormal circuit through signal encoding.

3. The dynamic aging device of a non-transparent bridge (PCIe) switching circuit according to claim 1, wherein, Endpoint devices are connected to the tail switching circuit via a port interconnect bus, serving as the load and excitation of a downstream port of the tail switching circuit.

4. The dynamic aging device of a non-transparent bridge (PCIe) switching circuit according to claim 1, wherein, The root complex CPU and endpoint devices use application-specific integrated circuits or FPGA circuits.

5. A method for dynamic burn-in of a non-transparent bridge (PCIe) switch circuit based on a dynamic burn-in apparatus of a non-transparent bridge (PCIe) switch circuit according to claim 1, characterized in that, Includes the following steps: S1, Power on all devices on the aging board and reset the root complex CPU device, the aging switching circuit and the endpoint device according to the maximum reset time required by the root complex CPU device, the aging switching circuit and the endpoint device. S2, after power-on reset is canceled, the port mode configuration line will fix each PCIe switching circuit on the old board to the working mode of one upstream port, at least one downstream port and at least one non-transparent bridge port; S3, completes the training and establishment of links based on each PCIe link on the port interconnect bus of multiple serially connected switching circuits of the root complex CPU device; S4. After the training and establishment of each link are completed, the root complex CPU device configures the primary bus number, secondary bus number and subordinate bus number, memory base point register and memory limit register of each transparent bridge port of each PCIe switching circuit on the old board through the PCIe link. S5, the root complex CPU device configures the BAR register and address translation register of the non-transparent bridge port of each PCIe switching circuit through the PCIe link. After configuration, it sends aging transactions sequentially through the series-connected switching circuits and endpoint devices to query the fault report registers inside all switching circuits and endpoint devices. Based on the query results, it determines whether the switching circuit is working properly. If the switching circuit is working properly and the aging time has not ended, aging continues until the required aging time is completed, and then power is cut off to end the aging process. If a switching circuit malfunctions, the root complex CPU continuously outputs the number of the malfunctioning switching circuit to the device status indicator line through a pin in a preset signal format and stops the periodic transmission of transactions. It outputs a device malfunction indicator signal and then cuts off the power to end the aging process.

6. The dynamic aging method of a non-transparent bridge (PCIe) switching circuit according to claim 5, characterized in that, When the root complex CPU and endpoint devices are implemented by the same FPGA, the endpoint devices' reception and detection status of aging transactions are directly reported to the root complex CPU via internal signals within the FPGA.

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