Memory system

Abstract

The present disclosure relates to a memory system. The memory system may include: a memory device including a memory block and a peripheral circuit; and a memory controller configured to transmit a program command based on a single-level cell scheme to the memory device to increase a threshold voltage of a selection transistor included in the memory block after an erase operation has been performed on the memory block, and configured to transmit a read command to the memory device to perform a check operation, wherein the check operation uses a first read voltage and a second read voltage higher than the first read voltage, and the check operation includes checking whether the threshold voltage falls within a range between the first read voltage and the second read voltage, or checking whether the threshold voltage is lower than the first read voltage or higher than the second read voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0150244 filed on November 11, 2020, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to a memory system, and more particularly, to a memory system including a memory device capable of storing data. Background Art

[0004] A memory system may include a memory device that may store data and a memory controller that may control the memory device.

[0005] Memory devices can be classified into volatile memory devices and nonvolatile memory devices.

[0006] A volatile memory device is a memory device that stores data only when power is supplied and loses the stored data when power supply is interrupted. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0007] A nonvolatile memory device may be a memory device that retains stored data even when power is interrupted. Examples of nonvolatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the Invention

[0008] Various embodiments of the present disclosure relate to a memory system that can quickly check the status of a memory device.

[0009] Embodiments of the present disclosure may provide a memory system. The memory system may include: a memory device including a memory block and a peripheral circuit, wherein the memory block includes a selection transistor and a memory cell coupled between a bit line and a source line, and the peripheral circuit is configured to perform a program operation or a read operation; and a memory controller configured to transmit a program command based on a single-level cell scheme to the memory device to increase a threshold voltage of the selection transistor after an erase operation has been performed on the memory block, and to transmit a read command to the memory device to perform a check operation, wherein the check operation uses a first read voltage and a second read voltage higher than the first read voltage, and wherein the check operation includes checking whether the threshold voltage of the selection transistor falls within a range between the first read voltage and the second read voltage, or checking whether the threshold voltage is lower than the first read voltage or higher than the second read voltage.

[0010] Embodiments of the present disclosure may provide a memory system. The memory system may include: a memory device including a memory block and a peripheral circuit, wherein the memory block includes a selection transistor and a memory cell connected between a bit line and a source line, and the peripheral circuit is configured to program or read the selection transistor; and a memory controller configured to transmit a command to the memory device to check the threshold voltage distribution of the selection transistor, wherein the peripheral circuit is further configured to store first data read from the selection transistor using a first read voltage in response to the command, and flip data read from the selection transistor using a second read voltage higher than the first read voltage and store the flipped data as second data, and wherein the memory controller is further configured to check the state of the memory block according to the number of fail bits included in the first data and the second data when the first data and the second data are output from the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0012] Figure 2 is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0013] Figure 3 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0014] Figure 4 It shows Figure 3 Schematic diagram of a storage block.

[0015] Figure 5 It shows Figure 4 A perspective view of the storage block.

[0016] Figure 6 It shows Figure 5 A cross-sectional view of a storage block.

[0017] Figure 7 is a diagram illustrating read voltages used in an inspection operation according to an embodiment of the present disclosure.

[0018] Figure 8 is a diagram illustrating a voltage selector according to an embodiment of the present disclosure.

[0019] Figure 9 is a diagram illustrating the operation of a memory system according to an embodiment of the present disclosure.

[0020] Figure 10 is a diagram illustrating the threshold voltage distribution of the selection transistor.

[0021] Figure 11 is a diagram illustrating a check operation of a memory system according to an embodiment of the present disclosure.

[0022] Figure 12 is a flowchart illustrating in detail a check operation of a memory system according to an embodiment of the present disclosure.

[0023] Figure 13 It is shown in detail Figure 12 Flowchart of the first checking operation.

[0024] Figure 14 1 is a diagram illustrating items of data read according to the threshold voltage of the drain selection transistor.

[0025] Figure 15 is a diagram illustrating a first checking operation according to an embodiment of the present disclosure.

[0026] Figure 16A and Figure 16B is a diagram illustrating data stored in a page buffer during a first check operation.

[0027] Figure 17 It is shown in detail Figure 12 Flowchart of the second checking operation.

[0028] Figure 18 is a diagram illustrating a second checking operation according to an embodiment of the present disclosure.

[0029] 19A to 19D is a diagram illustrating data stored in a page buffer during a second check operation.

[0030] Figure 20 is a diagram illustrating a method of operating a memory controller according to an embodiment of the present disclosure.

[0031] Figure 21A and Figure 21B are diagrams illustrating various embodiments of a comparator.

[0032] Figure 22 It shows Figure 3 Schematic diagram of an embodiment of a memory block.

[0033] Figure 23 It is shown in detail including Figure 22 Flowchart of a memory system inspection operation of a memory block.

[0034] Figure 24 is a diagram illustrating a memory card system to which the memory device according to the present disclosure is applied.

[0035] Figure 25 is a diagram illustrating a solid-state drive (SSD) system to which a memory device according to the present disclosure is applied. DETAILED DESCRIPTION

[0036] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0037] Reference Figure 1 , the memory system 1000 may include a memory device 1100 and a memory controller 1200. The memory device 1100 may include a plurality of memory devices MD, and the plurality of memory devices MD may be coupled to the memory controller 1200 through input / output lines.

[0038] The memory controller 1200 may perform communication between the host 1500 and the memory device MD. The memory controller 1200 may generate a command CMD for controlling the memory device MD in response to a request RQ from the host 1500, and may perform background operations to improve the performance of the memory system 1000 even if the request RQ is not received from the host 1500.

[0039] The host 1500 may generate request RQs for various operations and may output the generated request RQs to the memory system 1000. For example, the request RQs may include a program request for controlling a program operation, a read request for controlling a read operation, an erase request for controlling an erase operation, etc.

[0040] The host 1500 can communicate with the memory system 1000 through various interfaces such as: Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), MultiMediaCard (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0041] The memory controller 1200 according to the present embodiment can check the state of the selection transistor included in the memory device MD. For example, the memory device MD may include a plurality of strings coupled between bit lines and source lines, and each string may include a selection transistor configured to electrically couple the bit line or source line to the corresponding string or electrically decouple the bit line or source line from the corresponding string, and a memory cell coupled between the selection transistors.

[0042] The selection transistor can be configured to have the same structure as the memory cell. Therefore, after the erase operation has been performed on the memory block, a programming operation can be performed on the selection transistor so that the selection transistor becomes capable of performing a switching function. The programming operation performed on the selection transistor can be an operation to increase the threshold voltage of the selection transistor, rather than an operation to store data. Therefore, after the programming operation has been performed on the selection transistor, the memory controller 1200 can perform a check operation to check whether the threshold voltage of the selection transistor is distributed within a normal range.

[0043] For example, the memory controller 1200 may transmit a program command based on a single-level cell scheme to the selected memory device MD to increase the threshold voltage of the select transistor and transmit a read command to the memory device MD to perform a check operation. In one embodiment, the check operation may use a first read voltage and a second read voltage higher than the first read voltage to check whether the threshold voltage of the select transistor is between the first read voltage and the second read voltage. In one embodiment, the check operation may check whether the threshold voltage is lower than the first read voltage or higher than the second read voltage. An embodiment of the memory controller 1200 capable of performing the check operation will be described in detail below.

[0044] Figure 2 is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0045] Reference Figure 2 The memory controller 1200 may include a command generator 21, a memory interface 22, a counter 23, a comparator 24, and a central processing unit (or processor) 25. The command generator 21 may generate a command CMD in response to a control signal CONS. The command generator 21 may generate a command CMD for performing a program operation, a read operation, or an erase operation in response to the control signal CONS. According to this embodiment, the command generator 21 may generate a program command based on a single-level cell scheme, and may generate a read command during a check operation in response to the control signal CONS for the check operation, and then generate an output command.

[0046] For example, upon receiving the control signal CONS for the inspection operation, the command generator 21 may generate a read command based on a multi-level cell scheme. The multi-level cell scheme may be a scheme in which two bits of data are stored in a memory cell and two bits of data are read from the memory cell, and may be different from a single-level cell scheme in which one bit of data is stored in a memory cell and one bit of data is read from the memory cell. That is, when the number of bits stored in a memory cell changes, the threshold voltage distribution of the memory cell changes, and thus the read voltage used in the read operation may also change.

[0047] In this embodiment, the read commands that can be used for the inspection operation are not limited to the multi-layer cell scheme, and read commands used in a cell scheme with a higher layer than the multi-layer cell scheme can be used. For example, the command generator 21 can generate a read command based on a three-layer cell scheme in which three bits of data are stored in a memory cell and three bits of data are read from the memory cell, and can generate a read command based on a four-layer cell scheme in which four bits of data are stored in a memory cell and four bits of data are read from the memory cell. Alternatively, a read command based on a scheme in which five or more bits of data are stored in a memory cell and five or more bits of data are read from the memory cell can be used. The read command used in the inspection operation can be preset in the command generator 21, taking into account the threshold voltage of the select transistor included in the memory device.

[0048] The memory interface 22 may transmit the command CMD generated by the command generator 21 to the selected memory device MD. For example, when the command generator 21 generates multiple commands, the memory interface 22 may queue the multiple commands sequentially and output the commands in the queued order. Furthermore, the memory interface 22 may receive data DATA output from the memory device MD and transmit the received data DATA to the counter 23.

[0049] The counter 23 can count the number of selected data items included in the data DATA transmitted from the memory interface 22 and can output a count value VALc. For example, the counter 23 can count the number of fail bits included in the data DATA. The fail bit can be selected as either data "1" or data "0". In this embodiment, the case where data "1" is set as the fail bit is described by way of example.

[0050] The comparator 24 can compare the count value VALc with a reference value and, based on the comparison result, generate and output state information STinfo of the memory block. For example, when the count value VALc is greater than the reference value, the comparator 24 can output state information STinfo indicating a bad state. When the count value VALc is less than or equal to the reference value, the comparator 24 can output state information STinfo indicating a normal state. Alternatively, the comparator 24 can generate and output state information STinfo corresponding to various states based on the count value VALc.

[0051] The central processing unit 25 may update the status of the memory block according to the status information STinfo and may manage the memory block based on the updated status. For example, the central processing unit 25 may output a control signal CONS based on the status information STinfo during a subsequent operation on the memory block corresponding to the status information STinfo. The control signal CONS may be transmitted to the command generator 21, and the command generator 21 may generate a command for the subsequent operation in response to the control signal CONS.

[0052] Figure 3 is a diagram illustrating a memory device MD according to an embodiment of the present disclosure.

[0053] Reference Figure 3 The memory device MD may include a memory cell array 110 that stores data, a peripheral circuit 200 that performs a program operation, a read operation, or an erase operation, and a logic circuit 160 that controls the peripheral circuit 200 .

[0054] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKi in which data is stored. Each of the memory blocks BLK1 to BLKi may include a plurality of memory cells, which may be implemented in a two-dimensional (2D) structure in which the memory cells are horizontally arranged on a substrate or in a three-dimensional (3D) structure in which the memory cells are vertically stacked on a substrate.

[0055] The peripheral circuit 200 may include a voltage generator 120, a row decoder 130, a page buffer group 140, and an input / output circuit 150. The voltage generator 120 may generate and output an operating voltage Vop for various operations in response to a voltage code VCD. For example, the voltage generator 120 may generate and output a program voltage, a verification voltage, a read voltage, a pass voltage, an erase voltage, etc. having various levels.

[0056] The row decoder 130 may select one memory block from among the memory blocks BLK1 to BLKi included in the memory cell array 110 according to the row address RADD, and may transfer the operating voltage Vop to the selected memory block.

[0057] The page buffer group 140 may be coupled to the memory cell array 110 via a bit line. For example, the page buffer group 140 may include page buffers coupled to respective bit lines. The page buffers may operate simultaneously in response to a page buffer control signal PBSIG and may temporarily store data during a program operation or a read operation.

[0058] During the inspection operation according to the present embodiment, in response to the page buffer control signal PBSIG, the page buffer group 140 may store the data sensed from the selected page in the selected memory block, or may flip the sensed data and store the flipped data. Here, the flipped data refers to the inverse data of the sensed data.

[0059] The input / output circuit 150 may be coupled to a memory controller (eg, Figure 1 The input / output circuit 150 may receive / output a command CMD, an address ADD, and data DATA through the input / output lines. For example, the input / output circuit 150 may transmit the command CMD and the address ADD received through the input / output lines to the logic circuit 160, and transmit the data DATA received through the input / output lines to the page buffer group 140. The input / output circuit 150 may output the data DATA received from the page buffer group 140 to the memory controller 1200 through the input / output lines.

[0060] The logic circuit 160 may output a voltage code VCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, the logic circuit 160 may include software that executes an algorithm in response to the command CMD and hardware that outputs various signals based on the address ADD and the algorithm.

[0061] The logic circuit 160 according to this embodiment can control the peripheral circuit 200 to check the state of the selection transistors included in the memory blocks BLK1 to BLKi in response to the command CMD. When receiving the command CMD for a read operation, the logic circuit 160 can select a read voltage corresponding to the command CMD and can output a voltage code VCD for generating the selected read voltage. For example, the logic circuit 160 may include a voltage selector 161 for outputting a voltage code VCD corresponding to the read voltage in response to the command CMD. The voltage selector 161 can select a single read voltage or multiple read voltages to be used in the read operation in response to the command CMD.

[0062] Figure 4 It shows Figure 3A diagram of a memory block showing Figure 3 An i-th memory block BLKi among the plurality of memory blocks BLK1 to BLKi is shown as an example.

[0063] Reference Figure 4 , the i-th memory block BLKi may include a plurality of strings ST1 to STj (where j is a positive integer). The first to j-th strings ST1 to STj may be coupled between the bit lines BL1 to BLj and the source line SL. For example, the first string ST1 may be coupled between the first bit line BL1 and the source line SL, the second string ST2 may be coupled between the second bit line BL2 and the source line SL, and the j-th string STj may be coupled between the j-th bit line BLj and the source line SL.

[0064] Each of the first to j-th strings ST1 to STj may include a source select transistor SST, a plurality of memory cells C1 to Cn, and a drain select transistor DST, and may further include a dummy cell between the memory cells C1 to Cn and the source select transistor SST or the drain select transistor DST, although not shown in the figure. The configuration of the j-th string STj is described in detail below by way of example.

[0065] The source select transistor SST included in the jth string STj can electrically couple the source line SL and the first memory cell C1 to each other or electrically decouple them according to the voltage applied to the source select line SSL. The gates of the first to nth memory cells C1 to Cn can be connected to the first to nth word lines WL1 to WLn, respectively. The drain select transistor DST can electrically couple the jth bit line BLj and the nth memory cell Cn to each other or electrically decouple them according to the voltage applied to the drain select line DSL. The gates of the source select transistors SST included in different strings ST1 to STj can be commonly connected to the source select line SSL, the gates of the first to nth memory cells C1 to Cn can be connected to the first to nth word lines WL1 to WLn, and the gates of the drain select transistors DST can be commonly connected to the drain select line DSL. A group of memory cells connected to the same word line can be referred to as a page (PG), and programming operations and read operations can be performed based on the page (PG).

[0066] The programming operation according to the present embodiment can be performed in an incremental step pulse programming (ISPP) method in which the programming voltage is gradually increased. During the programming operation performed in the ISPP method, multiple programming loops can be performed until the threshold voltage of the selected memory cell increases to the target voltage, and the programming voltage can be gradually increased each time each programming loop is performed.

[0067] The first to nth memory cells C1 to Cn can use various schemes to program or read data according to the number of bits stored. For example, in a single-level cell scheme, one bit of data can be stored in one memory cell and one bit of data can be read from one memory cell, and in a multi-level cell scheme, two bits of data can be stored in one memory cell and two bits of data can be read from one memory cell.

[0068] In a single-level cell scheme, each memory cell stores one bit of data, so the data stored in the memory cell can be either 0 or 1. That is, each memory cell programmed in the single-level cell scheme can be in either an erased state or a programmed state. Therefore, during a read operation based on the single-level cell scheme, threshold voltage distributions in an erased state and in a programmed state can be distinguished from each other using a single read voltage.

[0069] In the MLC scheme, two bits of data are stored in each memory cell, so the data stored in the memory cell can be 00, 01, 10, or 11. That is, each memory cell programmed in the MLC scheme can be in one erased state or in one of three programmed states. Therefore, during a read operation based on the MLC scheme, three read voltages can be used to distinguish the threshold voltage distributions in one erased state from those in the three programmed states.

[0070] A program operation or a read operation may be performed based on various schemes such as a triple-level cell scheme storing three bits of data in one memory cell and a quad-level cell scheme storing four bits of data in one memory cell in addition to the multi-level cell scheme.

[0071] The logic circuit 160 according to the present embodiment may be configured to program the selection transistors included in the erased memory block according to the single-level cell scheme. The logic circuit 160 may be configured to read the selected transistors programmed according to the single-level cell scheme according to the multi-level cell scheme or the triple-level cell scheme to check the selected transistors. The logic circuit 160 may be configured to perform a read operation using various schemes such as a quad-level cell scheme or a higher-level cell scheme in addition to the single-level cell scheme.

[0072] Figure 5 It shows Figure 4 A perspective view of the storage block. Figure 5 and Figure 4, the i-th memory block BLKi according to the present embodiment can be implemented in a three-dimensional (3D) structure. When the source line SL is horizontally formed on top of the substrate, the strings ST1 to ST4 can be formed on top of the source line SL in a vertical direction (e.g., Z direction). For example, the source select line SSL, the word line WL, and the drain select line DSL can be sequentially stacked on the source line SL. The number of source select lines SSL, the number of word lines WL, and the number of drain select lines DSL are not limited to the numbers shown in the figure and can be changed according to the memory device.

[0073] Each of the strings ST1 to ST4 may include a memory layer ML that vertically extends through a source select line SSL, a word line WL, and a drain select line DSL. The memory layer ML may include a charge trapping layer capable of trapping electrons. A contact CT may be formed on top of the memory layer ML, and a bit line BL may be formed on top of the contact CT. To describe any one of the strings ST1 to ST4 in detail, a cross section II' will be described below.

[0074] Figure 6 It shows Figure 5 FIG. 1 is a view of an example of a cross section II′ of a memory block, which may correspond to or represent any one string.

[0075] Reference Figure 6 The source select line SSL, the word line WL, and the drain select line DSL may be sequentially stacked on top of the source line SL. The memory layer ML may be formed to vertically penetrate (eg, along the Z direction) the drain select line DSL, the word line WL, and the source select line SSL.

[0076] According to one embodiment, the memory layer ML may be formed in a predetermined (e.g., cylindrical) shape and may include a blocking layer 61, a charge trapping layer 62, and a tunnel isolation layer 63 in sequence from the outer circumference to the inner circumference. The blocking layer 61 may be formed of an insulating layer, such as an oxide layer. The charge trapping layer 62 may be a layer for storing data and may be formed of a nitride layer. For example, electrons having a negative charge may be stored in the charge trapping layer 62 using a programming voltage during a programming operation, and electrons stored in the charge trapping layer 62 may be discharged to the outside using an erase voltage during an erase operation. The tunnel isolation layer 63 may be formed of an insulating layer, such as an oxide layer.

[0077] The channel layer 64 may be formed on the inner circumferential surface of the cylindrical memory layer ML. The channel layer 64 may have a predetermined shape (e.g., a cylindrical shape), may be a layer through which charges can move, and may be formed, for example, of an undoped semiconductor layer. In embodiments, the undoped semiconductor layer may include an undoped silicon layer.

[0078] The plug PL may be formed inside the cylindrical channel layer 64 and may have a predetermined shape, such as a cylindrical shape. For example, the plug PL may include a vertical isolation layer 65 and a capping layer 70. Both the vertical isolation layer 65 and the capping layer 70 may be formed in a cylindrical shape, and the capping layer 70 may be formed on top of the vertical isolation layer 65. The vertical isolation layer 65 may be formed of an insulating layer, such as an oxide layer. The capping layer 70 may be formed of a doped silicon layer doped with impurities.

[0079] Contact CT may be formed on top of memory layer ML, channel layer 64, and plug PL, and bit line BL may be formed on top of contact CT. Contact CT may be a layer for electrically coupling bit line BL to channel layer 64 and may form a conductive layer.

[0080] In a memory block having a 3D structure, the source select transistor SST, the memory cell Cn, and the drain select transistor DST can be formed into a similar structure. For example, similar to the memory cell Cn, each of the source select transistor SST and the drain select transistor DST can include a charge trapping layer 62. Therefore, in order to enable the source select transistor SST and the drain select transistor DST to perform a switching function, the source select transistor SST and the drain select transistor DST can be programmed to have a threshold voltage at a predetermined level. For example, after an erase operation has been performed on the memory block, a programming operation to increase the threshold voltage of the source select transistor SST and the drain select transistor DST can be performed. For example, the programming operation to increase the threshold voltage of the source select transistor SST and the drain select transistor DST can be performed as a background operation rather than as an operation in response to a user request.

[0081] Since all strings included in a memory block include source select transistors SST and drain select transistors DST, when a program operation is performed to increase the threshold voltages of the source select transistors SST and drain select transistors DST, the threshold voltage distribution of the source select transistors SST and drain select transistors DST is formed within a predetermined level range. Therefore, there may be a difference in the threshold voltages of the drain select transistors DST or source select transistors SST coupled to the same drain select line DSL or the same source select line SSL.

[0082] In order for the source select transistor SST and the drain select transistor DST to operate normally, the threshold voltage distribution of each of the source select transistor SST and the drain select transistor DST should fall within the range between the turn-on voltage and the turn-off voltage applied to the gates of the source select transistor SST and the drain select transistor DST. For example, the threshold voltage of the source select transistor SST and the drain select transistor DST should be lower than the turn-on voltage and higher than the turn-off voltage. Therefore, when a memory block includes a source select transistor SST or a drain select transistor DST whose threshold voltage is lower than the turn-off voltage or whose threshold voltage is higher than the turn-on voltage, normal operation cannot be performed on the corresponding memory block. Therefore, the present embodiment discloses a technology for quickly checking source select transistors SST and drain select transistors DST whose threshold voltage exceeds the normal or expected range from a first read voltage to a second read voltage.

[0083] Figure 7 is a diagram illustrating read voltages used in an inspection operation according to an embodiment of the present disclosure.

[0084] Reference Figure 7 , in a single-level cell (SLC) scheme, memory cells may be programmed only to a first program state P1, and thus a first read voltage Vr1 may be used in a read operation.

[0085] In a multi-level cell (MLC) scheme, memory cells can be programmed into first to third program states P1 to P3, and therefore first to third read voltages Vr1 to Vr3 can be used in a read operation. For example, the first read voltage Vr1 used in the MLC scheme can be a voltage used to distinguish memory cells in the erased state ER from memory cells in the first to third program states P1 to P3. The second read voltage Vr2 can be a voltage used to distinguish memory cells in the erased state ER and the first program state P1 from memory cells in the second program state P2 and the third program state P3. The third read voltage Vr3 can be a voltage used to distinguish memory cells in the erased state ER and the first and second program states P1 and P2 from memory cells in the third program state P3.

[0086] In a triple-level cell (TLC) scheme, memory cells can be programmed into first to seventh program states P1 to P7, and thus first to seventh read voltages Vr1 to Vr7 can be used in a read operation. For example, the first read voltage Vr1 used in the triple-level cell (TLC) scheme can be a voltage used to distinguish memory cells in the erased state ER from memory cells in the first to seventh program states P1 to P7. The second read voltage Vr2 can be a voltage used to distinguish memory cells in the erased state ER and the first program state P1 from memory cells in the second to seventh program states P2 to P7. The third read voltage Vr3 can be a voltage used to distinguish memory cells in the erased state ER and the first and second program states P1 and P2 from memory cells in the third to seventh program states P3 to P7. The fourth read voltage Vr4 can be a voltage used to distinguish memory cells in the erased state ER and the first to third program states P1 to P3 from memory cells in the fourth to seventh program states P4 to P7. The fifth read voltage Vr5 may be a voltage for distinguishing memory cells in the erased state ER and the first to fourth program states P1 to P4 from memory cells in the fifth to seventh program states P5 to P7. The sixth read voltage Vr6 may be a voltage for distinguishing memory cells in the erased state ER and the first to fifth program states P1 to P5 from memory cells in the sixth program state P6 and the seventh program state P7. The seventh read voltage Vr7 may be a voltage for distinguishing memory cells in the erased state ER and the first to sixth program states P1 to P6 from memory cells in the seventh program state P7.

[0087] In this embodiment, during the inspection operation, the selection transistor can be programmed using a single-level cell (SLC) scheme and the selection transistor can be read using a cell scheme of a higher level than the single-level cell (SLC) scheme. For example, the selection transistor programmed according to the single-level cell (SLC) scheme can be read using a multi-level cell (MLC) scheme or a triple-level cell (TLC) scheme. In particular, during the inspection operation of inspecting the state of the threshold voltage of the selection transistor programmed according to the single-level cell (SLC) scheme, two read voltages can be used in sequence according to the multi-level cell (MLC) scheme or the triple-level cell (TLC) scheme to quickly inspect the low threshold voltage and the high threshold voltage of the selection transistor. Here, the selection transistor with a low threshold voltage can be a slow transistor whose threshold voltage increases slower than normal time, and the selection transistor with a high threshold voltage can be a fast transistor whose threshold voltage increases faster than normal time.

[0088] In the case of a read operation based on a multi-level cell (MLC) scheme, for example, in response to a read command, a read operation using the second read voltage Vr2 can be performed, and a read operation using the first read voltage Vr1 and the third read voltage Vr3 can be performed. During the read operation using the second read voltage Vr2, all memory cells in the erased state ER and the first programmed state P1 can be read as memory cells in the erased state relative to the second read voltage Vr2, and memory cells in the second programmed state P2 and the third programmed state P3 can be read as memory cells in the programmed state. During the read operation using the first read voltage Vr1 and the third read voltage Vr3, the read operation using the third read voltage Vr3 can be performed after the read operation using the first read voltage Vr1 has been performed. Conversely, the read operation using the first read voltage Vr1 can be performed after the read operation using the third read voltage Vr3 has been performed. In this embodiment, a read operation is performed to check whether the select transistor includes a slow transistor and a fast transistor, so a read operation using at least two read voltages can be performed sequentially.

[0089] In this embodiment, during a check operation for checking a state of a threshold voltage of a selection transistor programmed according to a single-level cell (SLC) scheme, a first read voltage Vr1 and a third read voltage Vr3 may be sequentially used when a read operation is performed according to a multi-level cell (MLC) scheme in order to quickly check a low threshold voltage and a high threshold voltage of the selection transistor.

[0090] Even in the case of a read operation based on a triple-level cell (TLC) scheme, a read operation using at least two read voltages in sequence can be performed. For example, a read operation using a first read voltage Vr1 and a fourth read voltage Vr4 in sequence can be performed. In this embodiment, during a check operation for checking the state of the threshold voltage of a select transistor programmed according to a single-level cell (SLC) scheme, these first read voltage Vr1 and fourth read voltage Vr4 can be used in sequence when performing a read operation according to the triple-level cell (TLC) scheme to quickly check the low threshold voltage and the high threshold voltage of the select transistor.

[0091] In this embodiment, the inspection operation may be performed as a read operation based on a multi-level cell (MLC) scheme or a triple-level cell (TLC) scheme, or may be performed as a read operation based on a quad-level cell (QLC) scheme, etc. The scheme of the read operation and the read voltage of the inspection operation may be selected differently depending on the threshold voltage distribution of the selection transistor to be programmed.

[0092] In the present embodiment, a read voltage may be selected by a voltage selector 161 included in the logic circuit 160 in response to a command CMD provided from the memory controller 1200 .

[0093] Figure 8 is a diagram illustrating a voltage selector according to an embodiment of the present disclosure.

[0094] Reference Figure 8 , the voltage selector 161 may output a read voltage in response to the command CMD. The voltage selector 161 may select a read voltage to be used in the inspection operation according to the type of the command CMD, and may output a voltage code VCD for generating the selected read voltage. For example, when a read command CMDr_S based on a single-level cell (SLC) scheme is received, the voltage selector 161 may output a voltage code VCD for generating a first read voltage Vr1. When a read command CMDr_m based on a multi-level cell (MLC) scheme is received, the voltage selector 161 may output a voltage code VCD for generating a first read voltage Vr1 and a third read voltage Vr3, as well as a voltage code VCD for generating a second read voltage Vr2. When receiving a read command CMDr_t based on a triple-layer cell (TLC) scheme, the voltage selector 161 can output a voltage code VCD for generating a first read voltage Vr1 and a fourth read voltage Vr4, a voltage code VCD for generating a second read voltage Vr2 and a fifth read voltage Vr5, and a voltage code VCD for generating a third read voltage Vr3, a sixth read voltage Vr6, and a seventh read voltage Vr7.

[0095] During an inspection operation according to the present embodiment, when a read command CMDr_m based on a multi-level cell (MLC) scheme is received, the voltage selector 161 may output a voltage code VCD for generating a first read voltage Vr1 and a third read voltage Vr3, and a voltage code VCD for generating a second read voltage Vr2. When a read command CMDr_t based on a triple-level cell (TLC) scheme is received, the voltage selector 161 may output a voltage code VCD for generating a first read voltage Vr1 and a fourth read voltage Vr4, a voltage code VCD for generating a second read voltage Vr2 and a fifth read voltage Vr5, and a voltage code VCD for generating a third read voltage Vr3, a sixth read voltage Vr6, and a seventh read voltage Vr7.

[0096] Figure 9 is a diagram illustrating the operation of a memory system according to an embodiment of the present disclosure.

[0097] Reference Figure 9When the erase operation performed on the memory block selected from the memory blocks included in the memory device is completed in step S71, the memory system may perform a program operation to increase the threshold voltage of the selection transistors DST and SST included in the selected memory block in step S72. The program operation on the selection transistors DST and SST may be performed using a single-level cell (SLC) scheme.

[0098] After completing the programming operation performed on the selection transistors DST and SST, the memory system may perform a check operation to check the threshold voltage Vth of the selection transistors DST and SST in step S73. The check operation may be performed as a read operation based on a multi-level cell (MLC) scheme or a higher-level cell scheme. The memory system may check the state of the selection transistor based on data read from the selection transistor during the read operation and may determine whether the selected memory block including the selection transistor is a bad block or a normal block.

[0099] The memory system may store state information of the selected memory block generated during the check operation and may utilize the state information during subsequent operations to be performed on the selected memory block. Examples of the threshold voltage of the select transistor will be described in detail below.

[0100] Figure 10 is a diagram illustrating the threshold voltage distribution of the selection transistor.

[0101] Reference Figure 10 , assuming that the threshold voltage of the normal selection transistor is distributed in the range from the first read voltage V1 to the second read voltage V2. The first read voltage V1 may be lower than the second read voltage V2. In this embodiment, when a read operation is performed according to a multi-level cell (MLC) scheme for an inspection operation, Figure 7 The first read voltage Vr1 and the third read voltage Vr3 shown may be the first read voltage V1 and the second read voltage V2, respectively. In this embodiment, when a read operation is performed according to a triple-layer cell (TLC) scheme for a check operation, Figure 7 The illustrated first read voltage Vr1 and seventh read voltage Vr7 may be the first read voltage V1 and the second read voltage V2 , respectively.

[0102] When the threshold voltage of the selection transistor falls within a range Nlow lower than the first read voltage V1 (81), the conduction level of the selection transistor is lower than the reference level, thereby generating leakage current. When the threshold voltage of the selection transistor falls within a range Nhigh higher than the second read voltage V2 (82), the conduction level of the selection transistor is higher than the reference level, thereby turning off the selection transistor in an operation in which the selection transistor should be turned on.

[0103] A selection transistor having a threshold voltage lower than the first read voltage V1 may be a slow selection transistor, and a selection transistor having a threshold voltage higher than the second read voltage V2 may be a fast selection transistor. Since the selection transistors included in the memory block electrically couple or decouple the bit line or source line and the string to each other, when the slow selection transistor or the fast selection transistor is included in the memory block, the reliability of the memory block may be degraded.

[0104] Therefore, the memory system according to the present embodiment can determine whether a slow selection transistor or a fast selection transistor is included in a memory block through a check operation, and can determine a state of the memory block based on data read in the check operation.

[0105] Figure 11 is a diagram illustrating a check operation of a memory system according to an embodiment of the present disclosure.

[0106] Reference Figure 11 When the check operation is started, the memory controller may output a read command CMDr and an address ADD to the selected memory device MD. The read command CMDr may be a read command based on a multi-level cell scheme or a triple-level cell scheme, and the address ADD may be the address of a memory block that is the target of the check operation.

[0107] The memory device MD may sequentially perform a first read operation 1RD and a second read operation 2RD in response to a read command CMDr and an address ADD. A period during which the first read operation 1RD and the second read operation 2RD are performed may be a busy period BS during which the memory controller does not transmit other commands to the corresponding memory device. The first read operation 1RD may be an operation for checking the state of a drain select transistor, and the second read operation 2RD may be an operation for checking the state of a source select transistor.

[0108] During the first read operation, a read operation for checking the low threshold voltage of the drain select transistor and a read operation for checking the high threshold voltage of the drain select transistor may be sequentially performed. During the second read operation, a read operation for checking the low threshold voltage of the source select transistor and a read operation for checking the high threshold voltage of the source select transistor may be sequentially performed.

[0109] The memory device can quickly transmit read data to the memory controller. The memory device can flip the read data read during certain read operations to help the memory controller quickly check the status of the memory block. For example, the memory device can store data read during a read operation that checks a low threshold voltage without change, and can flip and then store data read during a read operation that checks a high threshold voltage.

[0110] For example, when reading data in a read operation that checks a high threshold voltage, the memory device may additionally perform a data flip operation (DATA Flip) that flips the read data. The data flip operation may be performed to adjust the items of data read from a selection transistor having a threshold voltage lower than or higher than a normal range to have the same value. For example, assuming that the fail bit of a selection transistor having a threshold voltage lower than the normal range has a value of "1," a data flip operation may be performed to adjust the items of data of a selection transistor having a threshold voltage higher than the normal range to have the same value of "1." In this embodiment, although the description is made on the assumption that the fail bit of a selection transistor having a threshold voltage outside the normal range is "1," the fail bit may be set to "0" depending on the memory system.

[0111] The data flip operation may be performed in the read operation checking the high threshold voltage during the first read operation 1RD, and may also be performed in the read operation checking the high threshold voltage during the second read operation 2RD.

[0112] When the busy period BS ends, the memory controller may output an output command CMDo to the memory device MD. In response to the output command CMDo, the memory device may output first data DATA1 and second data DATA2 to the memory controller, where the first data DATA1 is the result of the first read operation 1RD and the second data DATA2 is the result of the second read operation 2RD. Because the first data DATA1 includes fail bits for select transistors having threshold voltages lower than and higher than the reference voltage, the memory device may output the first data DATA1 to the memory controller. This operation may be performed without distinguishing data (read to check for threshold voltages lower than the reference voltage) from data (read to check for threshold voltages higher than the reference voltage). The memory device MD may transmit the first data DATA1 to the memory controller and, in turn, output the second data DATA2 to the memory controller.

[0113] In this manner, the read operation for checking the low threshold voltage and the read operation for checking the high threshold voltage are performed separately, but the first data DATA1 or the second data DATA2 includes the data items read in the respective read operations.

[0114] When all of the first data DATA1 and the second data DATA2 are output, the memory controller can count the number of fail bits included in the first data DATA1 and the second data DATA2, and can determine the state of the memory block based on the counting result. In this embodiment, it is assumed that the time when the memory controller counts the number of fail bits is the second time T2, and the fail bit is a "1" between the bit "0" and the bit "1" included in the first data DATA1 and the second data DATA2, and is equal to each other, so compared with the case where the fail bit includes both "0" and "1", the second time T2 is shortened.

[0115] That is, according to this embodiment, the first time T1 during which the memory device MD outputs the first data DATA1 and the second data DATA2 to the memory controller and the second time T2 during which the memory controller counts the number of fail bits in the first data DATA1 and the second data DATA2 and checks the status of the memory block can be shortened.

[0116] Figure 12 is a flowchart illustrating in detail a check operation of a memory system according to an embodiment of the present disclosure.

[0117] Reference Figure 12 In step S101, a memory controller included in a memory system may generate a read command CMDr and an address ADD, and may transmit the read command CMDr and the address ADD to a memory device.

[0118] The memory device may sequentially perform a first inspection operation S1010 on the drain select transistors included in the selected memory block and a second inspection operation S1020 on the source select transistors included in the selected memory block in response to a read command CMDr and an address ADD. An example of the first inspection operation S1010 performed on the drain select transistor DST is described in detail below.

[0119] In step S102, the memory device may perform a read operation to check a low threshold voltage Vth_low and a high threshold voltage Vth_high of a drain select transistor included in a selected memory block. In step S102, the low threshold voltage Vth_low may be read using a relatively low read voltage among a plurality of read voltages selected in response to a read command CMDr, and the high threshold voltage Vth_high may be read using a relatively high read voltage among the read voltages.

[0120] At step S103, the memory device may temporarily store the read first data DATA1 in a page buffer. At step S103, the read data for the low threshold voltage Vth_low may be stored unchanged in the page buffer, and the read data for the high threshold voltage Vth_high may be flipped and stored in the page buffer. The first data DATA1 may include the read data for the low threshold voltage Vth_low and the flipped read data for the high threshold voltage Vth_high. An example of the second inspection operation S1020 performed on the source select transistor SST will be described in detail below.

[0121] In step S104, the memory device may read the low threshold voltage Vth_low and the high threshold voltage Vth_high of the source select transistors included in the selected memory block, respectively. In step S104, the low threshold voltage Vth_low may be read using a relatively low read voltage among a plurality of read voltages selected in response to the read command CMDr, and the high threshold voltage Vth_high may be read using a relatively high read voltage among the read voltages.

[0122] In step S105, the memory device may temporarily store the read second data DATA2 in a page buffer. In step S105, the read data for the low threshold voltage Vth_low may be stored in the page buffer without change, and the read data for the high threshold voltage Vth_high may be flipped and stored in the page buffer. The second data DATA2 may include the read data for the low threshold voltage Vth_low and the flipped read data for the high threshold voltage Vth_high.

[0123] In step S106 , when the read operation performed on the drain select transistor DST and the source select transistor SST is completed, the memory controller may transmit an output command CMDo to the memory device.

[0124] In step S107 , the memory device may output the first data DATA1 and the second data DATA2 stored in the page buffer to the memory controller in response to the output command CMDo.

[0125] In step S108, the memory controller may count the number of fail bits included in the first data DATA1 and the second data DATA2, and may check the status of the storage block based on the count value. For example, when the data value "1" is set as the fail bit, the memory controller may process the corresponding storage block as a bad block or a normal block based on the count value of the fail bits included in the first data DATA1 and the second data DATA2. For example, when the count value is greater than a reference value, the memory controller may process the corresponding storage block as a bad block, and when the count value is less than or equal to the reference value, the memory controller may process the storage block as a normal block. Optionally, the memory controller may identify the status of the storage block in different ways based on the count value.

[0126] Figure 13 It is shown in detail Figure 12 Flowchart of the first checking operation.

[0127] Reference Figure 13 , a first inspection operation S1010 may be performed to inspect a threshold voltage of a drain selection transistor DST included in a memory block.

[0128] In step S111, when the first check operation S1010 is started, the memory device may perform a read operation of checking a low threshold voltage Vth_low among the threshold voltages of the drain select transistors DST included in the memory block. For example, when the read command is a command based on a multi-level cell (MLC) scheme, the memory device may perform a read operation on the drain select transistor DST by performing a read operation using a first read voltage Vr1, as shown in FIG. Figure 8 A first read voltage Vr1 may be applied to drain select lines commonly coupled to gates of drain select transistors.

[0129] At step S112 , the 1-1th data DATA1 - 1 sensed during the read operation of checking the low threshold voltage Vth_low of the drain select transistor DST may be temporarily stored in the page buffer.

[0130] Then, in step S113, the memory device may perform a read operation of checking a high threshold voltage Vth_high among the threshold voltages of the drain select transistors DST included in the memory block. For example, when the read command is a command based on a multi-level cell (MLC) scheme, the memory device may perform a read operation on the drain select transistor DST by performing a read operation using a third read voltage Vr3, as shown in FIG. Figure 8 A third read voltage Vr3 may be applied to drain select lines commonly coupled to the gates of the drain select transistors.

[0131] In step S114 , data sensed during a read operation to check the high threshold voltage Vth_high of the drain select transistor DST may be temporarily stored in the page buffer, after which the temporarily stored data may be flipped in the page buffer and then changed into the 1-2 th data DATA1 - 2 .

[0132] In step S115 , in the page buffer, first data DATA1 including 1-1th data DATA1 - 1 and 1-2th data DATA1 - 2 may be stored.

[0133] Figure 14 1 is a diagram illustrating items of data read according to the threshold voltage of the drain selection transistor.

[0134] Reference Figure 14 When the drain select transistors are read using the first read voltage Vr1, the 1-1 data DATA1-1 of the drain select transistors having a threshold voltage lower than the first read voltage Vr1 may be sensed as "1," and the 1-1 data DATA1-1 of the drain select transistors having a threshold voltage equal to or higher than the first read voltage Vr1 may be sensed as "0." The sensed 1-1 data DATA1-1 may be stored in the page buffer. During a read operation using the first read voltage Vr1, the drain select transistors having a threshold voltage lower than the first read voltage Vr1 are slow transistors whose programming speed is slower than normal. Therefore, the data of the slow transistors, that is, 1, may be a fail bit.

[0135] Then, when the drain select transistors are read using the third read voltage Vr3, data from drain select transistors with threshold voltages lower than the third read voltage Vr3 may be sensed as "1," and data from drain select transistors with threshold voltages equal to or higher than the third read voltage Vr3 may be sensed as "0." While the data sensed in this step remains unchanged, the drain select transistors with threshold voltages equal to or higher than the third read voltage Vr3 are fast transistors whose programming speed is higher than normal, and therefore the data from these fast transistors, namely, "0," may be a fail bit. However, since "1" is a fail bit in the 1-1th data DATA1-1, the memory device can use the third read voltage Vr3 to flip the data sensed during the read operation and then store the 1-2th data DATA1-2 in the page buffer. Therefore, even in the 1-2th data DATA1-2, a "1" may be a fail bit.

[0136] Figure 15 is a diagram illustrating a first checking operation according to an embodiment of the present disclosure.

[0137] Reference Figure 15, drain select transistors DST included in the memory block may be coupled to the first to i-th bit lines BL1 to BLi, respectively. Since the first inspection operation is performed as a read operation on the drain select transistors DST, the 1-1th data DATA1-1 and the 1-2th data DATA1-2 sensed during the read operation may be stored in the first to i-th page buffers PB1 to PBi, respectively coupled to the first to i-th bit lines BL1 to BLi. An embodiment of the operation of storing the 1-1th data DATA1-1 and the 1-2th data DATA1-2 in the first to i-th page buffers PB1 to PBi will be described below.

[0138] Figure 16A and Figure 16B is a diagram illustrating data stored in a page buffer during a first check operation, wherein a first page buffer coupled to a first bit line is shown as an example.

[0139] Reference Figure 16A and Figure 15 , the first page buffer PB1 may include first to j-th latches LT1 to LTj. Among the first to j-th latches LT1 to LTj, the first latch LT1 may store data received through the first bit line BL1 during a read operation, and each of the second to j-th latches LT2 to LTj may exchange data stored therein with another latch.

[0140] When a first read voltage Vr1 is applied to the drain select line DSL and then a read operation is performed, data sensed from the corresponding drain select transistor DST may be stored in the first latch LT1 through the first bit line BL1 (11). Subsequently, the data stored in the first latch LT1 may be transmitted to the second latch LT2 for a subsequent read operation (12). The data transmitted to the second latch LT2 may be data included in the 1-1th data DATA1-1.

[0141] Reference Figure 16B and Figure 15 , when the third read voltage Vr3 is applied to the drain select line DSL and then a read operation is performed, the data sensed from the corresponding drain select transistor DST may be stored in the first latch LT1 through the first bit line BL1 (13). Subsequently, the data stored in the first latch LT1 may be transmitted to the third latch LT3 (14). Thereafter, the first page buffer PB1 may flip the data stored in the third latch LT3 in response to the page buffer control signal. The flipped data stored in the third latch LT3 may be the data included in the 1-2 data DATA1-2.

[0142] Figure 17 It is shown in detail Figure 12 Flowchart of the second checking operation.

[0143] Reference Figure 17 , a second inspection operation S1020 may be performed to inspect a threshold voltage of a source selection transistor SST included in a memory block.

[0144] In step S151, when the second check operation S1020 is started, the memory device may perform a read operation of checking a low threshold voltage Vth_low among the threshold voltages of the source select transistors SST included in the memory block. For example, when the read command is a command based on a multi-level cell (MLC) scheme, the memory device may perform a read operation on the source select transistor SST by performing a read operation using a first read voltage Vr1, as shown in FIG. Figure 8 The first read voltage Vr1 may be applied to source select lines commonly coupled to gates of the source select transistors SST.

[0145] At step S152 , the 2-1 th data DATA2 - 1 sensed during the read operation of checking the low threshold voltage Vth_low of the source select transistor SST may be temporarily stored in the page buffer.

[0146] In step S153, the memory device may perform a read operation to check a high threshold voltage Vth_high among the threshold voltages of the source selection transistors SST included in the memory block. For example, when the read command is a command based on a multi-level cell (MLC) scheme, the memory device may perform a read operation on the source selection transistor SST by performing a read operation using a third read voltage Vr3, as shown in FIG. Figure 8 The third read voltage Vr3 may be applied to source selection lines commonly coupled to the gates of the source selection transistors SST.

[0147] In step S154 , data sensed during a read operation of checking a high threshold voltage Vth_high of the source select transistor SST may be temporarily stored in the page buffer, after which the temporarily stored data may be flipped in the page buffer and then changed into 2-2 th data DATA2 - 2 .

[0148] In step S155 , in the page buffer, second data DATA2 including 2-1st data DATA2 - 1 and 2-2nd data DATA2 - 2 may be stored.

[0149] Figure 18 is a diagram illustrating a second checking operation according to an embodiment of the present disclosure.

[0150] Reference Figure 18, the second inspection operation is performed as a read operation on the source select transistor SST, so the 2-1st data DATA2-1 and the 2-2nd data DATA2-2 sensed during the read operation can be stored in the first to i-th page buffers PB1 to PBi respectively coupled to the first to i-th bit lines BL1 to BLi. An embodiment of an operation of storing the 2-1st data DATA2-1 and the 2-2nd data DATA2-2 in the first to i-th page buffers PB1 to PBi will be described below.

[0151] 19A to 19D 2 is a diagram illustrating data stored in a page buffer during a second check operation, wherein a first page buffer coupled to a first bit line is shown as an example.

[0152] Reference Figure 19A and Figure 15 In a state where the 1-1 data DATA1-1 and the 1-2 data DATA1-2 are stored in the second latch LT2 and the third latch LT3, when the first read voltage Vr1 is applied to the source select line SSL and then a read operation is performed, the data sensed from the source select transistor SST can be stored in the first latch LT1 through the first bit line BL1 (15). Subsequently, the data stored in the first latch LT1 can be transmitted to the fourth latch LT4 for a subsequent read operation (16). The data transmitted to the fourth latch LT4 can be the data included in the 2-1 data DATA2-1.

[0153] Reference Figure 19B and Figure 15 , when the third read voltage Vr3 is applied to the source select line SSL and then a read operation is performed, the data sensed from the corresponding source select transistor SST may be stored in the first latch LT1 through the first bit line BL1 (17). Subsequently, the data stored in the first latch LT1 may be transmitted to the fifth latch LT5 (18). Thereafter, the first page buffer PB1 may flip the data stored in the fifth latch LT5 in response to the page buffer control signal. The flipped data stored in the fifth latch LT5 may be the data included in the 2-2nd data DATA2-2.

[0154] Reference Figure 19C, when the second check operation is completed, the first page buffer PB1 may transmit the 1-1th data DATA1-1 stored in the second latch LT2 to the j-th latch LTj in response to the page buffer control signal (19), and then may output the 1-1th data DATA1-1 as the first data DATA1. Subsequently, after the first page buffer PB1 transmits the 1-2th data DATA1-2 stored in the third latch LT3 to the j-th latch LTj in response to the page buffer control signal (20), the first page buffer PB1 may output the 1-2th data DATA1-2 as the first data DATA1. The input / output circuit (e.g., Figure 3 The input / output circuit 150 of the memory controller transmits the first data DATA1 output from the first page buffer PB1 to the memory controller.

[0155] Reference Figure 19D , after outputting the first data DATA1, the first page buffer PB1 may transmit the 2-1st data DATA2-1 stored in the fourth latch LT4 to the j-th latch LTj in response to the page buffer control signal (21), and then may output the 2-1st data DATA2-1 as the second data DATA2. Subsequently, after the first page buffer PB1 transmits the 2-2nd data DATA2-2 stored in the fifth latch LT5 to the j-th latch LTj in response to the page buffer control signal (22), the first page buffer PB1 may output the 2-2nd data DATA2-2 as the second data DATA2. The input / output circuit (e.g., Figure 3 The input / output circuit 150 of the memory controller transmits the second data DATA2 output from the first page buffer PB1 to the memory controller.

[0156] Figure 20 is a diagram illustrating a method of operating a memory controller according to an embodiment of the present disclosure.

[0157] Reference Figure 20 When the read operation performed on the memory device MD is completed, the command generator 21 may generate and output the output command CMDo. The memory interface 22 may transmit the output command CMDo received from the command generator 21 to the memory device MD. The memory device MD may sequentially output the first data DATA1 and the second data DATA2 in response to the output command CMDo (see Figure 19C and Figure 19D ).

[0158] The memory interface 22 may receive the first data DATA1 and the second data DATA2 output from the memory device MD, and the memory interface 22 may sequentially transmit the first data DATA1 and the second data DATA2 to the counter 23 .

[0159] The counter 23 may count the number of fail bits included in the first data DATA1 and output a first count value 1VALc, and may count the number of fail bits included in the second data DATA2 and output a second count value 2VALc. For example, when a fail bit is defined as having a value "1" between "0" and "1" included in the first data DATA1 and the second data DATA2, the counter 23 may count the number of bits having a value "1" included in each of the first data DATA1 and the second data DATA2 and output a first count value 1VALc and a second count value 2VALc.

[0160] The comparator 24 can compare the first count value 1VALc and the second count value 2VALc with a reference value, respectively, and can generate and output state information STinfo of the corresponding memory block based on the comparison results. For example, when the first count value 1VALc or the second count value 2VALc is greater than the reference value, the comparator 24 can output state information STinfo indicating a bad state, and when the first count value 1VALc and the second count value 2VALc are less than or equal to the reference value, the comparator 24 can output state information STinfo indicating a normal state. Alternatively, the comparator 24 can generate and output state information STinfo corresponding to various states based on the first count value 1VALc and the second count value 2VALc.

[0161] The central processing unit 25 may update the status of the memory block according to the status information STinfo, and may manage the memory block based on the updated status.

[0162] Figure 21A and 21B are diagrams illustrating various embodiments of a comparator.

[0163] Reference Figure 21A The comparator 24 may compare the first count value 1VALc and the second count value 2VALc with a reference value, respectively, and may output state information STinfo indicating whether the corresponding memory block is in a bad state or a normal state based on the comparison result. For example, when the first count value 1VALc or the second count value 2VALc is greater than the reference value, the comparator 24 may output state information STinfo indicating a bad state, and when the first count value 1VALc and the second count value 2VALc are less than or equal to the reference value, the comparator 24 may output state information STinfo indicating a normal state.

[0164] Reference Figure 21B ,and Figure 21A The comparator 24 shown is different, Figure 21B The illustrated comparator 24 can generate and output status information STinfo corresponding to respective states status 1 to status 8 based on the first count value 1VALc and the second count value 2VALc. For example, the comparator 24 may include a table that classifies the first count value 1VALc and the second count value 2VALc into a plurality of ranges A to D, and a table that includes the states status 1 to status 8 corresponding to the respective ranges. When the first count value 1VALc and the second count value 2VALc are input, the comparator 24 can output status information STinfo that includes both the state corresponding to the range within which the first count value 1VALc falls and the state corresponding to the range within which the second count value 2VALc falls.

[0165] Figure 22 It shows Figure 3 Schematic diagram of an embodiment of a memory block. Figure 22 According to an embodiment, the i-th memory block BLKi may include a plurality of drain select transistor groups DST_GR1 to DST_GR4 and a plurality of source select transistor groups SST_GR1 and SST_GR2. For example, each of the strings ST may include first to fourth drain select transistors DST1 to DST4 and first and second source select transistors SST1 and SST2. The first to fourth drain select transistors DST1 to DST4 may be sequentially coupled between the n-th memory cell Cn and the first to j-th bit lines BL1 to BLj, and the first and second source select transistors SST1 and SST2 may be sequentially coupled between the source line SL and the first memory cell C1.

[0166] The first drain select transistor group DST_GR1 may include a first drain select transistor DST1, and a gate of the first drain select transistor DST1 may be coupled to a first drain select line DSL1. Thus, the first to fourth drain select transistors DST1 to DST4 may form first to fourth drain select transistor groups DST_GR1 to DST_GR4, and the first to fourth drain select transistor groups DST_GR1 to DST_GR4 may be coupled to first to fourth drain select lines DSL1 to DSL4, respectively. Different voltages may be applied to the first to fourth drain select lines DSL1 to DSL4.

[0167] The first source select transistor group SST_GR1 may include a first source select transistor SST1, and a gate of the first source select transistor SST1 may be coupled to a first source select line SSL1. The second source select transistor group SST_GR2 may include a second source select transistor SST2, and a gate of the second source select transistor SST2 may be coupled to a second source select line SSL2. Different voltages may be applied to the first source select line SSL1 and the second source select line SSL2.

[0168] As in Figure 22 In the case of the i-th memory block BLKi shown, when including first to fourth drain select transistors DST1 to DST4 and first and second source select transistors SST1 and SST2 , an inspection operation on the select transistors may be performed for each group.

[0169] For example, when a check operation is initiated, respective read operations for checking the low and high threshold voltages of the first drain select transistor group DST_GR1 can be performed, and the read data can be temporarily stored in different latches of the page buffer. In this way, data read from the first to fourth drain select transistor groups DST_GR1 to DST_GR4 and data read from the first and second source select transistor groups SST_GR1 and SST_GR2 can be stored in the page buffer. The order in which the read operations are performed on the select transistor groups DST_GR1 to DST_GR4 and SST_GR1 and SST_GR2 can be changed depending on the memory device.

[0170] An embodiment of an inspection operation performed on a plurality of selection transistor groups will be described in detail below.

[0171] Figure 23 It is shown in detail including Figure 22 Flowchart of a memory system inspection operation of a memory block.

[0172] Reference Figure 23 , can be similar to the above reference Figure 12 The inspection operation of the plurality of selection transistor groups is performed in a manner described in the embodiment. Figure 12 The description of components that overlap between the described embodiments is repeated.

[0173] In step S201 , a memory controller included in a memory system may generate a read command CMDr and an address ADD, and may transmit the read command CMDr and the address ADD to a memory device.

[0174] The memory device may sequentially perform a first inspection operation S2010 on drain select transistors included in a selected memory block and a second inspection operation S2020 on source select transistors included in the selected memory block in response to a read command CMDr and an address ADD. An embodiment of the first inspection operation S2010 performed on the drain select transistors DST is described in detail below.

[0175] In step S202, the memory device may perform a read operation to check the low threshold voltage Vth_low and the high threshold voltage Vth_high of the first drain select transistor group DST_GR1 included in the selected memory block, and may store the read 1-1th data DATA1-1 in the page buffer. For example, the memory device may store the data read during the read operation of the low threshold voltage Vth_low in the page buffer without change, and may flip the data read during the read operation of the high threshold voltage Vth_high and store the flipped data in the page buffer.

[0176] In step S203, when step S202 is completed, the memory device may perform a read operation to check the low threshold voltage Vth_low and the high threshold voltage Vth_high of the second drain select transistor group DST_GR2 included in the selected memory block, and may store the read 1-2 data DATA1-2 in the page buffer. For example, the memory device may store the data read during the read operation of the low threshold voltage Vth_low in the page buffer without change, and may flip the data read during the read operation of the high threshold voltage Vth_high and store the flipped data in the page buffer.

[0177] In step S204, when step S203 is completed, the memory device may perform a read operation to check the low threshold voltage Vth_low and the high threshold voltage Vth_high of the third drain select transistor group DST_GR3 included in the selected memory block, and may store the read 1-3 data DATA1-3 in the page buffer. For example, the memory device may store the data read during the read operation at the low threshold voltage Vth_low in the page buffer without change, and may flip the data read during the read operation at the high threshold voltage Vth_high and store the flipped data in the page buffer.

[0178] In step S205, when step S204 is completed, the memory device may perform a read operation to check the low threshold voltage Vth_low and the high threshold voltage Vth_high of the fourth drain select transistor group DST_GR4 included in the selected memory block, and may store the read 1-4 data DATA1-4 in the page buffer. For example, the memory device may store the data read during the read operation at the low threshold voltage Vth_low in the page buffer without change, and may flip the data read during the read operation at the high threshold voltage Vth_high and store the flipped data in the page buffer.

[0179] An embodiment of a second inspection operation S2020 performed on the source select transistor SST will be described below.

[0180] In step 206, the memory device may perform a read operation to check the low threshold voltage Vth_low and the high threshold voltage Vth_high of the first source select transistor group SST_GR1 included in the selected memory block, and may store the read 2-1st data DATA2-1 in the page buffer. For example, the memory device may store the data read during the read operation of the low threshold voltage Vth_low in the page buffer without change, and may flip the data read during the read operation of the high threshold voltage Vth_high and store the flipped data in the page buffer.

[0181] In step S207, when step S206 is completed, the memory device may perform a read operation to check the low threshold voltage Vth_low and the high threshold voltage Vth_high of the second source select transistor group SST_GR2 included in the selected memory block, and may store the read 2-2 data DATA2-2 in the page buffer. For example, the memory device may store the data read during the read operation of the low threshold voltage Vth_low in the page buffer without change, and may flip the data read during the read operation of the high threshold voltage Vth_high and store the flipped data in the page buffer.

[0182] In step S208 , when the read operation performed on the drain select transistor DST and the source select transistor SST is completed, the memory controller may transmit an output command CMDo to the memory device.

[0183] In step S209, the memory device may output first data DATA1 and second data DATA2 stored in the page buffer to the memory controller in response to the output command CMDo. The first data DATA1 may include items of data DATA1-1, DATA1-2, DATA1-3, and DATA1-4 stored in the page buffer in step S2010, and the second data DATA2 may include items of data DATA2-1 and DATA2-2 stored in the page buffer in step S2020.

[0184] In step S210 , the memory controller may count the number of fail bits included in the first data DATA1 and the second data DATA2 , and may check the state of the memory block according to the count value.

[0185] Figure 24 is a diagram illustrating a memory card system to which the memory device according to the present disclosure is applied.

[0186] Reference Figure 24 , the memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300. The memory controller 2100 is coupled to the memory device 2200. The memory controller 2100 may access the memory device 2200. For example, the memory controller 2100 may control a program operation, a read operation, or an erase operation of the memory device 2200, or may control background operations of the memory device 2200. The memory controller 2100 may provide an interface between the memory device 2200 and a host. The memory controller 2100 may execute firmware for controlling the memory device 2200. Figure 24 The memory controller 2100 shown may include Figure 2 The memory controller 1200 shown includes means 21 to 25 and can be used, for example, with Figure 3 Memory device 2200 is configured in the same manner as memory device MD shown.

[0187] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) based on a specific communication protocol. In an embodiment, the memory controller 2100 can communicate with the external device through at least one of the following various interface protocols: Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WIFI, Bluetooth, and Non-Volatile Memory Express (NVMe) protocol. In an embodiment, the connector 2300 can be defined by at least one of the various communication protocols described above.

[0188] In an embodiment, the memory device 2200 may be implemented as any of various non-volatile memory devices such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0189] The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, MicroMMC, or eMMC), an SD card (SD, MiniSD, MicroSD, or SDHC), or a Universal Flash Storage (UFS).

[0190] Figure 25 is a diagram illustrating a solid-state drive (SSD) system to which a memory device according to the present disclosure is applied.

[0191] Reference Figure 25 , the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 can exchange signals with the host 3100 through a signal connector 3001 and receive voltage through a power connector 3002. The SSD 3200 may include an SSD controller 3210, a plurality of non-volatile memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240. Figure 3The memory device MD is configured in the same manner as shown Figure 25 Non-volatile memories 3221 to 322n are shown. Figure 25 The SSD controller 3210 shown may include Figure 2 The memory controller 1200 shown includes devices 21 to 25.

[0192] The SSD controller 3210 may control the plurality of non-volatile memories 3221 to 322n in response to signals received from the host 3100. In an embodiment, the signals may be signals based on interfaces between the host 3100 and the SSD 3200. For example, such signals may be signals defined by at least one of various interfaces such as a Universal Serial Bus (USB), a MultiMediaCard (MMC), an Embedded MMC (eMMC), a Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), an Advanced Technology Attachment (ATA), a Serial ATA (SATA), a Parallel ATA (PATA), a Small Computer System Interface (SCSI), an Enhanced Small Disk Interface (ESDI), an Integrated Drive Electronics (IDE), FireWire, a Universal Flash Storage (UFS), WiFi, Bluetooth, and a Non-Volatile Memory Express (NVMe) interface.

[0193] The auxiliary power supply 3230 can be connected to the host 3100 via the power connector 3002. The auxiliary power supply 3230 can be supplied with power from the host 3100 and can be charged. When the power supply from the host 3100 is not smoothly performed, the auxiliary power supply 3230 can supply power to the SSD 3200. In embodiments, the auxiliary power supply 3230 can be located inside the SSD 3200 or outside the SSD 3200. For example, the auxiliary power supply 3230 can be located in the motherboard and can also provide auxiliary power to the SSD 3200.

[0194] The buffer memory 3240 serves as a buffer memory for the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of non-volatile memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the non-volatile memories 3221 to 322n. The buffer memory 3240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, or LPDDR SDRAM, or a non-volatile memory such as FRAM, ReRAM, STT-MRAM, or PRAM.

[0195] According to one or more embodiments, time required to check a state of a memory device may be shortened by reducing time required to check a selection transistor included in the memory device.

[0196] For example, the controllers, processors, devices, managers, components, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features of the embodiments disclosed herein may be implemented in, for example, non-transitory logic that may include hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, devices, managers, components, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may be, for example, any of a variety of integrated circuits including, but not limited to, an application specific integrated circuit, a field programmable gate array, a combination of logic gates, a system on a chip, a microprocessor, or another type of processing or control circuitry.

[0197] When implemented at least in part in software, controllers, processors, devices, managers, components, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, a memory or other storage device for storing, for example, code or instructions to be run by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or those in addition to the elements described herein. Because the algorithms that form the basis of the method (or the operation of a computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operation of the method embodiments can convert the computer, processor, controller, or other signal processing device into a dedicated processor for performing the method described herein.

[0198] Although the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made in the present disclosure without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described exemplary embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0199] In the above embodiments, all or some of the steps may be selectively performed, and all or some of the steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described, and the steps may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples to facilitate understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0200] Meanwhile, exemplary embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these are only for the purpose of illustrating the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments and many variations are possible within the concept and scope of the present disclosure. It should be apparent to those skilled in the art that, in addition to the embodiments of the present disclosure herein, various modifications may be made based on the technical scope of the present disclosure. The embodiments may be combined to form other embodiments.

Claims

1. A memory system comprising: A memory device including a memory block and a peripheral circuit, wherein the memory block includes a selection transistor and a memory cell coupled between a bit line and a source line, and the peripheral circuit performs a program operation or a read operation; as well as Memory controller, The memory controller transmits a program command based on a single-level cell scheme to the memory device to increase a threshold voltage of the selection transistor after an erase operation has been performed on the memory block; and The memory controller transmits a read command to the memory device to perform a checking operation, wherein the checking operation uses a first read voltage and a second read voltage higher than the first read voltage, and wherein the checking operation includes: checking whether the threshold voltage of the selection transistor falls within a range between the first read voltage and the second read voltage, or It is checked whether the threshold voltage is lower than the first read voltage or higher than the second read voltage. 2 . The memory system of claim 1 , wherein the program command based on the single-level cell scheme comprises a command to store one bit of data in one memory cell. 3 . The memory system of claim 1 , wherein the read command is based on a cell scheme higher than the single-level cell scheme and includes a command corresponding to a program scheme of storing two or more bits of data in one memory cell.

4. The memory system according to claim 1 , wherein the first read voltage and the second read voltage are read voltages sequentially used during a read operation based on a cell scheme higher in layer than the single-level cell scheme, and wherein the peripheral circuit further: generating the first read voltage and the second read voltage in response to the read command, storing first data read from the selection transistor using the first read voltage in response to the read command, and Data read from the selection transistor using the second read voltage in response to the read command is inverted, and the inverted data is then stored as second data.

5. The memory system of claim 4 , wherein the peripheral circuit further sets the first data read from the selection transistor having the threshold voltage lower than the first read voltage and the second data read from the selection transistor having the threshold voltage equal to or higher than the second read voltage as fail bits.

6. The memory system of claim 5 , wherein the memory controller further: receiving the first data and the second data from the memory device, and A state of the memory block is checked according to the number of fail bits among the first data and the second data read from the selection transistor.

7. The memory system of claim 6 , wherein the memory controller checks the status by: When the number of failed bits is greater than a reference number of failed bits, the storage block is processed as a bad block, and When the number of fail bits is less than or equal to the reference number of fail bits, the memory block is processed as a normal block. 8 . The memory system according to claim 6 , wherein the memory controller further generates various types of status information of the memory block according to the number of fail bits.

9. The memory system according to claim 1, The peripheral circuit includes: a voltage generator that generates the first read voltage and the second read voltage to be applied to the gate of the selection transistor; as well as a page buffer that stores data read from the select transistor, and The memory device further includes a logic circuit configured to control the peripheral circuit in response to the program command or the read command.

10. The memory system of claim 1 , wherein the memory controller comprises: a command generator that selectively generates the program command based on the single-level cell scheme or the read command based on a cell scheme of a higher level than the single-level cell scheme; a memory interface for transmitting the program command and the read command to the memory device and receiving data output from the memory device; a counter that counts the number of fail bits included in data received by the memory interface and outputs the count value; a comparator that compares the count value with a reference value and outputs state information of the storage block based on a comparison result; as well as The processor processes the storage block as a bad block or a normal block according to the status information.

11. A memory system comprising: A memory device comprising a memory block and a peripheral circuit, wherein the memory block comprises a selection transistor and a memory cell coupled between a bit line and a source line, and the peripheral circuit programs or reads the selection transistor; and a memory controller that transmits a command to the memory device to check a threshold voltage distribution of the selection transistor, wherein the peripheral circuit further stores first data read from the selection transistor using a first read voltage in response to the command, flips data read from the selection transistor using a second read voltage higher than the first read voltage and stores the flipped data as second data, and Wherein, when the first data and the second data are output from the memory device, the memory controller further checks a state of the memory block according to the number of fail bits included in the first data and the second data.

12. The memory system of claim 11 , wherein the peripheral circuit comprises: a voltage generator that generates the first read voltage and the second read voltage to be applied to the gate of the selection transistor in response to a voltage code; a page buffer storing the first data and the second data read from the selection transistor in response to a page buffer control signal; as well as The logic circuit, in response to the command, outputs the voltage code so that the voltage generator generates the first read voltage and the second read voltage, and outputs the page buffer control signal so that the page buffer stores the first data and the second data.

13. The memory system of claim 12, wherein: Each of the page buffers includes a plurality of latches, and Each of the page buffers: storing data read using the first read voltage or the second read voltage in a first latch among the plurality of latches, receiving the data read from the first latch using the first read voltage, and storing the received data as the first data in a second latch among the plurality of latches, receiving the data read from the first latch using the second read voltage, and storing inverted data of the received data as the second data in a third latch among the plurality of latches, and The first data or the second data received from the second latch or the third latch is output to the memory controller through a fourth latch among the plurality of latches.

14. The memory system of claim 11 , wherein the memory controller comprises: A command generator, generating the command; a memory interface that outputs the command to the memory device and receives the first data and the second data output from the memory device; a counter that counts the number of fail bits included in the first data and the second data received by the memory interface and outputs a count value; a comparator that compares the count value with a reference value and outputs state information of the storage block based on a comparison result; as well as The processor processes the storage block as a bad block or a normal block based on the status information. 15 . The memory system according to claim 14 , wherein the command generator outputs a read command as the command to check a state of the selection transistor. 16 . The memory system according to claim 15 , wherein the read command is set as a command based on a multi-level cell scheme for reading two or more bits of data from a memory cell. 17 . The memory system of claim 14 , wherein the fail bit corresponds to the first data or the second data read from a selection transistor having a threshold voltage lower than the first read voltage or a selection transistor having a threshold voltage equal to or higher than the second read voltage.

18. The memory system of claim 14, wherein the comparator: When the count value is greater than the reference value, information indicating a bad block is included in the status information, and When the count value is less than or equal to the reference value, information indicating a normal block is included in the status information.

19. The memory system according to claim 14, wherein the comparator divides the count value into various ranges and outputs the status information having different information items according to the respective ranges.

20. The memory system of claim 14, wherein the processor: storing the state information corresponding to the storage block, and During a subsequent operation to be performed on the memory block, a control signal is output based on the status information.

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