Multi-storage card testing method, device, computer equipment and storage medium

Abstract

The present application belongs to the field of storage technology, and relates to a method, device, computer equipment and storage medium for testing multiple storage cards, the method comprising the steps of: obtaining a write command for writing data and the numbers of multiple storage cards into multiple storage cards, the write command carrying the data and the numbers; parsing the write command, obtaining the data and the numbers, and writing the data into the multiple storage cards according to the numbers; reading the data from every two multiple storage cards with different numbers, putting the read data into a comparison circuit for XOR operation, and judging whether the multiple storage cards are normal according to the XOR operation results. By adopting the present application, by numbering multiple storage cards, data can be written into multiple storage cards at the same time, without relying on manpower, and the test of storage cards can be automatically performed, which saves costs and can improve test efficiency. The test is reliable and easy to implement, and can be generally applied to the test of storage cards.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a testing method, device, computer equipment and storage medium for multiple storage cards. Background Art

[0002] With the development of information processing technology, the demand for storage devices has increased significantly. Small storage devices, such as memory cards, are widely used due to their portability, high data storage capacity and easy access. Based on the increase in demand for memory cards, the importance of memory card testing processes has also increased relatively before memory cards are mass-produced, and further ensure the performance and compatibility of memory cards. Therefore, low-cost and high-performance memory card testing has become an important issue for system manufacturers and designers.

[0003] When testing memory cards in the traditional way, testers need to manually and step by step process the test to ensure the performance of the memory card. For example, the tester needs to manually insert or remove each memory card for testing. In the test process, various different test devices are required to ensure the performance and compatibility of the memory card. It can be seen that the traditional memory card testing process is not only time-consuming but also costly. The principle of testing memory cards in the prior art is to write the same data into multiple memory cards, then read the data out, and verify the consistency between the read data and the written data, so as to operate the memory card.

[0004] This test operation has several characteristics: First, the amount of data is relatively large. For example, when the storage device to be tested is a memory card, if the capacity of the memory card is 256GB, then the test data is 256GB; if the storage device to be tested is a hard disk, if the capacity of the hard disk is 2T, then the test data must be 2T; second, the data to be tested are all written from the host side (computer) to multiple storage devices to be tested. Write--read--data comparison; then write--erase block--read--data comparison. Generally speaking, this kind of test process will be repeated several times to test the stability of the storage data of the storage device. It can be seen that the test process is very long and inefficient. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a method, device, computer equipment and storage medium for testing multiple memory cards to solve the problem that the testing process of multiple memory cards in the prior art is very long and inefficient.

[0006] In order to solve the above technical problems, the present application provides a method for testing multiple memory cards, which adopts the following technical solution and includes the following steps:

[0007] Acquire a write command for writing data and a serial number of the multi-storage card into the multi-storage card, wherein the write command includes the data and the serial number;

[0008] parsing the write command, obtaining the data and the serial number, and writing the data into the multi-storage card according to the serial number;

[0009] The data is read from every two multi-storage cards with different numbers, the read data is stored in a comparison circuit for XOR operation, and whether the two multi-storage cards with different numbers are normal is determined according to the result of the XOR operation.

[0010] Furthermore, before the step of obtaining a write command for writing the data and the serial number of the multi-storage card into the multi-storage card, wherein the write command carries the data and the serial number, the step further includes:

[0011] Sets the rules for writing commands.

[0012] Furthermore, the step of parsing the write command, obtaining the data and the serial number, and writing the data into the multi-storage card according to the serial number specifically includes:

[0013] Parsing the write command to obtain the data and the serial number;

[0014] Cache the acquired data in a cache area;

[0015] The data in the buffer area is written into the multi-storage card according to the number.

[0016] Furthermore, the step of reading the data from every two multi-storage cards with different numbers, putting the read data into a comparison circuit for XOR operation, and judging whether the multi-storage cards are normal according to the XOR operation result specifically includes:

[0017] Group the multiple memory cards in pairs according to their numbers;

[0018] Read the data from every two multi-storage cards with different numbers, and put the read data into a comparison circuit for XOR operation;

[0019] If the XOR operation result is 0, it is determined that the two multi-storage cards with different numbers are normal. If the XOR operation result is 1, it is determined that one of the two multi-storage cards with different numbers is abnormal.

[0020] The group of abnormal multi-memory cards is marked, and then each multi-memory card in the group of abnormal multi-memory cards is XORed with the normal multi-memory cards that have been detected, until the normal and abnormal conditions of all multi-memory cards are detected.

[0021] Furthermore, the rules for setting the write command include:

[0022] Set the first byte of the write command to represent the number of the multi-storage card.

[0023] Furthermore, after the step of reading the data from each two multi-storage cards with different numbers, putting the read data into a comparison circuit for XOR operation, and judging whether the multi-storage cards are normal according to the XOR operation result, the method further includes:

[0024] There are abnormal multiple memory card numbers displayed.

[0025] In order to solve the above technical problems, the present application also provides a test device for multiple memory cards, which adopts the following technical solution, including:

[0026] an acquisition module, used for acquiring a write command for writing data and a serial number of the multi-storage card into the multi-storage card, wherein the write command carries the data and the serial number;

[0027] A writing module, used for parsing the writing command, obtaining the data and the serial number, and writing the data into the multi-storage card according to the serial number;

[0028] The discrimination module is used to read the data from every two multi-storage cards with different numbers, put the read data into the comparison circuit for XOR operation, and judge whether the multi-storage cards are normal according to the XOR operation result.

[0029] Furthermore, the writing module includes:

[0030] A parsing module, used for parsing the write command to obtain the data and the serial number;

[0031] A cache module, used for caching the data into a cache area SRAM;

[0032] The output module is used to write the data into the multi-storage card according to the serial number through the buffer area SRAM.

[0033] In order to solve the above technical problems, the present application also provides a computer device, which adopts the technical solution described below, including a memory and a processor, wherein the memory stores computer-readable instructions, and the processor implements the steps of the above-mentioned multi-memory card testing method when executing the computer-readable instructions.

[0034] In order to solve the above technical problems, the present application also provides a computer-readable storage medium, which adopts the technical solution described below, and stores computer-readable instructions on the computer-readable storage medium. When the computer-readable instructions are executed by the processor, the steps of the above-mentioned multi-memory card testing method are implemented.

[0035] Compared with the prior art, the present application has the following main beneficial effects: by numbering multiple memory cards, data can be written to multiple memory cards at the same time without relying on manpower, and the memory card test can be automatically performed, which saves costs and improves the test efficiency. The test is reliable and easy to implement, and can be widely applied to the testing of memory cards. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the scheme in the present application, a brief introduction is given below to the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 is an exemplary system architecture diagram to which the present application may be applied;

[0038] Figure 2 A flowchart of an embodiment of a method for testing multiple memory cards of the present application;

[0039] Figure 3 It is a test principle diagram of multiple memory cards in the prior art;

[0040] Figure 4 It is a test data transmission timing diagram of multiple memory cards in the prior art;

[0041] Figure 5 is a test data transmission timing diagram of multiple memory cards of the present application;

[0042] Figure 6 This is a schematic diagram of an embodiment of the present application for simultaneously writing data into multiple memory cards;

[0043] Figure 7 is a schematic diagram of another embodiment of the present application for simultaneously writing data into multiple memory cards;

[0044] Figure 8 It is the eight-bit XOR circuit diagram of the present application;

[0045] Fig. 9 is the logic circuit diagram of the present application;

[0046] Fig.10 It is a structural schematic diagram of an embodiment of a test device for multiple memory cards of the present application;

[0047] Fig.11 yes Fig.10 A structural schematic diagram of a specific implementation of the writing module shown;

[0048] Fig.12 It is a structural diagram of an embodiment of a computer device of the present application.

[0049] In the figure, A-NOR gate, B-NAND gate, C-NO gate. DETAILED DESCRIPTION

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "including" and "having" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0051] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0052] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0053] like Figure 1 As shown, the system architecture 100 may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104, and a server 105. The network 104 is used to provide a medium for a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. The network 104 may include various connection types, such as wired, wireless communication links, or optical fiber cables, etc.

[0054] The user can use the first terminal device 101, the second terminal device 102, and the third terminal device 103 to interact with the server 105 through the network 104 to receive or send messages, etc. Various communication client applications can be installed on the first terminal device 101, the second terminal device 102, and the third terminal device 103, such as web browser applications, shopping applications, search applications, instant messaging tools, email clients, social platform software, etc.

[0055] The first terminal device 101, the second terminal device 102, and the third terminal device 103 can be various electronic devices with display screens and supporting web browsing, including but not limited to smart phones, tablet computers, e-book readers, MP3 players (Moving Picture E multi-memory card test perts Group Audio Layer III, Moving Picture Experts Compression Standard Audio Layer 3), MP4 (Moving Picture E multi-memory card test perts Group Audio Layer IV, Moving Picture Experts Compression Standard Audio Layer 4) players, laptop computers and desktop computers, etc.

[0056] The server 105 may be a server that provides various services, for example, a background server that provides support for pages displayed on the first terminal device 101 , the second terminal device 102 , and the third terminal device 103 .

[0057] It should be noted that the test method for multiple memory cards provided in the embodiment of the present application is generally executed by a server / terminal device, and accordingly, the test device for multiple memory cards is generally arranged in the server / terminal device.

[0058] It should be understood that Figure 1 The number of terminal devices, networks and servers in the embodiment is only for illustration. Any number of terminal devices, networks and servers may be provided according to implementation requirements.

[0059] Embodiment 1

[0060] Continue to refer Figure 2 , shows a flow chart of an embodiment of a method for testing multiple memory cards of the present application. The method for testing multiple memory cards comprises the following steps:

[0061] Step S201, obtaining a write command for writing data and the serial number of the multi-storage card into the multi-storage card, wherein the write command includes the data and the serial number.

[0062] Figure 3 This is a test schematic diagram of multiple memory cards in the prior art. Figure 3As shown, the test of multiple memory cards in the prior art usually consists of a test system consisting of a terminal, a USB hub and multiple memory cards. One end of the USB hub is a USB interface, and the other end can be multiple interfaces. The multiple interfaces can be the same or different. The multiple interfaces can include SATA interfaces, USB interfaces, Type-C interfaces, etc. Multiple memory cards are connected through interfaces such as SATA interfaces, USB interfaces, Type-C interfaces, etc. During the test, the tester needs to manually insert or remove each memory card such as multi-memory card 1, multi-memory card 2, multi-memory card 3, and multi-memory card 4 for testing. It can be seen that the test is time-consuming and labor-intensive.

[0063] Figure 4 1 is a test data transmission timing diagram of multiple memory cards in the prior art. Figure 4 As shown, the same data is written from the terminal to multiple storage cards, and the data consists of W1, W2, W3, and W4; at time T1, data W1 is written to card 1, at time T2, data W2 is written to card 1, at time T3, data W3 is written to card 1, and at time T4, data W4 is written to card 1. It can be seen that data storage is performed serially.

[0064] In some optional implementations of this embodiment, in step S201, before obtaining a write command for writing data and the number of the multi-storage card into the multi-storage card, wherein the write command includes the data and the number, the electronic device may further perform the following steps: setting rules for the write command.

[0065] For example, the rule for setting the write command includes: setting the first byte of the write command to represent the serial number of the multi-memory card. Of course, the number of bytes representing the serial number of the multi-memory card can also be defined according to actual needs and the number of multi-memory cards that need to be tested. Here, there is no restriction on the number of bytes of the serial number of the multi-memory card.

[0066] In the present application, multiple memory cards are numbered and the numbering information is written into the multiple memory cards, which facilitates tracking testing.

[0067] In this embodiment, the test method for multiple memory cards is executed on the electronic device (eg Figure 1 The server / terminal device shown in the figure can receive the test request of multiple storage cards through a wired connection or a wireless connection. It should be noted that the above wireless connection method may include but is not limited to 3G / 4G / 5G connection, WiFi connection, Bluetooth connection, WiMA multi-storage card test connection, Zigbee connection, UWB (ultra wideband) connection, and other wireless connection methods currently known or to be developed in the future.

[0068] Step S202, parsing the write command, obtaining the data and the serial number, and writing the data into the multi-storage card according to the serial number.

[0069] In some optional implementations of this embodiment, the step of parsing the write command, obtaining the data and the serial number, and writing the data into the multi-storage card according to the serial number specifically includes:

[0070] Parsing the write command to obtain the data and the serial number;

[0071] Cache the acquired data in a cache area;

[0072] The data in the buffer area is written into the multi-storage card according to the number.

[0073] Figure 5 1 is a test data transmission timing diagram of multiple memory cards of the present application. Figure 5 As shown, data W1, W2, W3 and W4 can be written into memory card 1 at the same time within a time T1, and the control circuit (master control) can also write data W1, W2, W3 and W4 into memory card 2 or / and memory card 3 or / and memory card 4 within a time T1. The numbers of memory card 1, memory card 2, memory card 3, memory card 4, etc. are obtained by parsing the write command. Before writing data W1, W2, W3 and W4 into memory card 2 or / and memory card 3 or / and memory card 4 within a time T1, data W1, W2, W3 and W4 can be cached in a cache area. A data output buffer is set to temporarily store data during writing and a certain space is reserved in the memory area. That is, the storage space of the main memory is used to temporarily store information output from the disk. The purpose is to ease the contradiction of speed mismatch between the CPU and the I / O device. Reduce the interrupt frequency to the CPU and relax the limit on the CPU interrupt response time. Improve the parallelism between the CPU and the I / O device. It can be seen that by adopting this embodiment, data storage is performed in parallel, which can save time.

[0074] Figure 6 This is a schematic diagram of an embodiment of the present application for simultaneously writing data into multiple memory cards. Figure 6 As shown, the terminal issues an instruction to write data into each memory card, and the CPU executes the instruction. The CPU controls the data of the terminal (host end) to be cached in the cache area SRAM first. The main control refers to the main control of the test device, which is soldered to a PCB. One end of the PCB has an interface for connecting to the host end, and the other end has a card slot for inserting multiple memory cards to connect the card to the test board.

[0075] Specifically, when the test starts, the CPU in the main control writes the host data W1, W2, W3 and W4 into the buffer first, and then writes the W1, W2, W3 and W4 data in the buffer into each card, so as to achieve simultaneous writing of data into each card.

[0076] Step S203, reading the data from every two multi-storage cards with different numbers, storing the read data in a comparison circuit for XOR operation, and judging whether the two multi-storage cards with different numbers are normal according to the result of the XOR operation.

[0077] In some optional implementations of this embodiment, the step of reading the data from every two multi-memory cards with different numbers, putting the read data into a comparison circuit for XOR operation, and judging whether the multi-memory cards are normal according to the XOR operation result specifically includes:

[0078] Group the multiple memory cards in pairs according to their numbers;

[0079] Read the data from every two multi-storage cards with different numbers, and put the read data into a comparison circuit for XOR operation;

[0080] If the XOR operation result is 0, it is determined that the two multi-storage cards with different numbers are normal. If the XOR operation result is 1, it is determined that one of the two multi-storage cards with different numbers is abnormal.

[0081] The group of abnormal multi-memory cards is marked, and then each multi-memory card in the group of abnormal multi-memory cards is XORed with the normal multi-memory cards that have been detected, until the normal and abnormal conditions of all multi-memory cards are detected.

[0082] The embodiment of the present application further claims to protect the simultaneous reading of data in each card, so as to determine whether the data can be read and read accurately (compared with the data written by the host, the data has no errors). Based on the data being able to be read and read accurately, the performance of each card is tested.

[0083] Figure 7 This is another schematic diagram of an embodiment of the present invention in which data is simultaneously written into multiple memory cards. Figure 7As shown, based on this, the main control of the embodiment of the present application further includes a comparison circuit, more specifically, an XOR circuit. Since the same data is written into each card, the CPU in the main control controls the reading of data from every two cards, and puts the read data into the comparison circuit for XOR operation. The same data in the two cards is expressed in binary "0" and "1". The XOR circuit is used to perform XOR operation on these data. If the two cards are OK, then the data read from the two cards are XORed, and the result of the XOR operation is "0"; if one of the two cards is NG (Not Good, Failed), then the result of the XOR operation is "1".

[0084] Specifically, since data is read out from the memory card, the data is read out byte by byte. Therefore, data comparison, ie, XOR operation, is byte by byte. The data reading and writing principle of the memory card is to read and write byte by byte.

[0085] Furthermore, since the data is composed of multiple bytes, the comparison circuit, or XOR circuit, is actually a byte XOR accumulation circuit. The data is continuous, and the XOR operation is performed byte by byte, which is actually an accumulation logic. The accumulation hardware can be a register.

[0086] Specifically, as long as a byte XOR operation result is "1", it means that the test result of one card is NG, and the test result of the memory card can be known.

[0087] For example, Figure 7 There are 4 cards in the test. The data in card 1 and card 2 are XORed, and the data in card 3 and card 4 are XORed. If the result of the XOR operation of the data in card 1 and card 2 is "0", and the result of the XOR operation of the data in card 3 and card 4 is "1", it means that at least one of card 3 and card 4 is NG. XOR the data in card 1 and card 3 or the data in card 1 and card 4; or XOR the data in card 2 and card 3 or the data in card 2 and card 4. In this way, all NG cards can be tested, or all cards can be tested.

[0088] XOR of A and B is equivalent to XOR of A and B, that is

[0089]

[0090] The above logical algebraic expression is obtained by transformation.

[0091] The corresponding logic circuit is composed of two NOR gates and one AND gate. For 8-bit binary comparison, 8 groups of the logic circuits can be connected in series.

[0092] Corresponding to a single CMOS XOR gate circuit, it consists of a NOR gate and an AND-NOR gate. For input A and B, first pass through the NOR gate to get Then pass through the AND-OR gate to get the XOR output of A and B.

[0093] Truth table:

[0094] A B NOR gate output AND-OR-NON gate output 0 0 1 0 0 1 0 1 1 0 0 1 1 1 0 0

[0095] The process of testing the memory card is as follows: the external data passes through multiple interfaces such as the USB interface, and is first input into the BULK FIFO of the SRAM for processing. According to the data requirements of the SRAM1235, 2k or others are input at a time, that is, partial input, and then the FIFO data is encoded and decoded according to the read and write requirements of the SRAM1235 (the SRAM needs to pass the XOR circuit data, w / r). After the operation is completed, it is returned to the SRAM and stored again in the USB or other operations as needed. Each write of data will overwrite the previous data of the SRAM FIFO.

[0096] Data comparison example:

[0097] 1001 1100 0011 0001 0101 1110 1011 0111 (mother card 32-bit binary data);

[0098] 9 c 3 1 5 eb 7 (32-bit hexadecimal);

[0099] 1001 1100 0011 0011 0101 1100 1011 0111 (daughter card 32-bit binary data);

[0100] 9 c3 35 cb 7 (hexadecimal);

[0101] It can be seen that errors occur in the 4th and 6th 8 bits.

[0102] XOR comparison result:

[0103] 0000 0000 0000 0010 0000 0010 0000 0000 (binary);

[0104] 0 0 0 2 0 2 0 0 (hexadecimal).

[0105] Figure 8 This is the 8-bit XOR circuit diagram of the present application. Figure 8As shown, it mainly includes two devices, NMOS and PMOS. The source S of PMOS1 is connected to the drain D of PMOS2, and the source of PMOS2 is connected to the gate G of PMOS5, the gate G of NMOS3, the drain D of NMOS2, and the drain D of NMOS1 respectively. PMOS1, PMOS2, NMOS1, and NMOS2 form an NOR gate A. PMOS3, PMOS4, NMOS4, and NMOS5 form an NAND gate B. The drain D of PMOS3 is connected to the drain D of PMOS4, the gate of PMOS4 is connected to the gate of NMOS4, the source of NMOS4 is connected to the drain of NMOS5, and the drain of NMOS4 is connected to the source of PMOS5 and the drain of NMOS3 respectively. PMOS5 and NMOS3 form a NOT gate C. The source of PMOS5 is connected to the drain of NMOS3. For the high level of G pole of NMOS (1), the source and drain of NMOS are turned on, otherwise, for the low level of gate in PMOS, the source and drain of PMOS are turned on. The working principle is: for input a and b, the NOR gate outputs a high level only when a and b are both 1 (high level). For output a and b, the NAND gate outputs 0 (low level) only when a and b are both 1. The NOT gate inverts the input.

[0106] The corresponding logic algebraic expression of the NAND gate and the NAND gate in series is: A and B are NOT or, the output value is inverted (NOT gate) and then ANDed with the NAND gates of A and B (corresponding series connection).

[0107] Fig. 9 It is the logic circuit diagram of this application. Fig. 9 As shown, referring to the algebraic formula A and B are ANDed, and the output value is then ORed with the NOT value of A and B.

[0108] In some optional implementations of this embodiment, after step S203, reading the data from each of two multi-memory cards with different numbers, storing the read data in a comparison circuit for XOR operation, and judging whether the two multi-memory cards with different numbers are normal according to the result of the XOR operation, the step may also include: displaying the number of the multi-memory card with abnormality. By setting a display interface to display the number of the multi-memory card with abnormality, it is convenient for users to know which multi-memory cards need to be retested or repaired, etc., and it is convenient for users to follow up the quality of the multi-memory cards with abnormality.

[0109] By numbering multiple memory cards, data can be written into multiple memory cards at the same time without relying on manpower. The memory card test can be automatically performed, saving costs and improving test efficiency. The test is reliable and easy to implement, and can be widely applied to memory card testing.

[0110] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through computer-readable instructions, and the computer-readable instructions can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the aforementioned storage medium can be a non-volatile storage medium such as a disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0111] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0112] Embodiment 2

[0113] Further references Fig.10 , as a response to the above Figure 2 In order to realize the method shown in the figure, the present application provides an embodiment of a test device for multiple memory cards, and the device embodiment is Figure 2 Corresponding to the method embodiment shown, the device can be specifically applied to various electronic devices.

[0114] like Fig.10 As shown, the multi-memory card testing device 400 described in this embodiment includes: an acquisition module 401, a writing module 402 and a determination module 403. Among them:

[0115] An acquisition module 401 is used to acquire a write command for writing data and a serial number of a multi-storage card into a multi-storage card, wherein the write command includes the data and the serial number;

[0116] A writing module 402, configured to parse the writing command, obtain the data and the serial number, and write the data into the multi-storage card according to the serial number;

[0117] The determination module 403 is used to read the data from every two multi-storage cards with different numbers, store the read data into the comparison circuit for XOR operation, and determine whether the two multi-storage cards with different numbers are normal according to the result of the XOR operation.

[0118] By numbering multiple memory cards, data can be written into multiple memory cards at the same time without relying on manpower. The memory card test can be automatically performed, saving costs and improving test efficiency. The test is reliable and easy to implement, and can be widely applied to memory card testing.

[0119] See also Fig.11 , is a structural diagram of a specific implementation of the writing module 402, the writing module 402 further includes a parsing module 4021, a cache module 4022 and an output module 4023. Among them,

[0120] The parsing module 4021 is used to parse the write command to obtain the data and the serial number;

[0121] The cache module 4022 is used to cache the obtained data into a cache area;

[0122] The output module 4023 is used to write the data in the buffer area into the multi-storage card according to the serial number.

[0123] By setting up a cache module, the speed mismatch between the CPU and I / O devices can be alleviated. The interrupt frequency to the CPU can be reduced, and the limit on the CPU interrupt response time can be relaxed, thus protecting the integrity of the written data.

[0124] Embodiment 3

[0125] To solve the above technical problems, the present application also provides a computer device. Fig.12 , Fig.12 This is a basic structural block diagram of the computer device in this embodiment.

[0126] The computer device 6 includes a memory 61, a processor 62, and a network interface 63 that are interconnected and communicated through a system bus. It should be noted that the figure only shows a computer device 6 having components of a memory 61, a processor 62, and a network interface 63, but it should be understood that it is not required to implement all the components shown, and more or fewer components can be implemented instead. Among them, those skilled in the art can understand that the computer device here is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to a microprocessor, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital processor (DSP), an embedded device, etc.

[0127] The computer device may be a desktop computer, a notebook, a PDA, a cloud server, etc. The computer device may interact with the user through a keyboard, a mouse, a remote controller, a touch pad, or a voice control device.

[0128] The memory 61 includes at least one type of readable storage medium, and the readable storage medium includes flash memory, hard disk, multi-memory card, card-type memory (for example, test memory of SD or D multi-memory card, etc.), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, disk, optical disk, etc. In some embodiments, the memory 61 can be an internal storage unit of the computer device 6, such as a hard disk or memory of the computer device 6. In other embodiments, the memory 61 can also be an external storage device of the computer device 6, such as a plug-in hard disk equipped on the computer device 6, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. Of course, the memory 61 can also include both the internal storage unit of the computer device 6 and its external storage device. In this embodiment, the memory 61 is generally used to store the operating system and various application software installed on the computer device 6, such as computer-readable instructions of the test method of the multi-memory card, etc. In addition, the memory 61 can also be used to temporarily store various types of data that have been output or are to be output.

[0129] The processor 62 may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chips in some embodiments. The processor 62 is generally used to control the overall operation of the computer device 6. In this embodiment, the processor 62 is used to run computer-readable instructions stored in the memory 61 or process data, such as computer-readable instructions for running the test method of the multi-memory card.

[0130] The network interface 63 may include a wireless network interface or a wired network interface. The network interface 63 is generally used to establish a communication connection between the computer device 6 and other electronic devices.

[0131] By numbering multiple memory cards, data can be written into multiple memory cards at the same time without relying on manpower. The memory card test can be automatically performed, saving costs and improving test efficiency. The test is reliable and easy to implement, and can be widely applied to memory card testing.

[0132] Embodiment 4

[0133] The present application also provides another embodiment, namely, providing a computer-readable storage medium, wherein the computer-readable storage medium stores computer-readable instructions, and the computer-readable instructions can be executed by at least one processor to enable the at least one processor to perform the steps of the multi-memory card testing method as described above.

[0134] By numbering multiple memory cards, data can be written into multiple memory cards at the same time without relying on manpower. The memory card test can be automatically performed, saving costs and improving test efficiency. The test is reliable and easy to implement, and can be widely applied to memory card testing.

[0135] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0136] Obviously, the embodiments described above are only some embodiments of the present application, rather than all embodiments. The preferred embodiments of the present application are given in the accompanying drawings, but they do not limit the patent scope of the present application. The present application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. Although the present application is described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions recorded in the aforementioned specific implementation methods, or to perform equivalent replacement of some of the technical features therein. Any equivalent structure made using the contents of the specification and drawings of this application, directly or indirectly used in other related technical fields, is similarly within the scope of patent protection of this application.

Claims

1. A method for testing multiple memory cards, characterized in that: The steps include: Setting a rule for a write command, and setting the first byte of the write command to represent the number of the multiple memory cards; Acquire a write command for writing data and a serial number of the multi-storage card into the multi-storage card, wherein the write command includes the data and the serial number; parsing the write command, obtaining the data and the serial number, and writing the data into the multi-storage card according to the serial number; The data is read from every two multi-memory cards with different numbers, the read data is stored in a comparison circuit for XOR operation, and whether the two multi-memory cards with different numbers are normal is determined according to the result of the XOR operation, wherein the steps of reading the data from every two multi-memory cards with different numbers, storing the read data in a comparison circuit for XOR operation, and determining whether the multi-memory cards are normal according to the result of the XOR operation specifically include: Group the multiple memory cards in pairs according to their numbers; Read the data from every two multi-storage cards with different numbers, and put the read data into a comparison circuit for XOR operation; If the XOR operation result is 0, it is determined that the two multi-storage cards with different numbers are normal. If the XOR operation result is 1, it is determined that one of the two multi-storage cards with different numbers is abnormal. The group of abnormal multi-memory cards is marked, and then each multi-memory card in the group of abnormal multi-memory cards is XORed with the normal multi-memory cards that have been detected, until the normal and abnormal conditions of all multi-memory cards are detected.

2. The method for testing multiple memory cards according to claim 1, characterized in that: The step of parsing the write command, obtaining the data and the serial number, and writing the data into the multi-memory card according to the serial number specifically includes: Parsing the write command to obtain the data and the serial number; Cache the acquired data in a cache area; The data in the buffer area is written into the multi-storage card according to the number.

3. The method for testing multiple memory cards according to claim 1 or 2, characterized in that: After the step of reading the data from every two multi-memory cards with different numbers, putting the read data into a comparison circuit for XOR operation, and judging whether the multi-memory cards are normal according to the XOR operation result, the following step is also included: There are abnormal multiple memory card numbers displayed.

4. A test device for multiple memory cards, characterized in that: include: an acquisition module, configured to set a rule for a write command, and to set the first byte of the write command to represent the number of the multi-memory card, and to acquire a write command for writing data and the number of the multi-memory card into the multi-memory card, wherein the write command includes the data and the number; A writing module, used for parsing the writing command, obtaining the data and the serial number, and writing the data into the multi-storage card according to the serial number; The discrimination module is used for reading the data from every two multi-storage cards with different numbers, storing the read data in a comparison circuit for XOR operation, and judging whether the two multi-storage cards with different numbers are normal according to the result of the XOR operation, wherein the operations of reading the data from every two multi-storage cards with different numbers, storing the read data in a comparison circuit for XOR operation, and judging whether the multi-storage cards are normal according to the result of the XOR operation specifically include: grouping the multi-storage cards in pairs according to the numbers of the multi-storage cards; reading the data from every two multi-storage cards with different numbers, storing the read data in a comparison circuit for XOR operation; if the result of the XOR operation is 0, judging that the two multi-storage cards with different numbers are normal, and if the result of the XOR operation is 1, judging that one of the two multi-storage cards with different numbers is abnormal; marking the group of the multi-storage cards with abnormalities, and then performing XOR operation on each multi-storage card in the group of the multi-storage cards with abnormalities and the normal multi-storage card that has been detected, until the normal and abnormal conditions of all the multi-storage cards are detected.

5. The test device for multiple memory cards according to claim 4, characterized in that: The writing module comprises: A parsing module, used for parsing the write command to obtain the data and the serial number; A cache module, used for caching the obtained data into a cache area; The output module is used to write the data in the buffer area into the multi-storage card according to the number.

6. A computer device, comprising a memory and a processor, wherein the memory stores computer-readable instructions, and the processor implements the steps of the multi-memory card testing method according to any one of claims 1 to 3 when executing the computer-readable instructions.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, implement the steps of the method for testing multiple memory cards according to any one of claims 1 to 3.

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