Method for manufacturing active component substrate

Abstract

The present invention discloses a method for manufacturing an active component substrate, comprising forming a blind hole in the substrate; forming a first conductive pattern and an active component on a first surface of the substrate, wherein the first conductive pattern overlaps the blind hole; after forming the first conductive pattern and the active component, performing an etching process on the substrate to form a through hole penetrating the substrate at the position of the blind hole; filling a conductive material into the through hole to form a conductive hole, wherein the conductive hole is electrically connected to the first conductive pattern; forming a second conductive pattern on a second surface of the substrate, wherein the second conductive pattern is electrically connected to the first conductive pattern through the conductive hole.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing an active component substrate, and in particular to a method for manufacturing an active component substrate having a through hole in the substrate. Background Art

[0002] At present, in order to reduce the size of the frame of the display panel, the chip on film (COF) technology is usually used. The thin film flip chip packaging technology is a technology for packaging chips on a flexible printed circuit board. The flexible printed circuit board can be bent from the front of the display panel to the back of the display panel, so that the chip can be set on the back of the display panel. Therefore, the display panel can have the advantage of a narrow frame. However, even if the flexible printed circuit board is bent from the front of the display panel to the back of the display panel, the flexible printed circuit board will still protrude from the side of the glass substrate of the display panel. Summary of the invention

[0003] The invention provides a method for manufacturing an active component substrate, which can improve the problem of expansion of conductive holes of the substrate.

[0004] At least one embodiment of the present invention provides a method for manufacturing an active component substrate, comprising forming a blind hole in the substrate; forming a first conductive pattern and an active component on a first surface of the substrate, wherein the first conductive pattern overlaps the blind hole; after forming the first conductive pattern and the active component, performing an etching process on the substrate to form a through hole penetrating the substrate at the position of the blind hole; filling the through hole with a conductive material to form a conductive hole, wherein the conductive hole is electrically connected to the first conductive pattern; forming a second conductive pattern on a second surface of the substrate, wherein the second conductive pattern is electrically connected to the first conductive pattern through the conductive hole.

[0005] Based on the above, the conductive via is formed after the active element is formed, so the influence of the manufacturing process of the active element on the conductive via can be avoided, thereby improving the problem of the conductive via deformation causing the substrate to crack. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1A to 1L is a cross-sectional schematic diagram of a method for manufacturing an active component substrate according to an embodiment of the present invention;

[0007] Figure 2 is a schematic top view of an active component substrate according to an embodiment of the present invention;

[0008] 3A to 3H is a cross-sectional schematic diagram of a method for manufacturing an active component substrate according to an embodiment of the present invention;

[0009] Figure 4is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention;

[0010] Figure 5 is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention;

[0011] Figure 6 is a cross-sectional schematic diagram of a spliced ​​display device according to an embodiment of the present invention;

[0012] Figure 7 is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention;

[0013] Figure 8 is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention;

[0014] Fig. 9 is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention;

[0015] Fig.10 It is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention.

[0016] Explanation of symbols

[0017] 10, 10a, 10b, 10c, 10d, 10e, 10f: Active component substrate

[0018] 100:Substrate

[0019] 102: Blind hole

[0020] 104:Through hole

[0021] 106,106c,106d,106e,106f: conductive holes

[0022] 110: first buffer layer

[0023] 120: semiconductor material layer

[0024] 120': semiconductor channel layer

[0025] 130: Gate insulation layer

[0026] 142: Gate

[0027] 144: first conductive pattern

[0028] 150: Dielectric layer

[0029] 162: Source

[0030] 164: Drain

[0031] 170: Flat layer

[0032] 182: First pad

[0033] 184: Second pad

[0034] 190: Protective layer

[0035] 210: Second buffer layer

[0036] 220: second conductive pattern

[0037] 300: Conductive material

[0038] 400: Light Emitting Diode

[0039] 402,404: Electrode

[0040] 500: Circuit board

[0041] 600: Encapsulation layer

[0042] AA: Display area

[0043] D1: Depth

[0044] E1, E2: Production process

[0045] S1: Side 1

[0046] S2: Side 2

[0047] TFT: Active Components

[0048] T1: Thickness

[0049] W1,W2: Width DETAILED DESCRIPTION

[0050] Figures 1A to 1L It is a cross-sectional schematic diagram of a method for manufacturing an active device substrate according to an embodiment of the present invention.

[0051] Please refer to Figure 1A , an etching process E1 is performed to form a blind hole 102 in the substrate 100. In this embodiment, the substrate 100 includes a first surface S1 and a second surface S2 opposite to the first surface S1, and the blind hole 102 is formed on the second surface S2 of the substrate 100. The blind hole 102 does not penetrate the substrate 100.

[0052] In some embodiments, the substrate 100 includes glass, quartz, organic polymer or other applicable materials, and the method of forming the blind hole 102 on the substrate 100 includes laser or other suitable methods.

[0053] In some embodiments, the thickness T1 of the substrate 100 is 100 micrometers to 600 micrometers. The depth D1 of the blind hole 102 is more than half the thickness of the substrate. The width W1 of the blind hole 102 is 10 micrometers to 300 micrometers.

[0054] Please refer to Figure 1B , forming a first buffer layer 110 on the first surface S1 of the substrate 100. In some embodiments, after forming the blind hole 102, the substrate 100 is turned over, and then the first buffer layer 110 is formed on the first surface S1 of the substrate 100. In this embodiment, the first buffer layer 110 covers the first surface S1 of the substrate 100, and the first buffer layer 110 overlaps the blind hole 102. In some embodiments, the material of the first buffer layer 110 includes silicon oxide, silicon nitride, silicon oxynitride, organic material or other suitable materials.

[0055] Please refer to Figure 1C to Figure 1E After forming the blind hole 102 , the first conductive pattern 144 and the active device TFT are formed on the first surface S1 of the substrate 100 . In this embodiment, the first conductive pattern 144 and the active device TFT are formed on the first buffer 110 .

[0056] Please refer to Figure 1C , a semiconductor material layer 120 is formed on the first surface S1 of the substrate 100 .

[0057] Please refer to Figure 1D , patterning the semiconductor material layer 120 to form a semiconductor channel layer 120' on the first surface S1 of the substrate 100. In some embodiments, the semiconductor channel layer 120' includes, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, oxide semiconductor material (for example: indium zinc oxide, indium gallium zinc oxide or other suitable materials, or a combination of the above), or other suitable materials or a combination of the above materials.

[0058] Please refer to Figure 1E , forming a gate insulating layer 130 on the semiconductor channel layer 120'. In this embodiment, the gate insulating layer 130 covers the entire surface of the first buffer layer 110 and overlaps the blind hole 102, but the present invention is not limited thereto. In other embodiments, the gate insulating layer 130 is patterned and does not overlap the blind hole 102.

[0059] The gate 142 and the first conductive pattern 144 are formed on the gate insulating layer 130. The gate 142 overlaps the semiconductor channel layer 120'. The first conductive pattern 144 overlaps the blind hole 102. In some embodiments, the gate 142 and the first conductive pattern 144 belong to the same conductive layer and are formed by the same patterning process.

[0060] In some embodiments, the gate 142 and the first conductive pattern 144 each include a single layer or a multi-layer structure. The gate 142 and the first conductive pattern 144 are, for example, metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, their alloys, their metal oxides, their metal nitrides, or their combinations or other conductive materials.

[0061] A dielectric layer 150 is formed on the gate 142 and the first conductive pattern 144. A source 162 and a drain 164 are formed on the dielectric layer 150. The source 162 and the drain 164 are electrically connected to the semiconductor channel layer 120'. At this point, the active element TFT is substantially completed. In the present embodiment, the active element TFT includes the semiconductor channel layer 120', the gate 142, the source 162 and the drain 164. The first conductive pattern 144 is selectively electrically connected to the active element TFT. For example, the first conductive pattern 144 is electrically connected to the gate 142 or the source 162 of the active element TFT, but the present invention is not limited thereto.

[0062] In this embodiment, the active device TFT is a top-gate thin film transistor, but the present invention is not limited thereto. In other embodiments, the active device TFT is a bottom-gate thin film transistor, a dual-gate thin film transistor or other types of thin film transistors.

[0063] In some embodiments, the semiconductor channel layer 120 ′ of the active device TFT includes low temperature polysilicon (LTPS), and the method of forming the active device TFT includes a manufacturing process at a temperature of 200 degrees Celsius to 600 degrees Celsius, but the present invention is not limited thereto.

[0064] A planarization layer 170 is formed on the active device TFT and the dielectric layer 150. A first pad 182 and a second pad 184 are formed on the planarization layer 170. In this embodiment, the second pad 184 is electrically connected to the drain 164 of the active device TFT.

[0065] A protection layer 190 is formed on the planar layer 170, the first pad 182, and the second pad 184. In some embodiments, the protection layer 190 is a strippable adhesive or a passivation layer.

[0066] Please refer to Figure 1F , flip the substrate 100. Form a second buffer layer 210 on the second surface S2 of the substrate 100. The second buffer layer 210 covers the blind hole 102. In some embodiments, the second buffer layer 210 is partially filled in the blind hole 102. In some embodiments, the material of the second buffer layer 210 includes silicon oxide, silicon nitride, silicon oxynitride, organic material or other suitable materials.

[0067] Please refer to Figure 1G , performing the manufacturing process E2 to form a through hole 104 penetrating the substrate 100 at the position of the blind hole 102. In the present embodiment, the through hole 104 also penetrates the first buffer layer 110, the gate insulating layer 130 and the second buffer layer 210. In the present embodiment, the manufacturing process E2 stops at the first conductive pattern 144. In the present embodiment, the manufacturing process E2 includes laser or other physical drilling. In some embodiments, the width W2 of the through hole 104 is 100 microns to 300 microns. In the present embodiment, the width W2 of the through hole 104 is greater than or equal to the width of the blind hole, but the present invention is not limited thereto. In other embodiments, the width W2 of the through hole 104 is less than or equal to the width of the blind hole. In the present embodiment, the manufacturing process E2 is performed from the second surface S2 of the substrate 100.

[0068] Please refer to Figure 1H , fill the conductive material 300 in the through hole 104 to form the conductive hole 106. The conductive hole 106 is electrically connected to the first conductive pattern 144. In some embodiments, the method of filling the conductive material 300 in the through hole 104 includes chemical plating, conductive paste coating or other suitable manufacturing processes. In some embodiments, the conductive material 300 includes pure metal, alloy or other conductive material. In some embodiments, the conductive material 300 includes silver conductive paste, and after filling the conductive material 300 in the through hole 104, the conductive material 300 is cured.

[0069] Please refer to Fig. 1I , forming the second conductive pattern 220 on the second surface S2 of the substrate 100. In this embodiment, the second conductive pattern 220 is formed on the second buffer layer 210. The second conductive pattern 220 is electrically connected to the first conductive pattern 144 through the conductive via 106.

[0070] The second conductive pattern 220 is a single-layer or multi-layer structure. In some embodiments, the second conductive pattern 220 is, for example, a metal such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, or the like, an alloy thereof, a metal oxide thereof, a metal nitride thereof, or a combination thereof or other conductive materials.

[0071] Please refer to Figure 1J , flip the substrate 100. Remove the protective layer 190. Provide a light emitting diode 400 on the first surface S1 of the substrate 100. In this embodiment, the light emitting diode 400 is moved from the growth substrate or the intermediate substrate to the first surface S1 of the substrate 100 by mass transfer technology. The electrodes 402 and 404 of the light emitting diode 400 are electrically connected to the first pad 182 and the second pad 184 respectively. In this embodiment, the light emitting diode 400 is electrically connected to the drain 164 of the active element TFT. In some embodiments, the light emitting diode 400 is a micro light emitting diode.

[0072] Please refer to Figure 1K , a circuit board 500 is provided on the second surface S2 of the substrate 100. The circuit board 500 is electrically connected to the second conductive pattern 220. In some embodiments, the circuit board 500 includes a thin film flip chip package.

[0073] In some embodiments, since the circuit board 500 does not extend beyond the side surface of the substrate 100 , the active component substrate can have the advantage of a narrow frame.

[0074] Please refer to Figure 1L , a packaging layer 600 is formed on the first surface S1 of the substrate 100. The packaging layer 600 covers the light emitting diode 400. At this point, the active device substrate 10 is substantially completed. In this embodiment, the packaging layer 600 also covers the side surface of the substrate 100, but the present invention is not limited thereto.

[0075] In this embodiment, the conductive via 106 is formed after the active element TFT is formed, so that the adverse effects of the heat treatment process for forming the active element TFT on the conductive via 106 can be avoided. Specifically, this embodiment avoids the problem of the conductive via 106 expanding due to heat caused by the heat treatment process used to manufacture the circuit and active element located on the first surface S1 of the substrate 100, and further avoids the problem of the conductive via 106 expanding and causing damage to the substrate 100. In some embodiments, the temperature of the manufacturing process after the conductive via 106 is formed is less than 300 degrees Celsius, for example 230 degrees Celsius.

[0076] Figure 2 is a schematic top view of an active device substrate 10 according to an embodiment of the present invention, wherein Figure 2 The substrate 100 , the conductive via 106 and the light emitting diode 400 are shown, and other elements are omitted.

[0077] Please refer to Figure 2 In this embodiment, a plurality of light emitting diodes 400 are disposed in the display area AA of the active device substrate 10. A plurality of conductive holes 106 are disposed between the display area AA and the edge of the substrate 100. In some embodiments, the positions of the conductive holes 106 can be adjusted according to actual needs.

[0078] 3A to 3H is a cross-sectional schematic diagram of a method for manufacturing an active device substrate according to an embodiment of the present invention. It must be noted here that 3A to 3H The implementation examples are used Figures 1A to 2 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0079] Please refer to Figure 3A In the present embodiment, an etching process E1 is performed to form a blind hole 102 on the first surface S1 of the substrate 100 .

[0080] Please refer to Figure 3B , a first buffer layer 110 is formed on the first surface S1 of the substrate 100. The first buffer layer 110 covers the blind hole 102. In this embodiment, the first buffer layer 110 is partially filled into the blind hole 102, but the present invention is not limited thereto.

[0081] Please refer to FIG. 3C to FIG. 3E After forming the blind hole 102 , the first conductive pattern 144 and the active device TFT are formed on the first surface S1 of the substrate 100 . In this embodiment, the first conductive pattern 144 and the active device TFT are formed on the first buffer 110 .

[0082] Please refer to Figure 3C , a semiconductor material layer 120 is formed on the first surface S1 of the substrate 100 .

[0083] Please refer to Figure 3D , patterning the semiconductor material layer 120 to form a semiconductor channel layer 120 ′ on the first surface S1 of the substrate 100 .

[0084] Please refer to Figure 3E , forming a gate insulating layer 130 on the semiconductor channel layer 120'. In this embodiment, the gate insulating layer 130 covers the entire surface of the first buffer layer 110 and overlaps the blind hole 102, but the present invention is not limited thereto. In other embodiments, the gate insulating layer 130 is patterned and does not overlap the blind hole 102.

[0085] A gate 142 and a first conductive pattern 144 are formed on the gate insulating layer 130 . The gate 142 overlaps the semiconductor channel layer 120 ′. The first conductive pattern 144 overlaps the blind hole 102 .

[0086] A dielectric layer 150 is formed on the gate electrode 142 and the first conductive pattern 144. A source electrode 162 and a drain electrode 164 are formed on the dielectric layer 150. The source electrode 162 and the drain electrode 164 are electrically connected to the semiconductor channel layer 120'. At this point, the active device TFT is substantially completed. In this embodiment, the active device TFT includes the semiconductor channel layer 120', the gate electrode 142, the source electrode 162 and the drain electrode 164.

[0087] In this embodiment, the active device TFT is a top-gate thin film transistor, but the present invention is not limited thereto. In other embodiments, the active device TFT is a bottom-gate thin film transistor, a dual-gate thin film transistor or other types of thin film transistors.

[0088] A planarization layer 170 is formed on the active device TFT and the dielectric layer 150. A first pad 182 and a second pad 184 are formed on the planarization layer 170. In this embodiment, the second pad 184 is electrically connected to the drain 164 of the active device TFT.

[0089] A protection layer 190 is formed on the planar layer 170 , the first pad 182 , and the second pad 184 .

[0090] Please refer to Figure 3F , turn over the substrate 100 . Form a second buffer layer 210 on the second surface S2 of the substrate 100 . In this embodiment, the second buffer layer 210 overlaps the blind hole 102 .

[0091] Please refer to Figure 3G , the manufacturing process E2 is performed to form a through hole 104 penetrating the substrate 100 at the position of the blind hole. In the present embodiment, the through hole 104 also penetrates the first buffer layer 110, the gate insulating layer 130 and the second buffer layer 210. In the present embodiment, the manufacturing process E2 stops at the first conductive pattern 144. In the present embodiment, the manufacturing process E2 includes laser or other physical drilling. In the present embodiment, the manufacturing process E2 is performed from the second surface S2 of the substrate 100.

[0092] In this embodiment, the width W2 of the through hole 104 is greater than or equal to the width of the blind hole, but the present invention is not limited thereto. In other embodiments, the width W2 of the through hole 104 is less than or equal to the width of the blind hole.

[0093] Please refer to Figure 3H , fill the conductive material 300 in the through hole 104 to form the conductive hole 106. The conductive hole 106 is electrically connected to the first conductive pattern 144. In some embodiments, the method of filling the conductive material 300 in the through hole 104 includes chemical plating, conductive paste coating or other suitable manufacturing processes. In some embodiments, the conductive material 300 includes pure metal, alloy or other conductive material. In some embodiments, the conductive material 300 includes silver conductive paste, and after filling the conductive material 300 in the through hole 104, the conductive material 300 is cured.

[0094] exist Figure 3H After the steps, execute Figure 1I to Figure 1L For details, refer to the previous paragraphs.

[0095] Figure 4 is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention. It must be noted here that Figure 4 The implementation examples are used Figures 1A to 2The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0096] Figure 4 The active device substrate 10a and Figure 1L The main difference between the active device substrate 10 and the active device substrate 10a is that the active device TFT of the active device substrate 10a is a bottom gate thin film transistor, but the present invention is not limited thereto. In other embodiments, the active device TFT is a top gate thin film transistor.

[0097] Please refer to Figure 4 In this embodiment, the first conductive pattern 144 and the gate 142 are formed on the first surface S1 of the substrate 100 . In this embodiment, the first conductive pattern 144 and the gate 142 are formed on the first buffer layer 110 .

[0098] The gate insulating layer 130 is formed on the gate 142 and the first conductive pattern 144 . The gate 142 and the first conductive pattern 144 are located between the gate insulating layer 130 and the first buffer layer 110 .

[0099] A semiconductor channel layer 120 ′ is formed on the gate insulating layer 130 . The semiconductor channel layer 120 ′ overlaps the gate 142 .

[0100] A source 162 and a drain 164 are formed on the semiconductor channel layer 120 ′.

[0101] A dielectric layer 150 is formed on the source 162 and the drain 164 .

[0102] The first pad 182 and the second pad 184 are formed on the dielectric layer 150. The light emitting diode 400 is electrically connected to the first pad 182 and the second pad 184.

[0103] The encapsulation layer 600 is formed on the first surface S1 of the substrate 100 . The encapsulation layer 600 covers the light emitting diode 400 .

[0104] In this embodiment, the conductive via 106 penetrates the substrate 100 , the first buffer layer 110 and the second buffer layer 210 .

[0105] Figure 5 is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention. It must be noted here that Figure 5 The implementation examples are used Figure 4The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0106] Figure 5 The active component substrate 10b and Figure 4 The main differences of the active device substrate 10a are: Figure 4 The first conductive pattern 144 and the gate 142 of the active device substrate 10a belong to the same film layer. Figure 5 The first conductive pattern 166 , the source 162 , and the drain 164 of the active device substrate 10 b belong to the same film layer.

[0107] In this embodiment, the conductive via 106 penetrates the substrate 100 , the first buffer layer 110 , the second buffer layer 210 , and the gate insulating layer 130 .

[0108] Figure 6 is a cross-sectional schematic diagram of a spliced ​​display device according to an embodiment of the present invention. It must be noted here that Figure 6 The implementation examples are used Figure 1L to Figure 2 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0109] Please refer to Figure 6 In this embodiment, a plurality of active component substrates 10 are spliced ​​together. Since the circuit board 500 is not disposed on the side of the substrate 100, the distance between adjacent active component substrates 10 can be reduced.

[0110] Figure 7 is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention. It must be noted here that Figure 7 The implementation examples are used Figure 1L to Figure 2 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0111] Figure 7 The active device substrate 10c and Figure 1L The difference between the active device substrate 10 and the active device substrate 10 is that the conductive hole 106c of the active device substrate 10c has a cross-sectional shape that is narrow at the top and wide at the bottom. For example, the conductive hole 106c is conical, and the cross-sectional shape of the conductive hole 106c is trapezoidal.

[0112] In this embodiment, the manufacturing process for forming the blind hole 102 (eg Figure 1A ) and production process E2 (such as Figure 1G ) are respectively performed from the same side of the substrate 100 (for example, both from the second side S2), and the width of the conductive hole 106c near the first conductive pattern 144 is smaller than the width of the conductive hole 106c near the second conductive pattern 220. In other words, the conductive hole 106c has different widths.

[0113] Figure 8 is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention. It must be noted here that Figure 8 The implementation examples are used Figure 7 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0114] Figure 8 The active device substrate 10d and Figure 7 The difference between the active component substrate 10c and the active component substrate 10d is that the width of the conductive hole 106d of the active component substrate 10d does not change in a gradual manner.

[0115] In this embodiment, the manufacturing process for forming the blind hole 102 (eg Figure 1A ) and production process E2 (such as Figure 1G ) are respectively performed from the same side of the substrate 100 (for example, both from the second side S2), and the width of the conductive hole 106d near the first conductive pattern 144 is smaller than the width of the conductive hole 106d near the second conductive pattern 220. In other words, the conductive hole 106d has different widths.

[0116] Fig. 9 is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention. It must be noted here that Fig. 9 The implementation examples are used 3A to 3H as well as Figure 1I to Figure 1L The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0117] Fig. 9 The active device substrate 10e and Figure 1L The difference between the active device substrate 10 and the active device substrate 10 is that the conductive hole 106e of the active device substrate 10c has a cross-sectional shape that is narrow at the bottom and wide at the top. For example, the conductive hole 106c is conical, and the cross-sectional shape of the conductive hole 106c is trapezoidal.

[0118] In this embodiment, the manufacturing process for forming the blind hole 102 (eg Figure 3A ) and production process E2 (such as Figure 3G ) are respectively performed from different sides of the substrate 100 (for example, the blind hole 102 is from the first side S1, and the manufacturing process E2 is from the second side S2), and the width of the conductive hole 106e near the first conductive pattern 144 is greater than the width of the conductive hole 106c near the second conductive pattern 220. In other words, the conductive hole 106c has different widths.

[0119] Fig.10 is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention. It must be noted here that Fig.10 The implementation examples are used Fig. 9 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0120] Fig.10 The active device substrate 10f and Fig. 9 The difference between the active component substrate 10e and the active component substrate 10f is that the width of the conductive hole 106f of the active component substrate 10f does not change in a gradual manner.

[0121] In this embodiment, the manufacturing process for forming the blind hole 102 (eg Figure 3A ) and production process E2 (such as Figure 3G ) are respectively performed from different sides of the substrate 100 (for example, the blind hole 102 is from the first side S1, and the manufacturing process E2 is from the second side S2), and the width of the conductive hole 106f near the first conductive pattern 144 is greater than the width of the conductive hole 106f near the second conductive pattern 220. In other words, the conductive hole 106f has different widths.

Claims

1. A method for manufacturing an active component substrate, comprising: forming a blind hole in the substrate; forming a first conductive pattern and an active element on the first surface of the substrate, wherein the first conductive pattern overlaps the blind hole; After forming the first conductive pattern and the active element, performing an etching process on the substrate to form a through hole penetrating the substrate at the position of the blind hole; Filling a conductive material into the through hole to form a conductive hole, wherein the conductive hole is electrically connected to the first conductive pattern; and forming a second conductive pattern on the second surface of the substrate, wherein the second conductive pattern is electrically connected to the first conductive pattern through the conductive hole, The step of forming the first conductive pattern and the active element on the first surface of the substrate includes: forming a semiconductor channel layer on the first surface of the substrate; forming a gate insulating layer on the semiconductor channel layer; forming a gate and the first conductive pattern on the gate insulating layer, wherein the gate overlaps the semiconductor channel layer; forming a dielectric layer on the gate and the first conductive pattern; and A source and a drain are formed on the dielectric layer and electrically connected to the semiconductor channel layer.

2. The manufacturing method according to claim 1, further comprising: forming the blind hole on the second surface of the substrate; forming a first buffer layer on the first surface of the substrate, wherein the first buffer layer overlaps the blind hole; forming the first conductive pattern and the active element on the first buffer layer; and The etching process is performed to form the through hole penetrating the substrate and the first buffer layer at the position of the blind hole.

3. The manufacturing method according to claim 2, further comprising: forming a second buffer layer on the second surface of the substrate, wherein the second buffer layer covers the blind hole; as well as The etching process is performed to form the through hole penetrating the substrate, the first buffer layer and the second buffer layer at the position of the blind hole.

4. The manufacturing method according to claim 1, further comprising: forming the blind hole on the first surface of the substrate; forming a first buffer layer on the first surface of the substrate, wherein the first buffer layer covers the blind hole; forming the first conductive pattern and the active element on the first buffer layer; as well as The etching process is performed to form the through hole penetrating the substrate and the first buffer layer at the position of the blind hole.

5. The manufacturing method according to claim 4, further comprising: forming a second buffer layer on the second surface of the substrate; as well as The etching process is performed to form the through hole penetrating the substrate, the first buffer layer and the second buffer layer at the position of the blind hole.

6. The manufacturing method according to claim 1, further comprising: Providing a circuit board on the second surface of the substrate, and the circuit board is electrically connected to the second conductive pattern; as well as A light emitting diode is provided on the first surface of the substrate. 7 . The manufacturing method as claimed in claim 1 , wherein a method of forming the blind hole on the substrate comprises laser, and the etching process comprises laser etching. The manufacturing method as claimed in claim 1 , wherein the conductive holes have different widths. 9 . The manufacturing method as claimed in claim 1 , wherein the etching process is performed to form the through hole penetrating the substrate and the gate insulating layer at the position of the blind hole. 10 . The manufacturing method as claimed in claim 1 , wherein a process for forming the active device comprises a process at a temperature of 200 degrees Celsius to 600 degrees Celsius. 11 . The manufacturing method as claimed in claim 1 , wherein the etching process stops at the first conductive pattern. 12 . The manufacturing method as claimed in claim 1 , wherein after forming the blind hole, the first conductive pattern and the active component are formed on the first surface of the substrate.

13. A method for manufacturing an active component substrate, comprising: forming a blind hole in the substrate; forming a first conductive pattern and an active element on the first surface of the substrate, wherein the first conductive pattern overlaps the blind hole; After forming the first conductive pattern and the active element, performing an etching process on the substrate to form a through hole penetrating the substrate at the position of the blind hole; Filling a conductive material into the through hole to form a conductive hole, wherein the conductive hole is electrically connected to the first conductive pattern; and forming a second conductive pattern on the second surface of the substrate, wherein the second conductive pattern is electrically connected to the first conductive pattern through the conductive hole, The step of forming the first conductive pattern and the active element on the first surface of the substrate includes: forming the first conductive pattern and the gate on the first surface of the substrate; forming a semiconductor channel layer; forming a gate insulating layer between the gate and the semiconductor channel layer, wherein the semiconductor channel layer overlaps the gate; and A source and a drain are formed on the semiconductor channel layer.

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