Image synthesis system, method, device and chip

Abstract

The embodiments of the present application provide a picture synthesis system, method, device and chip. The system includes a first chip for obtaining a network request carrying information for describing a combined picture of a first download address and a second download address, obtaining a first picture according to the first download address and sending the first picture to a second chip, and sending non-background layer information including the second download address to the second chip; the second chip is used to determine whether a cached picture corresponding to the second picture is cached in the RAM according to the non-background layer information; if there is a cached picture, the cached picture is obtained from the RAM and a superimposed picture is generated based on the first picture and the cached picture; if there is no cached picture, the first chip is notified to obtain the second picture according to the second download address, receive the second picture sent by the first chip, and generate a superimposed picture based on the first picture and the second picture. The present application breaks through the limitations of picture download and bus bandwidth on picture processing speed, and improves the picture processing speed.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a picture synthesis system, method, device and chip. Background Art

[0002] In the field of computer technology, a customized image processing service may be provided by an FPGA server, wherein the customized image processing service may include a service for combining multiple images into one image.

[0003] Generally, the FPGA server may include a CPU chip + an FPGA chip, and the CPU chip and the FPGA chip may be connected via a bus. After receiving a network request for requesting to combine multiple images into one image, the CPU chip obtains the multiple images according to the download address carried in the network request, and sends the multiple images to the FPGA chip via the bus. The FPGA chip combines the multiple images into one image according to the multiple images sent by the CPU chip.

[0004] However, this method has the problem of slow image processing speed due to limitations in network download and bus bandwidth between chips. Summary of the invention

[0005] The embodiments of the present application provide a picture synthesis system, method, device and chip to solve the problem of slow picture processing speed due to limitations of network download and bus bandwidth between chips in the prior art.

[0006] In a first aspect, an embodiment of the present application provides a picture synthesis system, comprising: a first chip, a second chip connected to the first chip via a bus, and a RAM outside the second chip;

[0007] The first chip is used to obtain a network request, the network request carries combined image information, the combined image information is used to describe a first download address and a second download address, the first download address is a download address of an image corresponding to a background layer, and the second download address is a download address of an image corresponding to a non-background layer;

[0008] The first chip is further used to obtain a first picture according to the first download address, and send the first picture to the second chip, and send non-background layer information to the second chip, wherein the non-background layer information includes the second download address;

[0009] The second chip is used to determine whether a cached image corresponding to the second image is cached in the RAM according to the non-background layer information; if the cached image is cached, obtain the cached image from the RAM, and generate an overlay image according to the first image and the cached image; if the cached image is not cached, notify the first chip to obtain the second image according to the second download address, receive the second image sent by the first chip, and generate an overlay image according to the first image and the second image;

[0010] The first chip is further configured to obtain the second picture according to the second download address in response to the notification of the second chip, and send the second picture to the second chip.

[0011] In a second aspect, an embodiment of the present application provides a picture synthesis method, which is applied to a first chip, and the method includes:

[0012] Obtain a network request, wherein the network request carries combined image information, wherein the combined image information is used to describe a first download address and a second download address, wherein the first download address is a download address of an image corresponding to a background layer, and the second download address is a download address of an image corresponding to a non-background layer;

[0013] Obtain a first picture according to the first download address, and send the first picture to the second chip, and send non-background layer information to the second chip, wherein the non-background layer information includes the second download address;

[0014] In response to the notification of the second chip, the second picture is obtained according to the second download address, and the second picture is sent to the second chip.

[0015] In a third aspect, an embodiment of the present application provides a method for synthesizing an image, which is applied to a second chip, and the method includes:

[0016] receiving a first picture and non-background layer information sent by a first chip, wherein the first picture is obtained by the first chip according to a first download address, and the non-background layer information includes a second download address, wherein the first download address is a download address of a picture corresponding to the background layer, and the second download address is a download address of a picture corresponding to the non-background layer;

[0017] Determine, based on the non-background layer information, whether a cached image corresponding to the second image is cached in the external RAM;

[0018] If the cache exists, obtaining the cached image from the RAM, and generating an overlay image according to the first image and the cached image;

[0019] If the second picture is not cached, the first chip is notified to obtain the second picture according to the second download address, the second picture sent by the first chip is received, and an overlay picture is generated according to the first picture and the second picture.

[0020] In a fourth aspect, an embodiment of the present application provides a picture synthesis device, applied to a first chip, including:

[0021] An acquisition module, used to acquire a network request, wherein the network request carries combined image information, wherein the combined image information is used to describe a first download address and a second download address, wherein the first download address is a download address of an image corresponding to a background layer, and the second download address is a download address of an image corresponding to a non-background layer;

[0022] A sending module, used to obtain a first picture according to the first download address, send the first picture to a second chip, and send non-background layer information to the second chip, wherein the non-background layer information includes the second download address; and, in response to a notification from the second chip, obtain the second picture according to the second download address, and send the second picture to the second chip.

[0023] In a fifth aspect, an embodiment of the present application provides a picture synthesis device, applied to a second chip, including:

[0024] a receiving module, configured to receive a first picture and non-background layer information sent by a first chip, wherein the first picture is obtained by the first chip according to a first download address, and the non-background layer information includes a second download address, wherein the first download address is a download address of a picture corresponding to the background layer, and the second download address is a download address of a picture corresponding to the non-background layer;

[0025] A determination module, used to determine whether a cached image corresponding to the second image is cached in the external RAM according to the non-background layer information;

[0026] An overlay module is configured to obtain the cached image from the RAM if the cached image is available, and generate an overlay image based on the first image and the cached image; if the cached image is not available, notify the first chip to obtain the second image according to the second download address, receive the second image sent by the first chip, and generate an overlay image based on the first image and the second image.

[0027] In a sixth aspect, an embodiment of the present application provides a chip, comprising: a memory, a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions, when executed by the processor, implement a method as described in any one of the second aspects.

[0028] In the seventh aspect, an embodiment of the present application provides a chip, comprising: a memory and a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions, when executed by the processor, implement a method as described in any one of the third aspects.

[0029] In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed, the method as described in any one of the second aspects is implemented.

[0030] In a ninth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed, the method as described in any one of the third aspects is implemented.

[0031] An embodiment of the present application further provides a computer program, which, when executed by a computer, is used to implement the method as described in any one of the first aspects.

[0032] An embodiment of the present application further provides a computer program, which, when executed by a computer, is used to implement the method as described in any one of the second aspects.

[0033] In an embodiment of the present application, the first chip can send the first image obtained according to the download address of the image corresponding to the background layer (i.e., the first download address) and the non-background layer information including the download address of the image corresponding to the non-background layer (i.e., the second download address) to the second chip. The second chip can determine whether there is a cached image corresponding to the second image cached in its external RAM according to the non-background layer information. If there is a cached image, it is directly obtained from the RAM. If there is no cached image, the first chip is notified to obtain the second image according to the second download address. This enables the second chip to directly obtain the image corresponding to the non-background layer from the RAM, so that some images corresponding to the non-background layer do not need to be downloaded or transmitted through the bus between the first chip and the second chip, breaking through the limitations of image download and bus bandwidth on image processing speed, thereby improving the image processing speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 A schematic diagram of an application scenario of an embodiment of the present application;

[0036] Figure 2 A schematic diagram of the structure of the picture synthesis system provided in the embodiment of the present application;

[0037] Figure 3A A schematic diagram of a picture corresponding to the background layer provided in an embodiment of the present application;

[0038] Figure 3B A schematic diagram of a picture corresponding to a non-background layer provided in an embodiment of the present application;

[0039] Figure 3C The basis provided for the embodiments of this application Figure 3A and Figure 3B Schematic diagram of superimposed images generated by images;

[0040] Figure 4 A schematic diagram of a process for processing a network request by a picture synthesis system provided in an embodiment of the present application;

[0041] Figure 5 A schematic diagram of a process flow of a picture synthesis method provided in an embodiment of the present application;

[0042] Figure 6 A schematic diagram of a flow chart of a method for synthesizing an image provided by another embodiment of the present application;

[0043] Figure 7 A schematic diagram of the structure of a picture synthesis device provided in one embodiment of the present application;

[0044] Figure 8 A schematic diagram of the structure of a chip provided in one embodiment of the present application;

[0045] Fig. 9 A schematic diagram of the structure of a picture synthesis device provided in another embodiment of the present application;

[0046] Fig.10 A schematic diagram of the structure of a chip provided in another embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings, and "multiple" generally includes at least two, but does not exclude the inclusion of at least one.

[0049] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0050] As used herein, the words "if" and "if" may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0051] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a product or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a product or system. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the product or system including the elements.

[0052] In addition, the step sequence in the following method embodiments is only an example and not a strict limitation.

[0053] Figure 1 Schematic diagram of application scenarios of the embodiments of the present application, such as Figure 1 As shown, the application scenario may include a terminal 11 and a server 12, wherein the terminal 11 may send a network request to the server 12 in response to a user operation, and the network request may be used to request to combine multiple pictures into one picture, and the terminal 11 may be, for example, a mobile phone, a tablet computer, a personal computer, etc. The server 12 may perform picture combination processing in response to the network request, and the server 12 may be a cloud server, a physical server, etc.

[0054] Among them, an application program (APP) may be installed on the terminal 11, and the user may use the application to trigger the terminal 11 to send a network request for a service object of the customized image processing service to the server 12, and the network request may be, for example, an http request.

[0055] The server 12 may include a first chip and a second chip connected to the first chip via a bus, wherein the first chip may respond to a network request, obtain a picture and send the picture to the second chip via the bus, and the second chip may combine multiple pictures into one picture. The computing power of the second chip may be stronger than that of the first chip.

[0056] Exemplarily, the first chip may include a central processing unit (CPU) chip, and the second chip may include a field programmable gate array (FPGA) chip. In this case, the server 12 may include an FPGA server. When the second chip is an FPGA chip, the second chip may also be located on an FPGA board, and the FPGA board may be connected to the computer where the CPU chip is located through a high-speed peripheral component interconnect standard (PCIE) bus, that is, the bus between the FPGA board and the CPU chip may be a PCIE bus.

[0057] Alternatively, illustratively, the first chip may include a CPU chip, and the second chip may include an Application Specific Integrated Circuit (ASIC) chip. Of course, in other embodiments, the first chip may also be other types of chips that can obtain images in response to network requests, and the second chip may also be other types of chips that can synthesize multiple images into one image and have stronger computing power than the first chip, and this application does not limit this.

[0058] The multiple pictures may include pictures corresponding to a background layer and pictures corresponding to a non-background layer, wherein the non-background layer is located above the background layer, the number of non-background layers may be multiple, and there is a hierarchical relationship between the multiple non-background layers. The pictures corresponding to the multiple non-background layers may be superimposed on the background layer in sequence according to the hierarchical relationship.

[0059] It should be noted that Figure 1 The scene shown can specifically be any type of scene that requires real-time image synthesis based on a network request sent by a terminal. Figure 1The scenario shown may specifically be an e-commerce scenario, and accordingly, the service object of the customized image processing service may be a merchant.

[0060] For example, taking the e-commerce scenario as an example, the image corresponding to the background layer may be a product image, the image corresponding to the non-background layer may include a watermark image, and the generated superimposed image may be a watermarked image. For another example, taking the e-commerce scenario as an example, the image corresponding to the background layer may be a product image, the image corresponding to the non-background layer may include a border image, and the generated superimposed image may be a bordered image. For another example, taking the e-commerce scenario as an example, the image corresponding to the background layer may be a product image, the image corresponding to the non-background layer may include a border image and a watermark image, and the generated superimposed image may be a bordered and watermarked image.

[0061] Usually, the CPU chip obtains the multiple images according to the download address carried in the network request, and sends the multiple images to the FPGA chip through the bus. The FPGA chip combines the multiple images into one image according to the multiple images sent by the CPU chip. However, this method has the problem of slow image processing speed due to the limitation of network download and bus bandwidth between chips.

[0062] The inventor of the present application found that in actual applications, for different network requests for the same service object (such as the same merchant), the images corresponding to the background layer are often different, but the images corresponding to the non-background layer are often the same. For example, in an e-commerce scenario, for the same merchant, the product images are often different, but the watermark image and the frame image are often the same. Therefore, the inventor of the present application proposed to cache the images corresponding to the non-background layer in a random access memory (RAM) outside the second chip.

[0063] Therefore, in order to solve the technical problem in the prior art that the image processing speed is slow due to the limitation of network download and bus bandwidth between chips, in an embodiment of the present application, the first chip can send the first image obtained according to the download address of the image corresponding to the background layer (i.e., the first download address) and the non-background layer information including the download address of the image corresponding to the non-background layer (i.e., the second download address) to the second chip. The second chip can determine whether there is a cached image corresponding to the second image cached in its external RAM according to the non-background layer information. If there is a cached image, it is directly obtained from the RAM. If there is no cached image, the first chip is notified to obtain the second image. The second chip can directly obtain the image corresponding to the non-background layer from the RAM, so that some images corresponding to the non-background layer do not need to be downloaded or transmitted through the bus between the first chip and the second chip, breaking through the limitations of image download and bus bandwidth on image processing speed and improving the image processing speed.

[0064] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0065] Figure 2 This is a structural diagram of a picture synthesis system provided in an embodiment of the present application. The picture synthesis system can be applied to Figure 1 In the server 12. Figure 2 As shown, the picture synthesis system may include: a first chip 21 , a second chip 22 connected to the first chip 21 via a bus, and a RAM 23 outside the second chip 22 .

[0066] The first chip 21 can be used to obtain a network request, and the network request carries combined image information, and the combined image information is used to describe a first download address and a second download address, the first download address is a download address of an image corresponding to a background layer, and the second download address is a download address of an image corresponding to a non-background layer. It should be understood that when the number of non-background layers is multiple, the second download address can be multiple. Exemplarily, the image corresponding to the background layer and the image corresponding to the non-background layer can both be stored in an object storage service (OSS) server, and the first chip 21 can download the image from the OSS server.

[0067] For example, when the network request is an http request, the combined image information can be carried in the Uniform Resource Locator (URL) address of the network request, and the first chip can obtain the combined image information by parsing the URL address. Of course, in other embodiments, the combined image information can also be carried in the network request in other ways, which is not limited in this application. The URL address of the network request can be, for example:

[0068] https: / / **-oss**.com / example.jpg? watermark,panda.png

[0069] Among them, **-oss**.com / example.jpg can represent the first download address, **-oss**.com / panda.png can represent the second download address, and the second picture is used as a watermark picture.

[0070] In one embodiment, the combined image information can also be used to describe the first preprocessing method and / or the second preprocessing method, wherein the first preprocessing method is a method for preprocessing the image corresponding to the background layer, and the second preprocessing method is a method for preprocessing the image corresponding to the non-background layer. The preprocessing method for an image may include, for example, rotation, scaling, setting transparency, etc. Taking the network request as an http request, and the combined image information carried in the URL address of the network request as an example, the URL address of the network request may be, for example:

[0071] https: / / **-oss**.com / example.jpg? process=image / resize,w_300 / watermark,panda.png? process=image / resize,P_30,t_90,g_se,x_10,y_10

[0072] Among them, process=image / resize,w_300 is the first preprocessing method, which can mean scaling example.jpg to a width of 300. process=image / resize,P_30,t_90,g_se,x_10,y_10 is the second preprocessing method, which can mean scaling panda.png by 30%, setting the transparency to 90%, setting the position to the lower right, setting the horizontal margin to 10, and setting the centerline vertical offset to 10.

[0073] In practical applications, the first download address carried in the network request may be the download address of the original image, and the second download address may be the download address of the processed image obtained by at least partially preprocessing the original image. In this case, the URL address of the network request in the above example may be changed to:

[0074] https: / / **-oss**.com / example.jpg? process=image / resize,w_300 / watermark,image_cGFuZGEucG5nP3gtb3NzLXByb2Nlc3M9aW1hZ2UvcmVzaXplLFBfMzA,t_90,g_se,x_10,y_10

[0075] Among them, cGFuZGEucG5nP3gtb3NzLXByb2Nlc3M9aW1hZ2UvcmVzaXplLFBfMzA is the value after panda.png?process=image / resize,P_30 is encoded.

[0076] After obtaining the network request, the first chip 21 can also be used to obtain the first picture according to the first download address, and send the first picture to the second chip 22. Exemplarily, the first chip 21 can directly send the picture downloaded according to the first download address to the second chip 22. In this case, the first chip 21 can also send the first preprocessing method to the second chip 22, and the second chip 22 preprocesses the first picture according to the first preprocessing method. Figure 3A shown.

[0077] After obtaining the network request, the first chip 21 can also be used to send the non-background layer information including the second download address to the second chip 22. Optionally, the non-background layer information can also include a second preprocessing method. It should be understood that the non-background layer does not include the first preprocessing method.

[0078] After receiving the non-background layer information sent by the first chip 21, the second chip 22 can also be used to determine whether a cached image corresponding to the second image is cached in RAM23 based on the non-background layer information; if it is cached, the cached image is obtained from RAM, and an overlay image is generated based on the first image and the cached image; if it is not cached, the first chip 21 is notified to obtain the second image according to the second download address, the second image sent by the first chip 21 is received, and an overlay image is generated based on the first image and the second image.

[0079] Exemplarily, a target keyword can be generated based on non-background layer information to determine whether there is a storage address corresponding to the target keyword in the correspondence between different keywords and storage addresses, and any keyword in the correspondence is cached at a storage address corresponding to any keyword in RAM23; if it exists, it means that a cached image corresponding to the second image is cached in RAM23; if it does not exist, it means that a cached image corresponding to the second image is not cached in RAM23.

[0080] Exemplarily, when the non-background layer information is character string information, generating a target keyword according to the non-background layer information may include: performing a hash operation on the non-background layer information to obtain the target keyword.

[0081] Optionally, in order to improve processing efficiency, it is possible to determine whether a cached image corresponding to the second image is cached in RAM23 by looking up a table. Based on this, in one embodiment, it is possible to determine whether the target keyword hits any keyword in a preset table, and the preset table is used to store the corresponding relationship between the keyword and the storage address of its corresponding cached image in RAM23; if it hits, it means that a cached image corresponding to the second image is cached in RAM23; if it does not hit, it means that a cached image corresponding to the second image is not cached in RAM23.

[0082] After receiving the notification from the second chip 22, the first chip 21 may also be used to respond to the notification from the second chip 22, obtain the second picture according to the second download address, and send the second picture to the second chip 22. Exemplarily, the first chip 21 may directly send the picture downloaded according to the second download address to the second chip 22, and the second chip 22 may preprocess the second chip according to the second preprocessing method.

[0083] Wherein, in the case where the first picture sent by the first chip 21 is an undecoded picture, after receiving the first picture sent by the first chip 21, the second chip 22 can decode the received first picture to obtain the decoded first picture. Further, in the case where the decoded first picture needs to be preprocessed, the second chip 22 can also adopt the first preprocessing method to preprocess the decoded first picture to obtain the preprocessed first picture. In one embodiment, after obtaining the preprocessed first picture, the preprocessed first picture can be used as the picture of the background layer.

[0084] In the case where the second picture sent by the first chip 21 is an undecoded picture, the second chip 22 can decode the received second picture after receiving the second picture sent by the first chip 21 to obtain a decoded second picture. Furthermore, in the case where the decoded second picture needs to be preprocessed, the second chip 22 can also adopt a second preprocessing method to preprocess the decoded second picture to obtain a preprocessed second picture. In one embodiment, after obtaining the preprocessed second picture, the preprocessed second picture can be superimposed as a picture of a non-background layer on a picture of a background layer to generate a superimposed picture. Taking the first picture as Figure 3A The picture shown, the second picture is Figure 3B As an example, the generated overlay image can be Figure 3C It should be understood that when there are multiple non-background layers, the images of the multiple non-background layers can be sequentially superimposed on the image of the background layer.

[0085] In the case where the cached picture corresponding to the second picture cached in RAM23 is an undecoded picture, the second chip 22 can decode the cached picture after acquiring the cached picture from RAM23 to obtain the decoded cached picture. Furthermore, in the case where the decoded cached picture needs to be preprocessed, the second chip 22 can also adopt a second preprocessing method to preprocess the decoded cached picture to obtain a preprocessed cached picture. In one embodiment, after obtaining the preprocessed cached picture, the preprocessed cached picture can be superimposed on the picture of the background layer as a picture of a non-background layer to generate a superimposed picture.

[0086] When the cached image corresponding to the second image cached in RAM23 is a preprocessed image, after obtaining the cached image from RAM23, the second chip 22 can superimpose the cached image as an image of a non-background layer on the image of the background layer to generate a superimposed image.

[0087] Optionally, after receiving the second picture sent by the first chip 21, the second chip 22 can directly cache the received second picture in the RAM 23, so that when the second picture is needed for superposition later, it can be directly obtained from the RAM 23. Based on this, in one embodiment, the second chip 22 can also be used to cache the second picture in the RAM 23 after receiving the second picture sent by the first chip.

[0088] Exemplarily, when a preset table is used to store the correspondence between the keyword and the storage address of the corresponding cache image in RAM23, the second chip 22 can specifically write the second image into RAM23, and add the correspondence between the target keyword and the storage address for storing the second image in RAM23 in the preset table.

[0089] Alternatively, when the non-background layer information also includes the second preprocessing method, after receiving the second image sent by the first chip 21 and processing the second image using the second preprocessing method to obtain the preprocessed second image, the second chip 22 can cache the obtained preprocessed second image into the RAM 23, so that when the preprocessed second image is needed to be superimposed later, the preprocessed second image can be directly obtained from the RAM 23. Based on this, in one embodiment, the second chip 22 can also be used to cache the preprocessed second image into the RAM 23.

[0090] Exemplarily, when a preset table is used to store the correspondence between the keyword and the storage address of the corresponding cache image in RAM23, the second chip 22 can specifically write the preprocessed second image into RAM23, and add a correspondence between the target keyword and the storage address in RAM23 for storing the preprocessed second image in the preset table.

[0091] Optionally, a life cycle can be set for the cached images cached in RAM 23, so as to save storage resources. Based on this, in one embodiment, the second chip 22 can also be used to mark any cached image in RAM 23 as expired when the life cycle of any cached image in RAM 23 is reached.

[0092] Exemplarily, the processing flow of the image synthesis system processing network requests is as follows: Figure 4In step 41, the combined image information can be parsed from the received network request; then, in step 42, the first image can be downloaded based on the first download address in the combined image information, and in step 43, the downloaded first image is decoded and the decoded first image is used as the image of the background layer; in step 44, for the current non-background layer, it can be determined whether the data in the RAM outside the chip is hit, and if it is hit, the cached image can be directly obtained from the RAM outside the chip in step 45, and the cached image is used as the current non-background layer The image is superimposed on the image of the background layer in step 46 If there is no hit, then in step 47, the second picture can be downloaded according to the second download address, and in step 48, the downloaded second picture is preprocessed in a second preprocessing manner, and in step 49, the preprocessed second picture is superimposed on the picture of the background layer as the current non-background layer picture; thereafter, in step 410, it can be determined whether the current non-background layer is the last non-background layer, if not, the process can return to step 44 for execution, and if so, the superimposed picture can be scaled and cropped in step 411, and the cropped and scaled superimposed picture can be encoded in step 412.

[0093] It should be noted that Figure 4 In the figure, a rectangular box filled with white is used to indicate that the corresponding step can be executed by the first chip, a rectangular box filled with dark gray is used to indicate that the corresponding step can be executed by the second chip, and a rectangular box filled with light gray is used to indicate that the corresponding step can be executed by the first chip or the second chip.

[0094] In an embodiment of the present application, the first chip can send the first image obtained according to the download address of the image corresponding to the background layer (i.e., the first download address) and the non-background layer information including the download address of the image corresponding to the non-background layer (i.e., the second download address) to the second chip. The second chip can determine whether there is a cached image corresponding to the second image cached in its external RAM according to the non-background layer information. If there is a cached image, it is directly obtained from the RAM. If there is no cached image, the first chip is notified to obtain the second image according to the second download address. The second chip can directly obtain the image corresponding to the non-background layer from the RAM, so that some images corresponding to the non-background layer do not need to be downloaded or transmitted through the bus between the first chip and the second chip, breaking through the limitations of image download and bus bandwidth on image processing speed, thereby improving the image processing speed.

[0095] Figure 5 Schematic diagram of a flow chart of a method for synthesizing an image provided by an embodiment of the present application. The method provided by this embodiment can be applied to the first chip 21 in the aforementioned image synthesis system, such as Figure 5 As shown, the method provided in this embodiment may include:

[0096] Step 51, obtaining a network request, wherein the network request carries combined image information, wherein the combined image information is used to describe a first download address and a second download address, wherein the first download address is a download address of an image corresponding to a background layer, and the second download address is a download address of an image corresponding to a non-background layer;

[0097] Step 52, obtaining a first picture according to the first download address, and sending the first picture to the second chip, and sending non-background layer information to the second chip, wherein the non-background layer information includes the second download address;

[0098] Step 53: In response to the notification of the second chip, obtain the second picture according to the second download address, and send the second picture to the second chip.

[0099] It should be noted that for the specific implementation of the first chip, please refer to Figure 2 The specific description of the illustrated embodiments will not be repeated here.

[0100] The image synthesis method provided in this embodiment sends non-background layer information including a second download address to a second chip through a first chip, obtains a second image according to the second download address in response to a notification from the second chip, and sends the second image to the second chip, so that when the second chip determines that a cached image corresponding to the second image is cached in an off-chip RAM according to the non-background layer information, the second chip can directly obtain the cached image from the RAM for image synthesis.

[0101] Figure 6 FIG. 2 is a flow chart of a method for synthesizing an image provided by another embodiment of the present application. The method provided by this embodiment can be applied to the second chip 22 in the aforementioned image synthesis system, such as Figure 6 As shown, the method provided in this embodiment may include:

[0102] Step 61, receiving a first picture and non-background layer information sent by a first chip, wherein the first picture is obtained by the first chip according to a first download address, and the non-background layer information includes a second download address, wherein the first download address is a download address of a picture corresponding to the background layer, and the second download address is a download address of a picture corresponding to the non-background layer;

[0103] Step 62, determining whether a cached image corresponding to the second image is cached in the external RAM according to the non-background layer information;

[0104] Step 63: if the cached image exists, obtain the cached image from the RAM, and generate an overlay image according to the first image and the cached image;

[0105] Step 64: if the second picture is not cached, notify the first chip to obtain the second picture according to the second download address, receive the second picture sent by the first chip, and generate a superimposed picture according to the first picture and the second picture.

[0106] In one embodiment, determining whether a cached image corresponding to the second image is cached in the RAM based on the non-background layer information includes: generating a target keyword based on the non-background layer information, and determining whether the target keyword hits any keyword in a preset table, wherein the preset table is used to store the correspondence between the keyword and the storage address of the corresponding cached image in the RAM, if it hits, it indicates that a cached image corresponding to the second image is cached in the RAM; if it does not hit, it indicates that a cached image corresponding to the second image is not cached in the RAM.

[0107] In one embodiment, the method further includes: after receiving the second image sent by the first chip, caching the second image into the RAM.

[0108] In one embodiment, the combined image information is also used to describe a second preprocessing method, and the second preprocessing method is a method for preprocessing the image corresponding to the non-background layer; the non-background layer information also includes the second preprocessing method; the generating the superimposed image according to the received first image and the second image obtained from the RAM specifically includes: preprocessing the received second image using the second preprocessing method to obtain the preprocessed second image; and generating the superimposed image according to the received first image and the preprocessed second image;

[0109] The method further includes: caching the preprocessed second image into the RAM.

[0110] In one embodiment, the method further includes: when the life cycle of any cached image in the RAM is reached, marking any cached image in the RAM as expired.

[0111] It should be noted that for the specific implementation of the second chip, please refer to Figure 2 The specific description of the illustrated embodiments will not be repeated here.

[0112] The picture synthesis method provided in this embodiment receives the first picture sent by the first chip and related information including the second download address, and determines whether a cache picture corresponding to the second picture is cached in the RAM according to the non-background layer information. If so, the cache picture is obtained from the RAM and an overlay picture is generated according to the first picture and the cached picture. If not, the first chip is notified to obtain the second picture, the second picture sent by the first chip is received, and an overlay picture is generated according to the first picture and the second picture. This enables the second chip to directly obtain the picture corresponding to the non-background layer from the RAM, so that some pictures corresponding to the non-background layer do not need to be downloaded or transmitted through the bus between the first chip and the second chip, breaking through the limitations of picture downloading and bus bandwidth on picture processing speed, thereby improving picture processing speed.

[0113] Figure 7 This is a structural diagram of a picture synthesis device provided in an embodiment of the present application; Figure 7 As shown, this embodiment provides a device, which can execute the method on the first chip side in the above method. Specifically, the device may include:

[0114] An acquisition module 71 is used to acquire a network request, wherein the network request carries combined image information, wherein the combined image information is used to describe a first download address and a second download address, wherein the first download address is a download address of an image corresponding to a background layer, and the second download address is a download address of an image corresponding to a non-background layer;

[0115] The sending module 72 is used to obtain the first picture according to the first download address, send the first picture to the second chip, and send non-background layer information to the second chip, wherein the non-background layer information includes the second download address; and, in response to the notification of the second chip, obtain the second picture according to the second download address, and send the second picture to the second chip.

[0116] Figure 7 The device shown can perform Figure 2 The method of the first chip side in the embodiment shown in the figure, for the part not described in detail in this embodiment, please refer to Figure 2 The implementation process and technical effects of this technical solution refer to Figure 2 The description in the illustrated embodiment will not be repeated here.

[0117] In one possible implementation, Figure 7 The structure of the device shown can be implemented as a chip. Figure 8 As shown, the chip may include: a processor 81 and a memory 82. The memory 82 is used to store the processor 81 and the memory 82 to support the chip to execute the above Figure 2In the illustrated embodiment, the method provided in the first chip side program, the processor 81 is configured to execute the program stored in the memory 82 .

[0118] The program includes one or more computer instructions, wherein when the one or more computer instructions are executed by the processor 81, the following steps can be implemented:

[0119] Obtain a network request, wherein the network request carries combined image information, wherein the combined image information is used to describe a first download address and a second download address, wherein the first download address is a download address of an image corresponding to a background layer, and the second download address is a download address of an image corresponding to a non-background layer;

[0120] Obtain a first picture according to the first download address, and send the first picture to the second chip, and send non-background layer information to the second chip, wherein the non-background layer information includes the second download address;

[0121] In response to the notification of the second chip, the second picture is obtained according to the second download address, and the second picture is sent to the second chip.

[0122] Optionally, the processor 81 is further configured to execute the aforementioned Figure 2 All or part of the steps on the first chip side in the illustrated embodiment.

[0123] The chip structure may also include a communication interface 83 for the chip to communicate with other devices or communication networks.

[0124] Fig. 9 This is a structural diagram of a picture synthesis device provided in another embodiment of the present application; see attached Fig. 9 As shown, this embodiment provides a device, which can execute the method on the second chip side in the above method. Specifically, the device may include:

[0125] The receiving module 91 is used to receive a first picture and non-background layer information sent by the first chip, wherein the first picture is obtained by the first chip according to a first download address, and the non-background layer information includes a second download address, wherein the first download address is a download address of a picture corresponding to the background layer, and the second download address is a download address of a picture corresponding to the non-background layer;

[0126] A determination module 92, configured to determine whether a cached image corresponding to the second image is cached in the external RAM according to the non-background layer information;

[0127] The overlay module 93 is used to obtain the cached image from the RAM if it is cached, and generate an overlay image based on the first image and the cached image; if it is not cached, notify the first chip to obtain the second image according to the second download address, receive the second image sent by the first chip, and generate an overlay image based on the first image and the second image.

[0128] In one embodiment, the determination module 92 is specifically used to: generate a target keyword based on the non-background layer information, and determine whether the target keyword hits any keyword in a preset table, wherein the preset table is used to store the correspondence between the keyword and the storage address of the corresponding cached image in the RAM. If it hits, it indicates that a cached image corresponding to the second image is cached in the RAM; if it does not hit, it indicates that a cached image corresponding to the second image is not cached in the RAM.

[0129] In one embodiment, the apparatus provided in this embodiment may further include a first cache module, configured to cache the second image into the RAM after receiving the second image sent by the first chip.

[0130] In one embodiment, the combined image information is further used to describe a second preprocessing method, and the second preprocessing method is a method for preprocessing the image corresponding to the non-background layer; the non-background layer information also includes the second preprocessing method; the superposition module 93 is specifically used to: preprocess the received second image using the second preprocessing method to obtain a preprocessed second image; and generate a superimposed image according to the received first image and the preprocessed second image;

[0131] The device provided in this embodiment may further include a second cache module, configured to cache the preprocessed second image into the RAM.

[0132] In one embodiment, the apparatus provided in this embodiment may further include a cleaning module, which is used to mark any cached image in the RAM as expired when the life cycle of any cached image in the RAM is reached.

[0133] Fig. 9 The device shown can perform Figure 2 The method of the second chip side in the embodiment shown in FIG. 1 may be referred to for the part not described in detail in the embodiment. Figure 2 The implementation process and technical effects of this technical solution refer to Figure 2 The description in the illustrated embodiment will not be repeated here.

[0134] In one possible implementation, Fig. 9 The structure of the device shown can be implemented as a chip. Fig.10 As shown, the chip may include: a processor 101 and a memory 102. The memory 102 is used to store the processor 101 and the memory 102. Figure 2 In the illustrated embodiment, the program on the second chip side of the method provided is that the processor 101 is configured to execute the program stored in the memory 102 .

[0135] The program includes one or more computer instructions, wherein when the one or more computer instructions are executed by the processor 101, the following steps can be implemented:

[0136] receiving a first picture and non-background layer information sent by a first chip, wherein the first picture is obtained by the first chip according to a first download address, and the non-background layer information includes a second download address, wherein the first download address is a download address of a picture corresponding to the background layer, and the second download address is a download address of a picture corresponding to the non-background layer;

[0137] Determine, based on the non-background layer information, whether a cached image corresponding to the second image is cached in the external RAM;

[0138] If the cache exists, the cached image is obtained from the RAM, and an overlay image is generated based on the first image and the cached image; if the cache does not exist, the first chip is notified to obtain the second image according to the second download address, the second image sent by the first chip is received, and an overlay image is generated based on the first image and the second image.

[0139] Optionally, the processor 101 is further configured to execute the aforementioned Figure 2 All or part of the steps on the second chip side in the embodiment shown.

[0140] The chip structure may also include a communication interface 103 for the chip to communicate with other devices or communication networks.

[0141] In addition, the embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed, the following is achieved: Figure 5 The method described in the method embodiment shown.

[0142] The present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed, the following is achieved: Figure 6 The method described in the method embodiment shown.

[0143] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative labor.

[0144] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by adding a necessary general hardware platform, and of course can also be implemented by combining hardware and software. Based on such an understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a computer product, and the present application can be in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0145] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable device to generate a machine, so that the instructions executed by the processor of the computer or other programmable device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0146] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0147] These computer program instructions may also be loaded onto a computer or other programmable device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1The steps for the functions specified in one or more boxes.

[0148] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0149] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0150] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, linked lists, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A picture synthesis system, characterized in that: include: A first chip, a second chip connected to the first chip via a bus, and a random access memory RAM outside the second chip; The first chip is used to obtain a network request, the network request carries combined image information, the combined image information is used to describe a first download address and a second download address, the first download address is a download address of an image corresponding to a background layer, and the second download address is a download address of an image corresponding to a non-background layer; The first chip is further used to obtain a first picture according to the first download address, and send the first picture to the second chip, and send non-background layer information to the second chip, wherein the non-background layer information includes the second download address; The second chip is used to determine whether a cached image corresponding to the second image is cached in the RAM according to the non-background layer information; If the cache exists, obtaining the cached image from the RAM, and generating an overlay image according to the first image and the cached image; If the second picture is not cached, instructing the first chip to obtain the second picture according to the second download address, receiving the second picture sent by the first chip, and generating a superimposed picture according to the first picture and the second picture; The first chip is further configured to obtain the second picture according to the second download address in response to the notification of the second chip, and send the second picture to the second chip.

2. The system according to claim 1, characterized in that The determining, according to the non-background layer information, whether a cached image corresponding to the second image is cached in the RAM comprises: A target keyword is generated according to the non-background layer information, and it is determined whether the target keyword hits any keyword in a preset table, wherein the preset table is used to store the correspondence between the keyword and the storage address of its corresponding cached image in the RAM. If it hits, it indicates that a cached image corresponding to the second image is cached in the RAM; if it does not hit, it indicates that a cached image corresponding to the second image is not cached in the RAM.

3. The system according to claim 1, characterized in that The second chip is further configured to cache the second image into the RAM after receiving the second image sent by the first chip.

4. The system according to claim 1, characterized in that The combined image information is further used to describe a second preprocessing method, where the second preprocessing method is a method for preprocessing the image corresponding to the non-background layer; the non-background layer information also includes the second preprocessing method; The second chip is specifically configured to preprocess the received second image using the second preprocessing method to obtain a preprocessed second image; and generate a superimposed image according to the received first image and the preprocessed second image; The second chip is further used to cache the preprocessed second image into the RAM.

5. The system according to any one of claims 1 to 4, characterized in that: The second chip is further configured to mark any cached image in the RAM as expired when the life cycle of any cached image in the RAM is reached.

6. The system according to any one of claims 1 to 4, characterized in that: The first chip includes a central processing unit (CPU) chip, and the second chip includes a field programmable gate array (FPGA) chip.

7. A method for synthesizing an image, characterized in that: Applied to the first chip, the method includes: Obtain a network request, wherein the network request carries combined image information, wherein the combined image information is used to describe a first download address and a second download address, wherein the first download address is a download address of an image corresponding to a background layer, and the second download address is a download address of an image corresponding to a non-background layer; Obtain a first picture according to the first download address, and send the first picture to the second chip, and send non-background layer information to the second chip, wherein the non-background layer information includes the second download address; In response to the notification of the second chip, a second picture is obtained according to the second download address, and the second picture is sent to the second chip.

8. A method for synthesizing an image, characterized in that: Applied to the second chip, the method includes: receiving a first picture and non-background layer information sent by a first chip, wherein the first picture is obtained by the first chip according to a first download address, and the non-background layer information includes a second download address, wherein the first download address is a download address of a picture corresponding to the background layer, and the second download address is a download address of a picture corresponding to the non-background layer; Determine, based on the non-background layer information, whether a cached image corresponding to the second image is cached in the external RAM; If the cache exists, obtaining the cached image from the RAM, and generating an overlay image according to the first image and the cached image; If the second picture is not cached, the first chip is notified to obtain the second picture according to the second download address, the second picture sent by the first chip is received, and an overlay picture is generated according to the first picture and the second picture.

9. The method according to claim 8, characterized in that The determining, according to the non-background layer information, whether a cached image corresponding to the second image is cached in the RAM comprises: A target keyword is generated according to the non-background layer information, and it is determined whether the target keyword hits any keyword in a preset table, wherein the preset table is used to store the correspondence between the keyword and the storage address of its corresponding cached image in the RAM. If it hits, it indicates that a cached image corresponding to the second image is cached in the RAM; if it does not hit, it indicates that a cached image corresponding to the second image is not cached in the RAM.

10. The method according to claim 8, characterized in that The method further includes: after receiving the second picture sent by the first chip, caching the second picture in the RAM.

11. The method according to claim 8, characterized in that The non-background layer information also includes a second preprocessing method, and the second preprocessing method is a method of preprocessing the image corresponding to the non-background layer; Generating the superimposed picture according to the received first picture and the second picture obtained from the RAM specifically includes: preprocessing the received second picture by using the second preprocessing method to obtain the preprocessed second picture; and generating the superimposed picture according to the received first picture and the preprocessed second picture; The method further includes: caching the preprocessed second image into the RAM.

12. The method according to claim 8, characterized in that The method further includes: when the life cycle of any cached image in the RAM is reached, marking any cached image in the RAM as expired.

13. A picture synthesis device, characterized in that: Applied to the second chip, the device comprises: a receiving module, configured to receive a first picture and non-background layer information sent by a first chip, wherein the first picture is obtained by the first chip according to a first download address, and the non-background layer information includes a second download address, wherein the first download address is a download address of a picture corresponding to the background layer, and the second download address is a download address of a picture corresponding to the non-background layer; A determination module, used to determine whether a cached image corresponding to the second image is cached in the external RAM according to the non-background layer information; An overlay module is configured to obtain the cached image from the RAM if the cached image is available, and generate an overlay image based on the first image and the cached image; if the cached image is not available, notify the first chip to obtain the second image according to the second download address, receive the second image sent by the first chip, and generate an overlay image based on the first image and the second image.

14. A chip, characterized in that: include: A memory, a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions, when executed by the processor, implement the method as described in any one of claims 7 to 12.

Images