A nonvolatile multi-state electrochemical memory and its processing method

Abstract

A non-volatile multi-state electrochemical memory and its processing method. The memory includes a source electrode, a drain electrode, a gate electrode, and an electrolyte layer disposed on a substrate. The source electrode serves as the bottom electrode, the drain electrode serves as the top electrode, and a polymer semiconductor channel is disposed between the source and drain electrodes to form an upright sandwich structure. The gate electrode is disposed on the side of the sandwich structure, and the polymer semiconductor channel is disposed between the gate electrode and the surface of the substrate. The electrolyte layer covers and fills the gate electrode, the sandwich structure, and the gap between the gate electrode and the sandwich structure from top to bottom. The gate electrode is connected to a write pulse circuit, and the drain electrode is connected to a read pulse circuit. The storage conductance value is calculated by obtaining a read current. The processing method includes using a solution processing method to deposit the polymer semiconductor channel, enhancing channel crystallization of the channel, and using a reactive ion etching method to open the channel. The present invention can realize multi-state non-volatile storage in a single device, with accurate writing, simple structure, and low processing cost.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and in particular relates to a non-volatile multi-state electrochemical memory and a processing method thereof. Background Art

[0002] Artificial intelligence technology has always been a strategic research focus for countries around the world. However, the hardware supporting artificial intelligence computing is still based on computer systems based on complementary metal-oxide-silicon semiconductor field-effect transistors (CMOS). Existing computer systems face the following technical bottlenecks: (1) Limited hardware computing efficiency; (2) Algorithm limitations. The algorithms currently used by computers are still based on the traditional von Neumann architecture and run in a sequential manner. Compared with the parallel data processing method of the human brain neural network, they are less efficient; (3) Due to the physical separation of the data storage unit and the data processing unit (CPU), the continuous calling, storage and transmission of data largely lead to the problems of high energy consumption and low efficiency of the system.

[0003] In contrast, artificial neural network (ANN) technology, based on the human brain's efficient, low-energy computing and storage methods, can provide AI with computational and memory capabilities comparable to those of the human brain. This technology breaks away from the traditional von Neumann architecture, which separates computation and storage, and achieves true computation-storage integration. This is the foundation for advanced AI applications and a key strategic research direction currently being pursued by various countries. Currently, the vast majority of neural networks are constructed using computer simulation or two-terminal non-volatile memristor arrays to construct ANNs and CNNs. These memristors include redox-reduction memristors (ReRAMs) and phase-change material memristors (PCMs). However, these two-terminal devices suffer from the following major issues: a small number of valid states (less than 6 bits) and extremely random conductance updates, which severely impact the computational efficiency of neural networks.

[0004] To address these shortcomings, researchers have developed three-terminal floating-gate transistor memories (FG) and electrochemical random access memory (ECRAM). Although these three-terminal devices have improved writing accuracy, they each have the following difficult-to-overcome issues:

[0005] Floating-gate memory suffers from poor write linearity and high write voltages (generally greater than 5V). Furthermore, its floating-gate structure significantly increases processing complexity. For most electrochemical memristors, a necessary condition for non-volatility is a forced open circuit between the gate and the channel. This condition often requires integrating other devices or circuits (such as switching circuits, field-effect transistors, and conductive bridge memory) onto the gate, significantly reducing its integration density and introducing processing incompatibility issues. Given these challenges, the industry urgently needs a memory with low write randomness, high linearity, a high number of stored bits, long and stable storage time, and low processing costs for high-performance integrated storage and computing hardware. Summary of the Invention

[0006] The purpose of the present invention is to address the problems in the above-mentioned prior art and provide a non-volatile multi-state electrochemical memory and a processing method thereof. The memory has a special device structure and a new polymer chain segment-ion interaction mechanism, which can realize multi-state non-volatile storage on a single device, with accurate writing, simple structure and low processing cost.

[0007] In order to achieve the above object, the present invention has the following technical solutions:

[0008] In a first aspect, a non-volatile multi-state electrochemical memory is provided, comprising a substrate and a source electrode, a drain electrode, a gate electrode, and an electrolyte layer arranged on the substrate; the source electrode serves as a bottom electrode, the drain electrode serves as a top electrode, and a polymer semiconductor channel is arranged between the source electrode and the drain electrode to form an upright sandwich structure; the gate electrode is arranged on the side of the sandwich structure, and a polymer semiconductor channel is arranged between the gate electrode and the surface of the substrate; the electrolyte layer covers and fills the gate electrode, the sandwich structure, and the gap between the gate electrode and the sandwich structure from top to bottom; the gate electrode is connected to a write pulse circuit, and the drain electrode is connected to a read pulse circuit, and the storage conductance value is calculated by obtaining a read current using Ohm's law.

[0009] Preferably, the source and drain in the sandwich structure are arranged to cross at 90° in space.

[0010] Preferably, the length of the polymer semiconductor channel between the source and the drain is 30nm to 80nm, the width is 10μm to 300μm, and the thickness is 10μm to 300μm; the length of the polymer semiconductor channel between the gate and the substrate is 10μm to 300μm, the width is 10μm to 300μm, and the thickness is 30nm to 80nm; the length of the gate is 10μm to 300μm, and the width is 10μm to 300μm.

[0011] Preferably, the source electrode, the drain electrode and the gate electrode are all polarizable inert electrodes, and the polarizable inert electrodes include any one of gold and indium tin oxide.

[0012] Preferably, the polymer semiconductor channel is formed of a polymer semiconductor material with high crystallinity, and the polymer semiconductor material with high crystallinity includes any one of PDPP3T, PBTTT, PTBT-p, P(g2T-TT) and BBL.

[0013] In a second aspect, a method for processing the nonvolatile multi-state electrochemical memory is provided, comprising the following steps:

[0014] Depositing metal on a clean substrate to form a source electrode;

[0015] Using a solution processing method to deposit an organic semiconductor on the surface of the source electrode and the substrate on the side of the source electrode to prepare a polymer semiconductor channel;

[0016] Enhancement of channel crystallization of polymer semiconductor channels by high temperature annealing process;

[0017] Depositing metal on the source electrode and the polymer semiconductor channel on the side of the source electrode to form a drain electrode and a gate electrode respectively, with a gap between the drain electrode and the gate electrode in the horizontal direction;

[0018] Reactive ion etching is used to open the polymer semiconductor channel between the drain and gate electrodes;

[0019] An electrolyte layer is prepared so that the electrolyte layer covers and fills the gate, the sandwich structure and the gap between the gate and the sandwich structure from top to bottom, thereby completing the processing of the non-volatile multi-state electrochemical memory.

[0020] Preferably, the solution processing method includes any one of a solution shear processing method and a solution spin coating method;

[0021] The solution shearing processing method includes:

[0022] An organic semiconductor solution is dripped onto the front of the source electrode and the substrate surface on the side of the source electrode, which are preheated to a temperature of 30° C. to 50° C., so that a narrow gap of 100 μm to 300 μm is maintained between the single crystal silicon wafer and the source electrode and the substrate surface on the side of the source electrode, and the single crystal silicon wafer is manipulated to scrape the organic semiconductor solution at a speed of 1 mm / s to 40 mm / s to form a uniform polymer film;

[0023] The spin coating method comprises:

[0024] The organic semiconductor solution is dropped onto the source electrode and the substrate surface on the side of the source electrode, and immediately rotated at a speed of 1000 rpm-3000 rpm to form a uniform polymer film;

[0025] The polymer film formed by the solution shearing processing method and the solution spin coating method is then placed in a vacuum environment to completely evaporate the solvent.

[0026] Preferably, the high temperature annealing process is to perform high temperature annealing on the prepared polymer semiconductor channel in an inert gas or vacuum atmosphere;

[0027] The reactive ion etching method directly uses the drain and the gate as masks for etching, the etching gas is oxygen, the flow rate is 20 sccm, the etching power is 10W to 20W, and the etching time is 180s to 210s.

[0028] Preferably, in the process of preparing the electrolyte layer, the dielectric material: room temperature ionic liquid: acetone are mixed in a mass ratio of 1:4:7, and dropped with a dispensing machine to cover and fill the gate, the sandwich structure, and the gap between the gate and the sandwich structure, and then placed in a vacuum environment to allow the acetone to completely evaporate to form a solid electrolyte layer.

[0029] Preferably, the dielectric material includes any one of poly(vinylidene fluoride-co-hexafluoropropylene) and polymethyl methacrylate-polystyrene-polymethyl methacrylate;

[0030] The room temperature ionic liquid includes any one of 1-ethyl-3-methylimidazoline bis(trifluoromethylsulfonyl imide), 1-butyl-3-imidazoline bis(trifluoromethylsulfonyl imide) and tributylmethylammonium bis(trifluoromethylsulfonyl imide).

[0031] Compared with the prior art, the present invention has at least the following beneficial effects:

[0032] This non-volatile multi-state electrochemical memory is a novel vertical structure electrochemical memory with a special device structure and a new polymer chain segment-ion interaction mechanism, which can realize multi-analog non-volatile storage on a single device. Compared with traditional two-terminal memories (memristors), this device has more accurate writing, low randomness, and a larger number of effective storage states; compared with traditional three-terminal floating gate transistor memories, this device also has more accurate and linear writing, simpler structure, and low processing cost; and compared with existing three-terminal electrochemical random access memories, the gate of this device does not need to be integrated with other devices to achieve intrinsic non-volatility. Its writing accuracy is similar to that of the most advanced three-terminal electrochemical memories, and its storage time is longer and more stable. For example, its storage stability is comparable to that of the most advanced heterogeneous two-terminal phase change memristors reported so far, while its writing accuracy and linearity are far higher than that, which has never been achieved by previous technologies. These advantages make the present invention very suitable for building high-performance storage and computing hardware, including artificial neural synapses as fully connected layers of neural networks, and as convolution kernels of convolutional neural networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the structure of the non-volatile multi-state electrochemical memory of the present invention;

[0034] Figure 2 A top-view electron microscope image of the nonvolatile multi-state electrochemical memory of the present invention;

[0035] Figure 3 This is a flow chart of the method for processing the non-volatile multi-state electrochemical memory of the present invention;

[0036] Figure 4 The device performance of the present invention is tested in an air atmosphere, wherein:

[0037] Figure (a) is the transfer characteristic curve; Figure (b) is the conductivity retention ability curve;

[0038] Figure (c) is a statistical diagram of the conductance continuous write / erase process controlled by voltage pulses with a storage state number of 1024;

[0039] Figure (d) is a statistical diagram of the conductance continuous write / erase process controlled by voltage pulses with a storage state number of 50;

[0040] Figure (e) is a statistical diagram of the conductance continuous write / erase process controlled by current pulses;

[0041] Figure (f) is a statistical diagram of the conductivity continuous writing process controlled by voltage pulses of different amplitudes. DETAILED DESCRIPTION

[0042] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0043] Example 1

[0044] See also Figure 1 The non-volatile multi-state electrochemical memory of the present invention includes a substrate 1 and a source electrode 2, a drain electrode 4, a gate electrode 5, and an electrolyte layer 6 disposed on the substrate 1. The source electrode 2 serves as a bottom electrode, the drain electrode 4 serves as a top electrode, and a polymer semiconductor channel 3 is disposed between the source electrode 2 and the drain electrode 4 to form an upright sandwich structure. The source electrode 2 and the drain electrode 4 in this sandwich structure are arranged at a 90-degree angle in space, as shown in FIG. Figure 2 As shown, gate 5 is positioned on the side of the sandwich structure, with a polymer semiconductor channel 3 disposed between gate 5 and the surface of substrate 1. Electrolyte layer 6 covers and fills gate 5, the sandwich structure, and the gap between the two structures from top to bottom. During use, gate 5 is connected to a write pulse circuit, and drain 4 is connected to a read pulse circuit. The read current is then used to calculate the stored conductance using Ohm's law.

[0045] In one possible embodiment, the polymer semiconductor channel 3 between the source electrode 2 and the drain electrode 4 has a length of 30 nm to 80 nm, a width of 10 μm to 300 μm, and a thickness of 10 μm to 300 μm; the polymer semiconductor channel 3 between the gate electrode 5 and the substrate 1 has a length of 10 μm to 300 μm, a width of 10 μm to 300 μm, and a thickness of 30 nm to 80 nm. The gate electrode 5 has a length of 10 μm to 300 μm and a width of 10 μm to 300 μm. At the same time, the source electrode 2, the drain electrode 4, and the gate electrode 5 all use polarizable inert electrodes, including but not limited to any one of gold (Au) and indium tin oxide (ITO). The polymer semiconductor channel 3 is formed using a highly crystalline polymer semiconductor material, including but not limited to any one of PDPP3T, PBTTT, PTBT-p, P(g2T-TT), and BBL.

[0046] The nonvolatile multi-state electrochemical memory of the present invention is a side-gate vertical transistor structure with an extremely high aspect ratio and a channel with highly ordered molecular chain segments. This makes it intrinsically nonvolatile to written gate voltage pulses or gate current pulses. Without the need for additional device integration, it can accurately (write noise σ / △GDS <7.5%) and linearly (write nonlinearity less than 0.2) write and long-term stable storage (>20,000 seconds) of multiple (>1024, 10-bit) nonvolatile conductivity states. The memory is simple to prepare and can be easily formed into large-scale crossbar arrays. By integrating multiple identical memories into an array, high-performance artificial neural networks (ANNs) and convolutional neural networks (CNNs) can be implemented in hardware to perform neuromorphic computing functions.

[0047] Example 2

[0048] See also Figure 3 The method for processing the non-volatile multi-state electrochemical memory of the present invention comprises the following steps:

[0049] Depositing metal on a clean substrate 1 to form a source electrode 2;

[0050] A polymer semiconductor channel 3 is prepared by depositing an organic semiconductor on the surface of the source electrode 2 and the substrate 1 on the side of the source electrode 2 using a solution processing method;

[0051] enhancing the channel crystallization of the polymer semiconductor channel 3 by a high temperature annealing process;

[0052] Depositing metal on the source electrode 2 and the polymer semiconductor channel 3 on the side of the source electrode 2 to form a drain electrode 4 and a gate electrode 5 respectively, with a gap between the drain electrode 4 and the gate electrode 5 in the horizontal direction;

[0053] Use reactive ion etching to open the polymer semiconductor channel 3 between the drain electrode 4 and the gate electrode 5;

[0054] The electrolyte layer 6 is prepared so that the electrolyte layer 6 covers and fills the gate 5, the sandwich structure, and the gap between the gate 5 and the sandwich structure from top to bottom, thereby completing the processing of the non-volatile multi-state electrochemical memory.

[0055] In one embodiment, the method for forming the polymer semiconductor channel 3 from an organic semiconductor requires the ability to form a uniform, pinhole-free, highly crystalline thin film, so the solution processing method includes any one of a solution shear processing method and a solution spin coating method;

[0056] Among them, solution shear processing methods include:

[0057] An organic semiconductor solution is dripped onto the front of the source electrode 2 and the surface of the substrate 1 on the side of the source electrode 2, which are preheated to a temperature of 30°C-50°C, so that a narrow gap of 100μm to 300μm is maintained between the single-crystalline silicon wafer and the source electrode 2 and the surface of the substrate 1 on the side of the source electrode 2. The single-crystalline silicon wafer is manipulated to scrape the organic semiconductor solution at a speed of 1mm / s to 40mm / s to form a uniform polymer film;

[0058] Spin coating methods include:

[0059] The organic semiconductor solution is dropped onto the source electrode 2 and the surface of the substrate 1 on the side of the source electrode 2, and immediately rotated at a speed of 1000 rpm-3000 rpm to form a uniform polymer film;

[0060] For both methods, the formed polymer film needs to be placed in a vacuum environment for 1 hour to completely evaporate the solvent.

[0061] In one embodiment, the high temperature annealing process is to perform high temperature annealing on the prepared polymer semiconductor channel 3 in an inert gas or vacuum atmosphere. The high temperature annealing process makes the organic semiconductor molecules more compact and orderly during annealing, thereby making the polymer semiconductor channel 3 have high crystallinity.

[0062] In order to remove excess organic semiconductors to open the channel, reactive ion etching is used to remove excess organic semiconductors. The reactive ion etching method directly uses the drain 4 and the gate 5 as masks for etching, without the need for an additional mask. The etching gas is oxygen with a flow rate of 20 sccm, an etching power of 10 W to 20 W, and an etching time of 180 s to 210 s.

[0063] In one embodiment, during the preparation of the electrolyte layer 6, the dielectric material: room temperature ionic liquid: acetone are mixed in a mass ratio of 1:4:7, and are added dropwise with a dispensing machine to cover and fill the gate 5, the sandwich structure, and the gap between the gate 5 and the sandwich structure, and then placed in a vacuum environment to allow the acetone to completely evaporate to form a solid electrolyte layer 6.

[0064] Furthermore, the dielectric material used has high ionic conductivity, high electrical and thermal stability, and should be a hydrophobic material to inhibit the effect of moisture on device performance in the air. The dielectric material includes but is not limited to poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF-HFP) or polymethyl methacrylate-polystyrene-polymethyl methacrylate (PMMA-PS-PMMA).

[0065] The room temperature ionic liquid used should be liquid at room temperature, have a wide electrochemical window (±2V vs. Ag / AgCl) and high ionic conductivity, and should be a hydrophobic ionic liquid to inhibit the influence of moisture on the device performance in the air. Room temperature ionic liquids include but are not limited to 1-ethyl-3-methylimidazolinium bis(trifluoromethylsulfonylimide) (EMIMTFSI), 1-butyl-3-imidazolinium bis(trifluoromethylsulfonylimide) (BMIMTFSI), and tributylmethylammonium bis(trifluoromethylsulfonylimide) (TBMATFSI).

[0066] Example 3

[0067] The specific processing method of the non-volatile multi-state electrochemical memory of the present invention is as follows:

[0068] Step 1: Clean the rigid Si / SiO2 or flexible substrate 1: Place the substrate 1 in soapy water or detergent, ultrapure water, acetone, and isopropyl alcohol for ultrasonic cleaning for 30 minutes each;

[0069] Step 2: The source electrode 2 is formed on the cleaned substrate 1 by mask vacuum evaporation, photolithography, or electron beam direct writing: first, 5 nm of chromium or titanium is deposited at 0.01 nm / s as an adhesion layer to enhance the bonding strength between the upper gold layer and the substrate, followed by 45 nm of gold deposited at 0.1 nm / s;

[0070] Step 3: Prepare a polymer semiconductor solution and stir overnight. For different crystalline polymer semiconductors, the preferred solvent and solution concentration are different, as follows:

[0071] PDPP3T: chlorobenzene / o-dichlorobenzene, 5mg / ml-10mg / ml, depending on the molecular weight;

[0072] PTBT-p: chlorobenzene, 18 mg / ml-24 mg / ml, depending on the molecular weight;

[0073] P(g2T-TT): chloroform, 5mg / ml-10mg / ml, depending on the molecular weight;

[0074] BBL: methanesulfonic acid, 5 mg / ml-10 mg / ml, depending on the molecular weight;

[0075] After sufficient dissolution, the polymer semiconductor channel 3 is deposited by solution shearing or spin coating. For the solution shearing method: an appropriate amount of organic semiconductor solution is added to the front end of the substrate preheated at a temperature of 30°C-50°C, and the slit width between the single crystal silicon wafer and the substrate is 100μm-300μm. The single crystal silicon wafer is manipulated to scrape the solution at a speed of 1mm / s-40mm / s to form a uniform organic semiconductor film, and its film thickness (i.e., channel length) depends on the substrate temperature (negative correlation), the slit width (positive correlation) and the scraping speed (basically positive correlation within this speed range); for the spin coating method: the solution is added dropwise onto the substrate and immediately rotated at a speed of 1000rpm-3000rpm for 60s to form a uniform polymer film.

[0076] To ensure a wide conductivity modulation range and high-speed writing, the film thickness should be as small as possible. However, when it is less than 30nm, the intrinsic resistance of the channel (off-state resistance) will be greatly reduced, which will compress the number of storable conductivity states. Therefore, the thickness of the polymer semiconductor film should be controlled between 30nm and 80nm. The formed film is then placed in a vacuum environment for 1 hour to completely evaporate the solvent.

[0077] Step 4: Place the film on a hot plate for annealing in a nitrogen or vacuum atmosphere to give the polymer chain segments sufficient energy to rearrange them and enhance their crystallization, thereby increasing the barrier to ion deintercalation and improving storage time and stability. For different crystalline polymer semiconductors, the preferred annealing temperature and time are different, as follows:

[0078] PDPP3T: 150℃, 15min-30min;

[0079] PTBT-p: 200°C, 1h;

[0080] P(g2T-TT): 140°C, 30 min;

[0081] BBL: 140℃, 2h;

[0082] Step 5: Use a mask to vacuum evaporate and deposit the drain electrode 4 and the gate electrode 5: deposit 10 nm of gold at a rate of 0.01 nm / s, and then deposit 60 nm of gold at a rate of 0.1 nm / s;

[0083] Step 6: Reactive ion etching (RIE) is used to directly use the drain electrode 4 as a mask to etch a channel pattern. The etching gas is oxygen, the gas flow rate is 20 sccm, the vacuum degree is 20 mbar, and the etching time is about 180s-210s.

[0084] Step 7: Mix the dielectric material, room temperature ionic liquid, and acetone in a mass ratio of 1:4:7 and drip the mixture onto the intersection of the source and drain electrodes using a dispensing machine, covering the channel and gate. Place the mixture in a vacuum environment for 1 hour to allow the acetone to completely evaporate and form a solid electrolyte layer. The preferred dielectric material is one of poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF-HFP) and polymethyl methacrylate-polystyrene-polymethyl methacrylate (PMMA-PS-PMMA); the preferred room temperature ionic liquid is one of 1-ethyl-3-methylimidazolinium bis(trifluoromethylsulfonyl imide) (EMIMTFSI), 1-butyl-3-imidazolinium bis(trifluoromethylsulfonyl imide) (BMIMTFSI), and tributylmethylammonium bis(trifluoromethylsulfonyl imide) (TBMATFSI).

[0085] The specific writing and reading methods of the nonvolatile multi-state electrochemical memory of the present invention are as follows:

[0086] When performing write / erase operations, Figure 4 As shown in Figures (c) to (f) in the figure, if the gate voltage writing method is used, a gate voltage pulse with an amplitude of ± (1.2 ~ 2.6) V and a width of 200μs-200ms is applied to the gate, wherein a negative gate voltage is used for writing and a positive gate voltage is used for erasing, so that ions are embedded in the channel or removed from the channel. The writing effect is as follows Figure 4 As shown in Figures (c) and (d), the memory has high writing accuracy and good linearity, where the gate voltage amplitude and the change in conductance have a good linear relationship, as shown in Figure 3. Figure 4 As shown in Figure (f) in the figure; if the gate current writing method is used, a gate current pulse with an amplitude of ±(20~200)nA and a width of 20ms is applied to the gate, the writing effect is as follows Figure 4 As shown in Figure (e), there is a one-to-one reconfigurable relationship between storage states;

[0087] When performing a read operation, the gate can be disconnected or grounded, and V is applied to the drain. read =0.01V~0.1V reading voltage pulse, obtain reading current I read , according to Ohm's law G=I read / V read The stored conductance value is calculated.

[0088] Figure 4Figure (a) shows the transfer characteristic curve, including the channel current-gate voltage and gate current-gate voltage relationships, which are all centrosymmetrical, indicating that the memory has intrinsic non-volatility. Figure (b) shows the conductivity retention capability curve, showing that multiple different conductivity states can be maintained for a long time. The inset shows that each conductivity state can be maintained for more than 20,000 seconds with small conductivity drift. Figure (c) shows the statistical diagram of the continuous write / erase process of the conductivity controlled by voltage pulses. The number of stored states is 1024, showing that compared with existing electrochemical memories, it has a large conductivity modulation range and a large number of valid states. Figure (d) also shows the statistical diagram of the continuous write / erase process of the conductivity controlled by voltage pulses. The number of stored states is 50, showing good write linearity and high write accuracy. Figure (e) shows the statistical diagram of the continuous write / erase process of the conductivity controlled by current pulses. It can be seen that there is a one-to-one reconfigurable relationship between the storage states. After 2500 consecutive write and erase cycles, the memory performance remains almost unchanged. Figure (f) is a statistical diagram of the continuous writing process of conductance controlled by voltage pulses of different amplitudes. It can be seen that the change in conductance is linearly related to the pulse amplitude. Therefore, during neural network training, the change in conductance (synaptic weight) can be accurately controlled by controlling the pulse amplitude, thereby improving network training efficiency.

[0089] The working mechanism of the memory of the present invention is as follows: when the gate voltage pulse amplitude is higher than a certain threshold, the driving force is large, the ions in the solid electrolyte undergo electromigration, overcome a certain potential barrier, enter the crystalline phase region where the polymer molecules are tightly arranged and regularly, and are embedded therein. When the gate voltage is removed, the non-volatility of the storage is guaranteed by two necessary conditions: (1) the polymer chain segments are arranged very regularly and tightly, and have a strong interaction force with the ions embedded in the channel, so that the ion deintercalation needs to overcome a large potential barrier; (2) for general organic electrochemical transistor devices, the reason for the volatility of their conductivity is that after the gate voltage is removed, the positive and negative ion charges in the channel and the electrolyte are unbalanced, thereby forming a reverse electric field that causes ion deintercalation. Since the channel depth-to-length ratio of the transistor memory is extremely large (d / L>2000), the potential distribution along the depth direction of the channel becomes extremely flat, resulting in a smaller reverse electric field, making it difficult for ions to overcome the potential barrier and deintercalate. These two conditions ensure the non-volatility of the conductivity, forming a long-term memory of synaptic weights similar to that of neural synapses, and realizing stable non-volatile storage. At the same time, because this memory uses an intrinsic polymer semiconductor as the channel (channel) and has an extremely high channel depth-to-length ratio, its conductivity modulation range is very large (>10 times). This value is significantly better than that of existing electrochemical memories, making it possible to store a higher number of effective conductivity states.

[0090] The performance indicators of a single memory of the present invention are as follows:

[0091] ① Storage data volume: the number of distinguishable conductivity states is greater than 1024 (10-bit), and the dynamic range of stored conductivity is greater than 10 times;

[0092] ② Storage stability: Conductivity state retention time > 20,000s, conductivity drift γ < 0.008, where γ meets the energy condition: (t / t0) γ =R t / R0, R and R0 are the resistance values of the memory channel at time t0 and time t respectively;

[0093] ③ Storage accuracy: nonlinearity of conductivity writing <0.2, writing signal-to-noise ratio (△G DS / σ) 2 >179, where △G DS is the average value of the conductance update during writing, σ is the standard deviation, and the conductance update amount has a good linear relationship with the pulse amplitude;

[0094] ④ Write endurance: can withstand at least 2000 write and erase events without obvious performance degradation.

[0095] In addition to the above performance indicators, the memory of the present invention has the following characteristics:

[0096] ① It can be processed by solution method, which is simple and low in cost;

[0097] ② It is easy to build a crossbar array, which can be expanded into memory arrays and neural networks;

[0098] ③ Since both the channel material and the electrolyte have intrinsic flexibility, flexible or stretchable devices can be prepared;

[0099] ④ Relying on intrinsic non-volatility for storage, it is possible to achieve polymorphic non-volatile storage with high integration without the need to integrate with other devices or circuits (such as field-effect transistors, switching circuits) to force the gate and channel to open.

[0100] ⑤ Gate current pulses or gate voltage pulses can be used for writing and erasing respectively. When current pulses are used for writing and erasing, a reconfigurable storage state can be obtained, and writing and erasing are almost completely linearly symmetrical.

[0101] The above description is merely a preferred embodiment of the present invention and is not intended to impose any limitation on the technical solution of the present invention. Those skilled in the art should understand that, without departing from the spirit and principles of the present invention, the technical solution can also be subjected to several simple modifications and replacements, and these modifications and replacements are also within the scope of protection covered by the claims.

Claims

1. A nonvolatile multi-state electrochemical memory, characterized in that: The invention comprises a substrate (1) and a source electrode (2), a drain electrode (4), a gate electrode (5) and an electrolyte layer (6) arranged on the substrate (1); the source electrode (2) serves as a bottom electrode, the drain electrode (4) serves as a top electrode, and a polymer semiconductor channel (3) is arranged between the source electrode (2) and the drain electrode (4) to form a positive sandwich structure; the gate electrode (5) is arranged on the side of the sandwich structure, and the polymer semiconductor channel (3) is arranged between the gate electrode (5) and the surface of the substrate (1); the electrolyte layer (6) covers and fills the gate electrode (5), the sandwich structure and the gap between the gate electrode (5) and the sandwich structure from top to bottom; the gate electrode (5) is connected to a write pulse circuit, and the drain electrode (4) is connected to a read pulse circuit, and a storage conductance value is obtained by obtaining a read current and calculating it according to Ohm's law.

2. The nonvolatile multi-state electrochemical memory according to claim 1, characterized in that: The source electrode (2) and the drain electrode (4) in the sandwich structure are arranged to cross each other at 90 degrees in space.

3. The nonvolatile multi-state electrochemical memory according to claim 2, characterized in that: The polymer semiconductor channel (3) between the source electrode (2) and the drain electrode (4) has a length of 30 nm to 80 nm, a width of 10 μm to 300 μm, and a thickness of 10 μm to 300 μm; the polymer semiconductor channel (3) between the gate electrode (5) and the substrate (1) has a length of 10 μm to 300 μm, a width of 10 μm to 300 μm, and a thickness of 30 nm to 80 nm; the gate electrode (5) has a length of 10 μm to 300 μm, and a width of 10 μm to 300 μm.

4. The nonvolatile multi-state electrochemical memory according to claim 1, wherein: The source electrode (2), the drain electrode (4) and the gate electrode (5) all adopt polarizable inert electrodes, and the polarizable inert electrodes include any one of gold and indium tin oxide.

5. The nonvolatile multi-state electrochemical memory according to claim 1, wherein: The polymer semiconductor channel (3) is formed by using a polymer semiconductor material with high crystallinity, and the polymer semiconductor material with high crystallinity includes any one of PDPP3T, PBTTT, PTBT-p, P(g2T-TT) and BBL.

6. A method for processing a nonvolatile multi-state electrochemical memory according to any one of claims 1 to 5, characterized in that: The following steps are involved: Depositing metal on a clean substrate (1) to form a source electrode (2); Depositing an organic semiconductor on the surface of the source electrode (2) and the substrate (1) on the side of the source electrode (2) using a solution processing method to prepare a polymer semiconductor channel (3); enhancing the channel crystallization of the polymer semiconductor channel (3) through a high temperature annealing process; Depositing metal on the source electrode (2) and the polymer semiconductor channel (3) on the side of the source electrode (2) to form a drain electrode (4) and a gate electrode (5) respectively, with a gap between the drain electrode (4) and the gate electrode (5) in the horizontal direction; Opening the polymer semiconductor channel (3) between the drain electrode (4) and the gate electrode (5) using reactive ion etching; An electrolyte layer (6) is prepared so that the electrolyte layer (6) covers and fills the gate (5), the sandwich structure, and the gap between the gate (5) and the sandwich structure from top to bottom, thereby completing the processing of the non-volatile multi-state electrochemical memory.

7. The processing method according to claim 6, characterized in that: The solution processing method includes any one of a solution shear processing method and a solution spin coating method; The solution shearing processing method includes: An organic semiconductor solution is dripped onto the front end of the surface of the source electrode (2) and the substrate (1) on the side of the source electrode (2) preheated to a temperature of 30°C-50°C, so that a slit with a width of 100 μm to 300 μm is maintained between the single crystal silicon wafer and the source electrode (2) and the surface of the substrate (1) on the side of the source electrode (2), and the single crystal silicon wafer is manipulated to scrape the organic semiconductor solution at a speed of 1 mm / s to 40 mm / s to form a uniform polymer film; The spin coating method comprises: The organic semiconductor solution is dropped onto the surface of the source electrode (2) and the substrate (1) on the side of the source electrode (2), and immediately rotated at a speed of 1000 rpm to 3000 rpm to form a uniform polymer film; The polymer film formed by the solution shearing processing method and the solution spin coating method is then placed in a vacuum environment to completely evaporate the solvent.

8. The processing method according to claim 6, characterized in that: The high temperature annealing process is to perform high temperature annealing on the prepared polymer semiconductor channel (3) in an inert gas or vacuum atmosphere; The reactive ion etching method directly uses the drain (4) and the gate (5) as masks for etching, the etching gas is oxygen, the flow rate is 20 sccm, the etching power is 10W to 20W, and the etching time is 180s to 210s.

9. The processing method according to claim 6, characterized in that: In the process of preparing the electrolyte layer (6), dielectric material: room temperature ionic liquid: acetone are mixed in a mass ratio of 1:4:7, and dropwise added using a dispensing machine to cover and fill the gate (5), the sandwich structure, and the gap between the gate (5) and the sandwich structure. The mixture is then placed in a vacuum environment to allow the acetone to completely volatilize to form a solid electrolyte layer (6).

10. The processing method according to claim 9, characterized in that: The dielectric material includes any one of poly(vinylidene fluoride-co-hexafluoropropylene) and polymethyl methacrylate-polystyrene-polymethyl methacrylate; The room temperature ionic liquid includes any one of 1-ethyl-3-methylimidazoline bis(trifluoromethylsulfonyl imide), 1-butyl-3-imidazoline bis(trifluoromethylsulfonyl imide) and tributylmethylammonium bis(trifluoromethylsulfonyl imide).

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