A monolithically integrated GaN / Ga2O3 cascode-enhanced single-particle burnout-resistant device and its preparation method

Abstract

The invention discloses a monolithically integrated GaN / Ga2O3 cascode enhanced single particle burnout resistant device, comprising a Ga2O3FET structure and a GaN HEMT structure arranged on the right side of the Ga2O3FET structure, wherein the Ga2O3FET structure and the GaN HEMT structure are both arranged on a substrate, and a first passivation layer is arranged between the GaN HEMT structure and the Ga2O3FET structure; the Ga2O3FET structure comprises a Ga2O3 buffer layer and a Ga2O3 channel layer from bottom to top, and a first source, a first gate and a first drain are arranged from left to right above the Ga2O3 channel layer; the GaN HEMT structure comprises an AlN nucleation layer, a GaN buffer layer and an AlGaN barrier layer from bottom to top, and a second source, a p-GaN layer and a second drain are arranged from left to right above the AlGaN barrier layer, and a second gate is arranged above the p-GaN layer. The present invention adopts the above structure to realize a novel Ga2O3 enhanced device, reduces the weight and complexity of the aerospace system, increases the reliability of the device, and improves the single particle burnout threshold voltage of the device under aerospace radiation environment application.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a monolithically integrated GaN / Ga2O3 cascode-enhanced single-particle burnout resistant device and a preparation method thereof. Background Art

[0002] Semiconductor devices with high power density and high energy conversion are used in power electronic systems in aerospace for power conversion, circuit control under high voltage and high current, and other equipment. With the increasing energy consumption, aerospace power systems that use hydraulic energy, gas energy, and mechanical energy as energy have problems such as large volume, high fuel consumption, and low energy conversion efficiency. Therefore, the development of power devices that meet the high frequency, high efficiency, high power density, and high reliability of switching power supplies is an effective way to promote the application and development of new power systems in aerospace that use electricity as the main environmentally friendly energy. With the continuous updating and development of power semiconductor device technology, the materials of power electronic systems have been updated from the first generation of silicon-based materials to the second generation of gallium arsenide materials, which have fundamentally changed the basic properties of devices and materials. Since the early 1990s, in order to meet the requirements of high frequency, wide bandgap, high efficiency, and high power devices, the research focus of power semiconductors has begun to shift to wide bandgap semiconductor devices. Among them, gallium oxide Ga2O3, as a new representative wide bandgap semiconductor material, has many advantages due to its wider bandgap width, low intrinsic carrier concentration, higher critical electric field strength, and faster electron saturation velocity. First, it has a higher reverse blocking voltage and faster switching frequency. Second, it has better radiation resistance and a wider temperature operating range. Third, it has lower input capacitance and lower on-resistance. There are high-energy particles in the natural radiation environment where aerospace systems work. These particles can penetrate the system and cause serious single-particle events. The most important failure mode is the single-particle burnout of power devices. The single-particle burnout threshold voltage parameter of power devices can measure the device's resistance to radiation single particles. It refers to the maximum reverse voltage value that the device can maintain without burning when it is in the reverse high-voltage working mode when it is turned off.

[0003] Single particle burnout has become a key technology that restricts the development of aerospace radiation resistance. Mature silicon-based devices require very complex radiation resistance reinforcement technology, which will seriously increase the complexity and weight of the system and cannot meet the development needs of system miniaturization and integration. The mainstream Ga2O3 transistor device achieves enhancement mode by relying on non-in-situ growth of P-type NiO xThese solutions use MIS structures and etching processes, which will introduce total dose problems and reliability problems caused by interface defects. Although the single-particle burnout of the third-generation wide-bandgap device has a certain research status, the single-particle burnout threshold voltage of all material devices is very low and far lower than the breakdown voltage of the device itself, which has serious reliability problems. It is urgent to develop a new transistor structure with enhanced single-particle burnout resistance. Summary of the invention

[0004] The purpose of the present invention is to provide a monolithically integrated GaN / Ga2O3 cascode enhanced single particle burnout resistance device and a preparation method thereof, so as to realize a novel Ga2O3 enhanced device, reduce the weight and complexity of the aerospace system, increase the reliability of the device, and improve the single particle burnout threshold voltage of the device under the application of the aerospace radiation environment.

[0005] To achieve the above object, the present invention provides a monolithically integrated GaN / Ga2O3 cascode enhanced single particle burnout resistant device, comprising a Ga2O3 FET structure and a GaN HEMT structure arranged on the right side of the Ga2O3 FET structure, wherein the Ga2O3 FET structure and the GaN HEMT structure are both arranged on a substrate, and a first passivation layer is arranged between the GaN HEMT structure and the Ga2O3 FET structure;

[0006] The Ga2O3 FET structure includes a Ga2O3 buffer layer and a Ga2O3 channel layer from bottom to top, and a first source electrode, a first gate electrode and a first drain electrode are arranged above the Ga2O3 channel layer from left to right;

[0007] The GaN HEMT structure includes an AlN nucleation layer, a GaN buffer layer and an AlGaN barrier layer from bottom to top, a second source electrode, a p-GaN layer and a second drain electrode are arranged above the AlGaN barrier layer from left to right, and a second gate electrode is arranged above the p-GaN layer;

[0008] The second drain is connected to the first source, and the second source is connected to the first gate.

[0009] Preferably, the first source and the second drain are connected via an inner interconnect metal layer, the first gate and the second source are connected via an outer interconnect metal layer, and a second passivation layer is provided between the outer interconnect metal layer and the inner interconnect metal layer.

[0010] Preferably, the second gate serves as the gate of a cascode structure enhanced power device, the second source serves as the source of the cascode structure enhanced power device, and the first drain serves as the drain of the cascode structure enhanced power device.

[0011] Preferably, the substrate is made of sapphire or Si or SiC or GaN or Ga2O3 bulk material.

[0012] Preferably, the second source and the second drain adopt a metal layer combination of Ti / Al or Ti / Al / Ni / Au or Ti / Al / Mo / Au, and the second gate adopts a metal layer combination of Ni / Au / Ni or Ni / Au or W / Au or Mo / Au.

[0013] Preferably, the first passivation layer and the second passivation layer are made of Si3N4 or Al2O3 or SiO2 or HfO2.

[0014] A method for preparing a monolithically integrated GaN / Ga2O3 cascode enhanced single-particle burnout resistant device comprises the following steps:

[0015] (1) cleaning and pre-treating the substrate surface to eliminate surface dangling bonds, and heat treating at 900°C-1200°C in a H2 atmosphere reaction chamber to remove surface contaminants;

[0016] (2) The heat-treated substrate is subjected to an MOCVD process to deposit Ga2O3 with a thickness of 100nm-1000nm as a buffer layer for the Ga2O3FET structure;

[0017] (3) Ga2O3 with a thickness of 100nm-1000nm is deposited on the Ga2O3 buffer layer by MOCVD process as the channel layer of the device, and the doping concentration is 1×10 15 cm -3 -1×10 20 cm -3 Si;

[0018] (4) growing a mask layer on the Ga2O3 channel layer, performing photolithography and etching on the mask layer, and exposing a regional window of the GaN HEMT structure on the substrate;

[0019] (5) depositing an AlN nucleation layer with a thickness of 50 nm to 100 nm on the regional window of the GaN HEMT structure using a MOCVD process;

[0020] (6) depositing a GaN buffer layer with a thickness of 0.1 μm to 10 μm on the AlN nucleation layer using a MOCVD process;

[0021] (7) depositing an AlGaN barrier layer with a thickness of 10 nm to 50 nm on the GaN buffer layer using a MOCVD process;

[0022] (8) A p-GaN layer with a thickness of 50 nm to 500 nm is deposited on the AlGaN barrier layer using the MOCVD process and a doping concentration of 1×10 16 cm -3 -1×10 20 cm -3 Mg;

[0023] (9) making a photolithography mask on the p-GaN layer, and etching away the p-GaN layer outside the gate region;

[0024] (10) growing a mask layer on the Ga2O3 channel layer, exposing source and drain windows by photolithography and etching, and implanting Si ions into the source and drain regions at high temperature using an ion implantation process in the source and drain windows;

[0025] (11) performing photolithography on the AlGaN barrier layer, and depositing a second source electrode and a second drain electrode by metal evaporation or magnetron sputtering, and performing high temperature annealing;

[0026] (12) performing photolithography on the Ga2O3 channel layer, and depositing source and drain metals in the first source and first drain windows by metal evaporation or magnetron sputtering, and performing high temperature annealing;

[0027] (13) performing photolithography on the Ga2O3 channel layer and the p-GaN layer, and depositing gate metals respectively by metal evaporation or magnetron sputtering;

[0028] (14) placing the epitaxial wafer after the above steps into a PECVD reaction chamber to deposit a passivation layer;

[0029] (15) performing photolithography and etching on the passivation layer to form gate, source and drain contact holes, and completing the metal interconnection between the second source of the GaN HEMT and the first gate of the Ga2O3 FET;

[0030] (16) placing the epitaxial wafer after the above steps into a PECVD reaction chamber to deposit a passivation layer;

[0031] (17) Photolithography and etching are performed on the passivation layer to form gate, source and drain contact holes, and the metal interconnection between the second drain of the GaN HEMT and the first source of the Ga2O3 FET is completed.

[0032] Therefore, the present invention adopts a monolithically integrated GaN / Ga2O3 cascode enhanced single particle burnout resistance device and a preparation method thereof, which has the following beneficial effects:

[0033] First, low-voltage enhancement-mode GaN HEMT and high-voltage depletion-mode Ga2O3 FET are monolithically heterogeneously integrated to form a new type of Cascode structure enhancement-mode power device, which is a new type of enhancement-mode Ga2O3 material device.

[0034] The second is to use p-GaN enhanced-mode GaN HEMT as the front-end device. Since GaN HEMT devices do not have a MIS structure layer corresponding to the dielectric, no additional total dose problem will be introduced;

[0035] The third is the high breakdown voltage characteristic of Ga2O3 material. At the same time, GaN is also a wide bandgap material, which increases the reliability of the device as a whole and improves the single-particle burnout threshold voltage of the device under aerospace radiation environment.

[0036] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a structural diagram of the Cascode structure enhanced power device of the present invention;

[0038] Figure 2 It is a flow chart of manufacturing a cascode structure enhanced power device according to the present invention. DETAILED DESCRIPTION

[0039] Figure 1 is a structural diagram of the Cascode structure enhanced power device of the present invention, such as Figure 1As shown, the present invention provides a monolithically integrated GaN / Ga2O3 cascode enhanced single-particle burnout resistant device, including a Ga2O3 FET structure and a GaN HEMT structure arranged on the right side of the Ga2O3 FET structure, wherein the Ga2O3 FET structure and the GaN HEMT structure are both arranged on a substrate, wherein the substrate is made of sapphire or Si or SiC or GaN or Ga2O3 bulk material, and the GaN HEMT structure and the Ga2O3 A first passivation layer is arranged between the FET structures; the Ga2O3FET structure includes a Ga2O3 buffer layer and a Ga2O3 channel layer from bottom to top, and a first source (Source1), a first gate (Gate1) and a first drain (Drain1) are arranged from left to right above the Ga2O3 channel layer; the GaNHEMT structure includes an AlN nucleation layer, a GaN buffer layer and an AlGaN barrier layer from bottom to top, and a second source (Source2), a p-GaN layer and a second drain (Drain2) are arranged from left to right above the AlGaN barrier layer, and a second gate (Gate2) is arranged above the p-GaN layer; the second drain is connected to the first source, and the second source is connected to the first gate. The first source and the second drain are connected through an inner interconnect metal layer, the first gate and the second source are connected through an outer interconnect metal layer, and a second passivation layer is arranged between the outer interconnect metal layer and the inner interconnect metal layer.

[0040] The second gate is used as the gate of the cascode structure enhanced power device, the second source is used as the source of the cascode structure enhanced power device, and the first drain is used as the drain of the cascode structure enhanced power device. The second source and the second drain are made of a metal layer combination of Ti / Al or Ti / Al / Ni / Au or Ti / Al / Mo / Au, and the second gate is made of a metal layer combination of Ni / Au / Ni or Ni / Au or W / Au or Mo / Au. The first passivation layer and the second passivation layer are made of Si3N4 or Al2O3 or SiO2 or HfO2.

[0041] Figure 2 The flowchart of the present invention for making a Cascode structure enhanced power device is shown in the figure. The method for making a monolithically integrated GaN / Ga2O3 Cascode enhanced single particle burnout resistant device comprises the following steps:

[0042] (1) cleaning and pre-treating the substrate surface to eliminate surface dangling bonds, and heat treating at 900°C-1200°C in a H2 atmosphere reaction chamber to remove surface contaminants;

[0043] (2) The heat-treated substrate is subjected to an MOCVD process to deposit Ga2O3 with a thickness of 100nm-1000nm as a buffer layer for the Ga2O3FET structure;

[0044] (3) Ga2O3 with a thickness of 100nm-1000nm is deposited on the Ga2O3 buffer layer by MOCVD process as the channel layer of the device, and the doping concentration is 1×10 15 cm -3 -1×10 20 cm -3 Si;

[0045] (4) growing a mask layer on the Ga2O3 channel layer, performing photolithography and etching on the mask layer, and exposing a regional window of the GaN HEMT structure on the substrate;

[0046] (5) depositing an AlN nucleation layer with a thickness of 50 nm to 100 nm on the regional window of the GaN HEMT structure using a MOCVD process;

[0047] (6) depositing a GaN buffer layer with a thickness of 0.1 μm to 10 μm on the AlN nucleation layer using a MOCVD process;

[0048] (7) depositing an AlGaN barrier layer with a thickness of 10 nm to 50 nm on the GaN buffer layer using a MOCVD process;

[0049] (8) A p-GaN layer with a thickness of 50 nm to 500 nm is deposited on the AlGaN barrier layer using the MOCVD process and a doping concentration of 1×10 16 cm -3 -1×10 20 cm -3 Mg;

[0050] (9) making a photolithography mask on the p-GaN layer, and etching away the p-GaN layer outside the gate region;

[0051] (10) growing a mask layer on the Ga2O3 channel layer, exposing source and drain windows by photolithography and etching, and implanting Si ions into the source and drain regions at high temperature using an ion implantation process in the source and drain windows;

[0052] (11) performing photolithography on the AlGaN barrier layer, and depositing a second source electrode and a second drain electrode by metal evaporation or magnetron sputtering, and performing high temperature annealing;

[0053] (12) performing photolithography on the Ga2O3 channel layer, and depositing source and drain metals in the first source and first drain windows by metal evaporation or magnetron sputtering, and performing high temperature annealing;

[0054] (13) performing photolithography on the Ga2O3 channel layer and the p-GaN layer, and depositing gate metals respectively by metal evaporation or magnetron sputtering;

[0055] (14) placing the epitaxial wafer after the above steps into a PECVD reaction chamber to deposit a passivation layer;

[0056] (15) performing photolithography and etching on the passivation layer to form gate, source and drain contact holes, and completing the metal interconnection between the second source of the GaN HEMT and the first gate of the Ga2O3 FET;

[0057] (16) placing the epitaxial wafer after the above steps into a PECVD reaction chamber to deposit a passivation layer;

[0058] (17) Photolithography and etching are performed on the passivation layer to form gate, source and drain contact holes, and the metal interconnection between the second drain of the GaN HEMT and the first source of the Ga2O3 FET is completed.

[0059] The technical solution of the present invention is further described below through the accompanying drawings and embodiments.

[0060] Example 1

[0061] A monolithically integrated GaN / Ga2O3 cascode enhanced single event burnout resistant device was fabricated with gallium oxide Ga2O3 as substrate and a Ga2O3 FET channel layer thickness of 500nm.

[0062] Step 1: pre-treat the surface of the gallium oxide Ga2O3 substrate to eliminate dangling bonds.

[0063] 1.1) Soak the Ga2O3 substrate in HF acid solution for 1 min, then sequentially place it in acetone solution, anhydrous ethanol solution and deionized water for ultrasonic cleaning for 10 min each, and blow dry the cleaned Ga2O3 substrate with nitrogen;

[0064] 1.2) The cleaned and dried substrate is heat treated at 1000°C in a H2 atmosphere reaction chamber to remove surface contaminants.

[0065] Step 2, making a Ga2O3 buffer layer.

[0066] The pretreated Ga2O3 substrate was placed in a metal organic chemical vapor deposition (MOCVD) system, and the pressure of the reaction chamber was set to 30 Torr and the temperature to 900°C. At the same time, a Ga source with a flow rate of 40 μmol / min and an oxygen with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 1 μm thick Ga2O3 buffer layer on the Ga2O3 substrate layer.

[0067] Step 3: fabricate a Ga2O3 channel layer.

[0068] At the same time, a Ga source with a flow rate of 20 μmol / min and an oxygen with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 500 nm thick Ga2O3 channel layer on the Ga2O3 buffer layer.

[0069] Step 4: Make a mask and a GaN active area.

[0070] At the same time, silane with a flow rate of 2000sccm and oxygen with a flow rate of 3000sccm are introduced into the reaction chamber to grow a 1μm SiO2 mask layer on the Ga2O3 buffer layer, and then placed in a RIE etching reaction chamber to expose the active area of ​​the GaN HEMT device.

[0071] Step 5: Prepare an AlN nucleation layer.

[0072] The epitaxial wafer that has completed the above process is placed into the MOCVD system under the same conditions as before, and Al source with a flow rate of 40 μmol / min, hydrogen with a flow rate of 1200 sccm, and ammonia with a flow rate of 3000 sccm are introduced into the chamber at the same time to grow a 50nm thick AlN nucleation layer on the gallium oxide Ga2O3.

[0073] Step 6: fabricate a GaN buffer layer.

[0074] At the same time, a Ga source with a flow rate of 40 μmol / min, a hydrogen with a flow rate of 1200 sccm, and an ammonia with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 1 μm thick GaN buffer layer on the AlN nucleation layer.

[0075] Step 7: fabricate an AlGaN barrier layer.

[0076] At the same time, an Al source with a flow rate of 40 μmol / min, a Ga source with a flow rate of 40 μmol / min, a hydrogen with a flow rate of 1200 sccm, and an ammonia with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 10 nm thick AlGaN barrier layer on the GaN buffer layer.

[0077] Step 8: fabricating a p-GaN layer.

[0078] At the same time, a Ga source with a flow rate of 40 μmol / min, a hydrogen with a flow rate of 1200 sccm, and an ammonia with a flow rate of 3000 sccm were introduced into the reaction chamber to grow an 80 nm thick GaN buffer layer on the AlGaN barrier layer with a doping concentration of 1×10 19 cm -3 A mask is made to etch away the p-GaN layer outside the gate area.

[0079] Step 9, ion implantation into the Ga2O3 channel source and drain regions.

[0080] The epitaxial wafer that has completed the above process is placed in RIE and the mask is removed. A new mask is grown and the source and drain regions of the Ga2O3 channel are selected for Si ion implantation. The energy is 100 keV and the total dose is 1×10 15 cm -2 After ion implantation, the mask is removed and annealing is performed at 900°C.

[0081] Step 10: fabricate the source and drain of the GaN HEMT.

[0082] A mask is made on the AlGaN barrier layer to form source and drain windows, and then it is placed in a metal evaporation reaction chamber, and the pressure of the reaction chamber is maintained at 8.8×10 -2 Pa, using aluminum and titanium targets with a purity of 99.999%, deposited Ti / Al metal as the source in the source window, and then annealed at a high temperature of 860°C for 30s.

[0083] Step 11, make Ga2O3 FET source and drain.

[0084] A mask is made on the Ga2O3 channel layer to form source and drain windows, and then it is placed in a metal evaporation reaction chamber, and the pressure of the reaction chamber is maintained at 8.8×10 -2 Pa, using titanium and gold targets with a purity of 99.999%, deposited Ti / Au metal as the source in the source window, and then annealed at a high temperature of 480°C.

[0085] Step 12, fabricate Ga2O3 FET and GaN HEMT gates.

[0086] Masks were made on the Ga2O3 channel layer and the p-GaN layer to form source and drain windows, and then placed in a metal evaporation reaction chamber with a pressure of 8.8×10 -2 Pa, using nickel and gold targets with a purity of 99.999%, metal Ni / Au / Ni with a thickness of 45nm / 200nm / 200nm was deposited on the drain window and the gate window respectively as the gate.

[0087] Step 13: making a passivation layer.

[0088] The sample after the above steps is placed in a plasma chemical vapor deposition (PECVD) reaction chamber, and a 50nm thick Si3N4 passivation layer is deposited at a high temperature of 400°C.

[0089] Step 14: Make contact holes and metal.

[0090] The source and gate are photolithographically processed and etched to form contact holes for the gate and source to complete metal interconnection.

[0091] Step 15: making a passivation layer.

[0092] The sample after the above steps is placed in a plasma chemical vapor deposition (PECVD) reaction chamber to deposit a 100 nm thick Al2O3 passivation layer.

[0093] Step 16, making contact holes and metal.

[0094] The source and drain are photolithographically etched to form contact holes for the drain and source to complete the device fabrication.

[0095] Example 2

[0096] A monolithically integrated GaN / Ga2O3 cascode-enhanced single-event burnout-resistant device was fabricated with sapphire as substrate and a Ga2O3 FET channel layer thickness of 300nm.

[0097] Step 1: pre-treat the surface of the sapphire substrate to eliminate dangling bonds.

[0098] 1.1) Soak the sapphire substrate in HF acid solution for 1 min, then sequentially place it in acetone solution, anhydrous ethanol solution and deionized water for ultrasonic cleaning for 10 min each, and blow dry the cleaned sapphire substrate with nitrogen;

[0099] 1.2) The cleaned and dried substrate is heat treated at 1000°C in a H2 atmosphere reaction chamber to remove surface contaminants.

[0100] Step 2: Prepare a Ga2O3 buffer layer.

[0101] The pretreated sapphire substrate was placed in a metal organic chemical vapor deposition (MOCVD) system, and the pressure of the reaction chamber was set to 30 Torr and the temperature to 900°C. At the same time, a Ga source with a flow rate of 50 μmol / min and an oxygen with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 2 μm thick buffer layer on the sapphire substrate layer.

[0102] Step three: fabricate a Ga2O3 channel layer.

[0103] At the same time, a Ga source with a flow rate of 20 μmol / min and an oxygen with a flow rate of 2000 sccm were introduced into the reaction chamber to grow a 300 nm thick Ga2O3 channel layer on the Ga2O3 buffer layer.

[0104] Step 4: Make a mask and a GaN active area.

[0105] At the same time, silane with a flow rate of 3000 sccm and oxygen with a flow rate of 3000 sccm are introduced into the reaction chamber, and a 2μm SiO2 mask layer is grown on the Ga2O3 buffer layer, and is placed in a RIE etching reaction chamber to expose the active area of ​​the GaN HEMT device.

[0106] Step five: preparing an AlN nucleation layer.

[0107] The epitaxial wafer that has completed the above process is placed into the MOCVD system with the same conditions as before, and Al source with a flow rate of 50 μmol / min, hydrogen with a flow rate of 1200 sccm, and ammonia with a flow rate of 3000 sccm are introduced into the chamber at the same time to grow a 60nm thick AlN nucleation layer on the gallium oxide Ga2O3.

[0108] Step six, making a GaN buffer layer.

[0109] At the same time, a Ga source with a flow rate of 40 μmol / min, a hydrogen with a flow rate of 2000 sccm, and an ammonia with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 2 μm thick GaN buffer layer on the AlN nucleation layer.

[0110] Step seven: fabricating an AlGaN barrier layer.

[0111] At the same time, an Al source with a flow rate of 50 μmol / min, a Ga source with a flow rate of 50 μmol / min, a hydrogen with a flow rate of 2000 sccm, and an ammonia with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 20 nm thick AlGaN barrier layer on the GaN buffer layer.

[0112] Step eight, making a p-GaN layer.

[0113] At the same time, a Ga source with a flow rate of 40 μmol / min, a hydrogen with a flow rate of 1200 sccm, and an ammonia with a flow rate of 3000 sccm were introduced into the reaction chamber to grow a 100 nm thick p-GaN on the AlGaN barrier layer with a doping concentration of 5×10 19 cm -3 A mask is made to etch away the p-GaN layer outside the gate area.

[0114] Step nine, ion implantation into the Ga2O3 channel source and drain regions.

[0115] The epitaxial wafer that has completed the above process is placed in RIE and the mask is removed. A new mask is grown and the source and drain regions of the Ga2O3 channel are selected for Si ion implantation. The energy is 120 keV and the total dose is 1×10 15 cm -2 After ion implantation, the mask is removed and high temperature annealing is performed at 920°C.

[0116] Step 10: Make the source and drain of GaN HEMT.

[0117] A mask is made on the AlGaN barrier layer to form source and drain windows, and then it is placed in a metal evaporation reaction chamber, and the pressure of the reaction chamber is maintained at 8.8×10 -2 Pa, using aluminum and titanium targets with a purity of 99.999%, deposited Ti / Al metal as the source in the source window, and then annealed at a high temperature of 875°C for 30s.

[0118] Step 11: Make the Ga2O3 FET source and drain.

[0119] A mask is made on the Ga2O3 channel layer to form source and drain windows, and then it is placed in a metal evaporation reaction chamber, and the pressure of the reaction chamber is maintained at 8.8×10 -2 Pa, using titanium and gold targets with a purity of 99.999%, deposited Ti / Au metal as the source in the source window, and then annealed at a high temperature of 460°C.

[0120] Step 12: Make Ga2O3 FET and GaN HEMT gates.

[0121] Masks were made on the Ga2O3 channel layer and the p-GaN layer to form source and drain windows, and then placed in a metal evaporation reaction chamber with a pressure of 8.8×10 -2 Pa, using nickel and gold targets with a purity of 99.999%, deposited metal Ni / Au with a thickness of 45nm / 200nm / 200nm as the gate in the drain window and gate window respectively.

[0122] Step 13: making a passivation layer.

[0123] The sample after the above steps is placed in a plasma chemical vapor deposition (PECVD) reaction chamber, and a 60nm thick Si3N4 passivation layer is deposited at a high temperature of 400°C.

[0124] Step 14: Make contact holes and metal.

[0125] The source and gate are photolithographically processed and etched to form contact holes for the gate and source to complete metal interconnection.

[0126] Step 15: making a passivation layer.

[0127] The sample after the above steps is placed in a plasma chemical vapor deposition (PECVD) reaction chamber to deposit a 100 nm thick Al2O3 passivation layer.

[0128] Step 16: Make contact holes and metal.

[0129] The source and drain are photolithographically etched to form contact holes for the drain and source to complete the device fabrication.

[0130] The above descriptions are only two specific embodiments of the present invention. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0131] Therefore, the present invention adopts a monolithically integrated GaN / Ga2O3 cascode enhanced single-particle burnout resistance device and a preparation method thereof of the above-mentioned structure, realizes a new Ga2O3 enhanced device, reduces the weight and complexity of the aerospace system, increases the reliability of the device, and improves the single-particle burnout threshold voltage of the device under aerospace radiation environment application.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solution of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of the present invention.

Claims

1. A monolithically integrated GaN / Ga2O3 cascode enhanced single event burnout resistant device, characterized in that: It comprises a Ga2O3 FET structure and a GaN HEMT structure arranged on the right side of the Ga2O3 FET structure, wherein the Ga2O3 FET structure and the GaN HEMT structure are both arranged on a substrate, and a first passivation layer is arranged between the GaN HEMT structure and the Ga2O3 FET structure; The Ga2O3 FET structure includes a Ga2O3 buffer layer and a Ga2O3 channel layer from bottom to top, and a first source electrode, a first gate electrode and a first drain electrode are arranged above the Ga2O3 channel layer from left to right; The GaN HEMT structure includes an AlN nucleation layer, a GaN buffer layer and an AlGaN barrier layer from bottom to top, a second source electrode, a p-GaN layer and a second drain electrode are arranged above the AlGaN barrier layer from left to right, and a second gate electrode is arranged above the p-GaN layer; The second drain is connected to the first source, and the second source is connected to the first gate.

2. The monolithically integrated GaN / Ga2O3 cascode enhanced single event burnout resistant device according to claim 1, characterized in that: The first source and the second drain are connected via an inner interconnect metal layer, the first gate and the second source are connected via an outer interconnect metal layer, and a second passivation layer is provided between the outer interconnect metal layer and the inner interconnect metal layer.

3. The monolithically integrated GaN / Ga2O3 cascode enhanced single event burnout resistant device according to claim 1, characterized in that: The second gate serves as the gate of the Cascode structure enhanced power device, the second source serves as the source of the Cascode structure enhanced power device, and the first drain serves as the drain of the Cascode structure enhanced power device.

4. The monolithically integrated GaN / Ga2O3 cascode enhanced single event burnout resistant device according to claim 1, characterized in that: The substrate is made of sapphire or Si or SiC or GaN or Ga2O3 bulk material.

5. The monolithically integrated GaN / Ga2O3 cascode enhanced single event burnout resistant device according to claim 1, characterized in that: The second source electrode and the second drain electrode adopt a metal layer combination of Ti / Al or Ti / Al / Ni / Au or Ti / Al / Mo / Au, and the second gate electrode adopts a metal layer combination of Ni / Au / Ni or Ni / Au or W / Au or Mo / Au.

6. The monolithically integrated GaN / Ga2O3 cascode enhanced single event burnout resistant device according to claim 2, characterized in that: The first passivation layer and the second passivation layer are made of Si3N4 or Al2O3 or SiO2 or HfO2.

7. A method for preparing a monolithically integrated GaN / Ga2O3 cascode-enhanced single-event burnout-resistant device as claimed in any one of claims 1 to 6, characterized in that: The following steps are involved: (1) Cleaning and pre-treating the substrate surface to eliminate surface dangling bonds, and heat treating at 900°C-1200°C in a H2 atmosphere reaction chamber to remove surface contaminants; (2) The heat-treated substrate is subjected to an MOCVD process to deposit Ga2O3 with a thickness of 100nm-1000nm as a buffer layer for the Ga2O3 FET structure; (3) Using MOCVD process to deposit Ga2O3 with a thickness of 100nm-1000nm on the Ga2O3 buffer layer as the channel layer of the device, and the doping concentration is 1×10 15 cm -3 -1×10 20 cm -3 Si; (4) growing a mask layer on the Ga2O3 channel layer, performing photolithography and etching on the mask layer, and exposing a regional window of the GaN HEMT structure on the substrate; (5) Depositing an AlN nucleation layer with a thickness of 50nm-100nm on the regional window of the GaN HEMT structure using the MOCVD process; (6) Depositing a GaN buffer layer with a thickness of 0.1 μm to 10 μm on the AlN nucleation layer using a MOCVD process; (7) Depositing an AlGaN barrier layer with a thickness of 10 nm to 50 nm on the GaN buffer layer using a MOCVD process; (8) A p-GaN layer with a thickness of 50nm-500nm is deposited on the AlGaN barrier layer using MOCVD process and the doping concentration is 1×10 16 cm -3 -1×10 20 cm -3 Mg; (9) Making a photolithography mask on the p-GaN layer and etching away the p-GaN layer outside the gate region; (10) growing a mask layer on the Ga2O3 channel layer, exposing the source and drain windows by photolithography and etching, and using an ion implantation process in the source and drain windows to implant Si ions into the source and drain regions at high temperature; (11) performing photolithography on the AlGaN barrier layer, and depositing a second source electrode and a second drain electrode by metal evaporation or magnetron sputtering, and performing high temperature annealing; (12) performing photolithography on the Ga2O3 channel layer, and depositing source and drain metals in the first source and first drain windows by metal evaporation or magnetron sputtering, and annealing at high temperature; (13) performing photolithography on the Ga2O3 channel layer and the p-GaN layer, and depositing gate metals respectively by metal evaporation or magnetron sputtering; (14) placing the epitaxial wafer after the above steps into a PECVD reaction chamber to deposit a passivation layer; (15) Performing photolithography and etching on the passivation layer to form gate, source, and drain contact holes, completing the metal interconnection between the second source of the GaN HEMT and the first gate of the Ga2O3 FET; (16) placing the epitaxial wafer after the above steps into a PECVD reaction chamber to deposit a passivation layer; (17) Perform photolithography and etching on the passivation layer to form gate, source, and drain contact holes, and connect the metal of the second drain of the GaN HEMT and the first source of the Ga2O3 FET to complete the device fabrication.

Images