A passive RFID chip and control method based on Internet of Things technology

Abstract

The present invention relates to a passive RFID chip based on Internet of Things technology and a control method, comprising: a rectifier circuit, a modulation circuit and a demodulation circuit connected in sequence, wherein the rectifier circuit is a single-ended two-stage voltage doubler rectifier, and the modulation circuit is an amplitude keying circuit. Threshold processing is performed by the rectifier circuit to improve the sensitivity of the rectifier and the energy conversion efficiency. The rectifier tube is composed of an N-type MOS tube and a P-type MOS tube to reduce the reverse leakage current, and a radio frequency signal with a phase opposite to that of the source is added to the tube grid to increase the sensitivity of the rectifier and further reduce the reverse leakage current.

Description

Technical Field

[0001] The present invention relates to the design field of RFID chips, and in particular to a passive RFID chip based on Internet of Things technology and a control method thereof. Background Art

[0002] RFID technology is a contactless identification technology that uses radio frequency signals to identify objects. RFID is a basic technology used for the underlying construction of the Internet of Things. Compared with optical identification technologies such as barcodes and QR codes that can only identify one type of object, RFID can be used to identify a single object. It can also directly read the information of the internal chip through the packaging material and support the identification of multiple objects at the same time. RFID can also apply various encryption technologies to achieve more secure information transmission. According to the source of energy, RFID is divided into active and passive types; according to the frequency of use, it can be divided into low frequency (LF), high frequency (HF) and ultra-high frequency (UHF). Relatively speaking, in the domestic integrated circuit industry, the development of UHF RFID has just started, and there are few finished UHF RFID tag chips. Summary of the invention

[0003] In view of the shortcomings of the prior art, the present invention provides a passive RFID chip based on the Internet of Things technology, characterized in that it includes: a rectifier circuit, a modulation circuit, and a demodulation circuit connected in sequence, the rectifier circuit is a single-ended two-stage voltage doubler rectifier, and the modulation circuit is an amplitude keying circuit.

[0004] Preferably, the single-ended two-stage voltage doubler rectifier comprises: a voltage doubler circuit and a rectifier circuit connected in sequence, and each stage of rectifier tubes of the voltage doubler circuit and the rectifier circuit are respectively provided with an NMOS diode and a PMOS diode.

[0005] Preferably, the demodulation circuit includes an envelope detection circuit, a voltage limiting circuit, a peak detection circuit and a hysteresis comparator, the input end of the envelope detection circuit serves as the input end of the demodulation circuit, the output end of the envelope detection circuit is respectively connected to the input end of the peak detection circuit and the input end of the hysteresis comparator through the voltage limiting circuit, and the output end of the hysteresis comparator serves as the output end of the demodulation circuit.

[0006] Furthermore, the hysteresis comparator includes complementary inputs based on an N-type MOS tube differential pair and a P-type MOS tube differential pair.

[0007] Preferably, a wireless receiver is provided at the input end of the amplitude keying circuit.

[0008] Based on the same inventive concept, the present invention also provides a control method for a passive RFID chip based on Internet of Things technology, comprising:

[0009] The RF energy received by the antenna from the electromagnetic field emitted by the reader is converted into a DC level for normal operation of the chip by using the rectifier of the passive RFID chip;

[0010] The DC level signal uses a demodulation circuit to obtain a signal envelope;

[0011] After acquiring the signal envelope, the modulation circuit backscatters the digital baseband signal to be returned to the reader.

[0012] Compared with the closest prior art, the present invention has the following beneficial effects:

[0013] Threshold processing is performed through the rectifier circuit to improve the rectifier sensitivity and energy conversion efficiency. The rectifier tube is composed of N-type MOS tube and P-type MOS tube to reduce the reverse leakage current. At the same time, a radio frequency signal with a phase opposite to that of the source is added to the tube gate to increase the rectifier sensitivity and further reduce the reverse leakage current. A low-power hysteresis comparator is designed, and the dynamic range of the demodulator is improved by combining N-type input and P-type input. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a design flow chart of a passive RFID chip based on Internet of Things technology provided by the present invention;

[0015] Figure 2 This is a control flow chart of a passive RFID chip based on Internet of Things technology provided by the present invention;

[0016] Figure 3 It is a schematic diagram of an RF-DC charge pump of a passive RFID chip based on Internet of Things technology provided by the present invention;

[0017] Figure 4 This is a schematic diagram of a voltage doubler rectifier of a passive RFID chip based on Internet of Things technology provided by the present invention;

[0018] Figure 5 This is a schematic diagram of a voltage doubling circuit of a passive RFID chip based on Internet of Things technology provided by the present invention;

[0019] Figure 6 This is a schematic diagram of a rectifier circuit of a passive RFID chip based on Internet of Things technology provided by the present invention;

[0020] Figure 7 It is a schematic diagram of a rectifier circuit for threshold compensation of a passive RFID chip based on Internet of Things technology provided by the present invention;

[0021] Figure 8 It is a schematic diagram of a demodulation circuit of a passive RFID chip based on Internet of Things technology provided by the present invention;

[0022] Fig. 9 This is a schematic diagram of an envelope detection circuit of a passive RFID chip based on Internet of Things technology provided by the present invention;

[0023] Fig.10 It is a schematic diagram of a peak detection circuit of a passive RFID chip based on Internet of Things technology provided by the present invention;

[0024] Fig.11 It is a schematic diagram of a hysteresis comparator circuit of a passive RFID chip based on Internet of Things technology provided by the present invention;

[0025] Fig.12 The present invention provides an ASK modulation circuit schematic diagram of a passive RFID chip based on Internet of Things technology. DETAILED DESCRIPTION

[0026] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Embodiment 1:

[0029] The present invention provides a passive RFID chip based on Internet of Things technology, such as Figure 1 As shown, it includes: a rectifier circuit, a modulator circuit, and a demodulator circuit connected in sequence, wherein the rectifier circuit is a single-ended two-stage voltage doubler rectifier, and the modulator circuit is an amplitude keying circuit.

[0030] The single-ended two-stage voltage doubler rectifier comprises: a voltage doubler circuit and a rectifier circuit connected in sequence, wherein rectifier tubes of each stage of the voltage doubler circuit and the rectifier circuit are respectively provided with NMOS diodes and PMOS diodes.

[0031] The demodulation circuit includes an envelope detection circuit, a voltage limiting circuit, a peak detection circuit and a hysteresis comparator. The input end of the envelope detection circuit serves as the input end of the demodulation circuit. The output end of the envelope detection circuit is respectively connected to the input ends of the peak detection circuit and the hysteresis comparator through the voltage limiting circuit. The output end of the hysteresis comparator serves as the output end of the demodulation circuit. The hysteresis comparator includes complementary inputs based on an N-type MOS tube differential pair and a P-type MOS tube differential pair.

[0032] The input end of the amplitude keying circuit is provided with a wireless receiver.

[0033] Embodiment 2:

[0034] The present invention provides a control method for a passive RFID chip based on Internet of Things technology, such as Figure 2 As shown, including:

[0035] The RF energy received by the antenna from the electromagnetic field emitted by the reader is converted into a DC level for the normal operation of the chip by using the rectifier of the passive RFID chip. The RFID chip is passive, and all the energy required for the chip to work comes from the electromagnetic waves sent during the reader scanning process. Therefore, the first step of the entire identification process is that the RFID reader scans the chip to send an electromagnetic wave signal, and the rectifier on the RFID chip converts the RF energy received by the antenna from the electromagnetic field emitted by the reader into the DC level required for the chip to work. The DC level signal is amplified by the voltage doubler circuit inside the rectifier circuit, and the signal is compensated by the threshold compensation circuit; the DC level signal uses the demodulation circuit to obtain the signal envelope; after obtaining the signal envelope, the modulation circuit backscatters the digital baseband signal to be returned to the reader, and the modulator circuit sends the digital baseband signal to be returned by backscattering. The reader receives the signal, and the overall identification process is completed.

[0036] Embodiment 3:

[0037] The present invention provides a practical application of a passive RFID chip based on Internet of Things technology, including:

[0038] The RF front-end circuit mainly includes three basic modules: rectifier, modulator and demodulator.

[0039] The rectifier (RECT) is mainly responsible for converting the radio frequency energy received by the antenna from the electromagnetic field emitted by the reader into the DC level required for the chip to work. The energy is stored in the energy storage capacitor. At the same time, the input impedance of the rectifier determines the input impedance of the tag chip, and its conversion efficiency greatly affects the energy that the subsequent circuit can obtain.

[0040] The demodulator (DEMOD) is mainly responsible for restoring the electromagnetic wave signal received by the antenna from the electromagnetic field emitted by the reader into a signal that can be recognized by the digital baseband. Its demodulation sensitivity and demodulation depth indicators greatly affect the recognition rate of the tag;

[0041] The modulator (MOD) is mainly responsible for sending the digital baseband signal to be returned by backscattering. The modulation network distributes the energy received by the tag and the energy transmitted back to the reader. Therefore, the modulation network affects both the communication quality between the tag and the reader and the energy that the tag can receive. At the same time, the impedance characteristics of the modulation network affect the chip impedance, which in turn affects the working bandwidth of the tag chip.

[0042] 1) Rectifier design:

[0043] The rectifier in the tag chip is responsible for converting the RF energy received by the antenna into DC energy. Since the amplitude of the tag receiving signal is low, it cannot be directly supplied to the chip, and the level needs to be increased, which requires a voltage doubling circuit. The present invention uses a voltage doubling rectifier composed of an RF-DC charge pump to achieve voltage doubling and rectification at the same time. Figure 3 As shown, C is the pump capacitor of the charge pump voltage, Cs is the parasitic capacitance of each node, and CL is the output voltage stabilizing capacitor. The first n stages are voltage doubling circuits, which increase the voltage step by step through the unidirectional conduction performance of the diode. The last stage diode only performs rectification to obtain the highest potential of the previous stage. Cn is the DC level that provides voltage boost for each stage.

[0044] A simple single-ended two-stage voltage doubler rectifier structure is constructed based on the RF-DC charge pump. Figure 4 As shown; the voltage doubler rectifier can be divided into two parts: the voltage doubler circuit, such as Figure 5 As shown, the rectifier circuit, such as Figure 6 As shown,

[0045] When the chip input RF signal is in the positive half cycle, diode D1 is reverse biased and cut off, and the current passes through diode D2 to charge capacitor C2. The charge is maintained on capacitor C2, generating voltage VC=V out. When the chip input RF signal is in the negative half cycle, the current passes through diode D1 from the ground to charge capacitor C1. At this time, diode D2 is cut off, and the voltage on capacitor C1 is VC. After the input RF signal becomes a positive half cycle, because diode D1 is cut off, the resistance is very large, that is, the discharge time of capacitor C1 is very long. Before VC drops, the next charging cycle has arrived, so VC remains unchanged. In the next cycle, the DC voltage on capacitor C1 is superimposed on the positive half axis of the input voltage to charge capacitor C2. The voltage on capacitor C2 can reach up to twice VC, that is, Vout can reach twice Vin.

[0046] According to the above, in the design of the present invention, two MOS tubes are used in each stage to form a rectifier tube, such as Figure 7 As shown, each stage of the rectifier tube is composed of an NMOS diode and a PMOS diode.

[0047] The bias current flows through the diode formed by the MOS tube, generating the required voltage Va at the drain-source end of the MOS tube. The good current mirror capability of the current mirror can ensure the accurate compensation of the threshold voltage. In order to better avoid the influence of threshold voltage changes caused by process errors, the gate of each rectifier tube introduces the RF signal through the capacitor. It can be seen that for the P-type rectifier tube M2 and the N-type rectifier tube M3, the phase of the RF signal on the gate is opposite to the phase of the RF signal on the source. When the rectifier tube is in the conduction cycle, the gate-source voltage change of each rectifier tube will increase to twice the original, and the rectifier tube can be turned on at a lower input signal. When the rectifier tube is in the off cycle, the gate-source voltage change of each rectifier tube will also increase to twice the original, and the rectifier tube can be better turned off. As analyzed above, the circuit designed in this paper improves the sensitivity of the rectifier and reduces the reverse leakage current.

[0048] 2) Design of demodulation circuit

[0049] The demodulation circuit extracts the modulated signal from the modulated signal received by the reader and converts it into a digital signal that can be recognized by the digital baseband.

[0050] The demodulator designed in the present invention is composed of an envelope detection circuit, a voltage limiting circuit, a peak detection circuit and a hysteresis comparator. Figure 8 shown.

[0051] The envelope detection circuit is mainly responsible for extracting the signal envelope from the modulated carrier.

[0052] The voltage limiting circuit is mainly used to prevent the strong input signal in the near field from changing the working state of the comparator, thereby causing signal distortion and increasing the bit error rate, and to ensure that the chip can operate in a large dynamic range.

[0053] The peak detection circuit is responsible for extracting the DC amplitude from the input signal envelope and providing a reference voltage for the hysteresis comparator so that the signal can be demodulated correctly. It mainly affects the output duty cycle and dynamic operating range of the demodulation circuit.

[0054] The hysteresis comparator compares the input signal with the reference voltage, thereby converting the analog input signal into a signal that can be processed by the digital baseband. The use of hysteresis is mainly to reduce the impact of noise and improve the signal-to-noise ratio and sensitivity of the demodulation circuit.

[0055] Specifically: Fig. 9 As shown in the figure, in order to improve the sensitivity of the demodulation circuit, the envelope detection circuit uses a voltage doubler circuit. All charge transfer tubes use N tubes to increase the signal envelope amplitude after voltage doubling. The role of C6 and C7 is to stabilize the threshold compensation voltage.

[0056] Peak detection circuit, its specific circuit is as follows Fig.10As shown, the threshold detection circuit is mainly composed of three parts: operational amplifier, feedback, and circuit filter circuit. When the input voltage Vin is very small, all tail currents flow through the M1 tube, the M2 tube is cut off, the potential at point A is low, and the M6 ​​tube is cut off; when Vin begins to rise, the M2 tube gradually turns on, the potential at point A rises, the M6 ​​tube turns on, and point A charges the capacitor C. Although the capacitor C discharges from the MOS resistor formed by M10, the discharge current is very small and the discharge is very slow. Vref is maintained, and Vref rises with the increase of Vin until Vin reaches the maximum value. When Vin begins to decrease, Vin will be less than Vref, and the potential at point A decreases. At this time, the M6 ​​tube is reverse biased and cut off, so Vref can keep the maximum value of Vin unchanged. The discharge constant of the filter circuit composed of the resistor of the MOS tube here is greater than the period of Vin. The use of MOS tubes greatly reduces the area of ​​the RC filter circuit.

[0057] The design of the hysteresis comparator is introduced below:

[0058] The hysteresis comparator in the present invention uses a N-type MOS tube differential pair and a P-type MOS tube differential pair as complementary inputs. Fig.11 As shown, the circuit can achieve a hysteresis comparator input swing of 0 to VDD.

[0059] In the figure, the M5 / M6 differential coupling pair and the M25 / M26 differential coupling pair generate positive feedback, thereby generating hysteresis. Since the two hysteresis comparators have the same principle, the specific principle of the hysteresis comparator is briefly described below using the NMOS differential pair input as an example: In the circuit, the M21 tube and the M22 tube differential pair have the same size, the M23 tube and the M24 tube have the same size, and the M25 tube and the M26 tube have the same size and are β times the size of the M23 tube and the M24 tube. When Venv is much smaller than Vref, the M21 tube is turned on, the M22 tube is turned off, and the tail current ID32 flows through the M21 tube and the M23 tube. The M25 tube mirrors the β times ID23 to the drain of the M22 tube. Since the M22 tube is turned off, the M25 tube works in the linear region, and the drain voltage of the M22 tube is VDD. When Venv rises to be equal to Vref, ID21=ID22, but M25 will flow out β times of ID21 current, so M25 still works in the linear region, and the drain potential of M22 is still VDD. Only when Venv is greater than Vref and satisfies ID21*β=ID22, that is, ID25=ID22, the flip point is reached. On this basis, a slight increase in Venv can make ID22 greater than ID25, so that the drain voltage of M22 flips. On the other hand, the rise of Venv makes the leakage current flowing through M22 greater than the leakage current of M25, so that current flows through M24, and M26 mirrors β times of ID24. Since ID21=ID23+ID26, as ID26 increases, the current of ID23 decreases, and the mirror current ID25 decreases. Since ID22=ID25+ID24, ID24 will increase, thus bringing positive feedback. The final result is that the current flowing through M22 tube all flows through M24 tube, ID26 mirrors ID24, resulting in the current flowing through M23 tube and M25 tube to be 0. Similarly, when Venv decreases, only when Venv decreases to less than Vref, so that ID21 = β*ID22, will it reach another flip point, which forms hysteresis.

[0060] 3) Modulation circuit:

[0061] In RFID chips, signal modulation is achieved by using backscattering technology. Backscattering relies on changing the chip impedance to reflect the energy sent by the reader to the tag and then modulate the signal.

[0062] The present invention uses NMOS tube to form ASK circuit. Fig.12 As shown, the present invention uses dual antenna input. When returning the signal, the delay of the two signal paths may cause signal crosstalk, so an antenna selection signal is added to judge the signal strength, thereby selecting the path with a strong receiving signal for backscattering modulation.

[0063] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0064] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0065] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0066] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A passive RFID chip based on Internet of Things technology, characterized in that: include: A rectifier circuit, a modulator circuit, and a demodulator circuit connected in sequence, wherein the rectifier circuit is a single-ended two-stage voltage doubler rectifier, and the modulator circuit is an amplitude keying circuit; The demodulation circuit includes an envelope detection circuit, a voltage limiting circuit, a peak detection circuit and a hysteresis comparator, the input end of the envelope detection circuit serves as the input end of the demodulation circuit, the output end of the envelope detection circuit is respectively connected to the input end of the peak detection circuit and the input end of the hysteresis comparator through the voltage limiting circuit, and the output end of the hysteresis comparator serves as the output end of the demodulation circuit; The hysteresis comparator includes complementary inputs based on an N-type MOS tube differential pair and a P-type MOS tube differential pair, and the specific structure includes two circuit parts that are mirror images of each other: Part of the circuit uses N-type MOS tubes for differential pair input, then: The gate of the M21 tube is connected to the Vref voltage; the source of the M21 tube is connected to the source of the M22 tube and the drain of the M32 tube; the drain of the M21 tube is connected to the source of the M23 tube and the source of the M26 tube; the gate of the M23 tube is connected to its own source, the gate of the M27 tube and the gate of the M25 tube; the drain of the M23 tube, the drain of the M26 tube, the drain of the M27 tube, and the drain of the M31 tube are connected to the VDD voltage; the source of the M27 tube is connected to the drain of the M29 tube; the gate of the M29 tube is connected to its own drain and the gate of the M30 tube; the source of the M29 tube, the source of the M30 tube, the source of the M31 tube, and the source of the M32 tube are connected to the VSS voltage; the drain of the M30 tube is connected to the source of the M28 tube and the demod_out output terminal; the gate of the M31 tube is connected to its own drain and the gate of the M32 tube; The gate of M22 is connected to the Venv voltage; the drain of M22 is connected to the source of M24 and the source of M25; the gate of M24 is connected to its own source, the gate of M28 and the gate of M26; the drain of M24, the drain of M25 and the drain of M28 are connected to the VDD voltage; the size of M21 is the same as that of M22; the size of M23 is the same as that of M24; the size of M25 and M26 is the same and is β times the size of M23 and M24.

2. A passive RFID chip based on Internet of Things technology as claimed in claim 1, characterized in that: The single-ended two-stage voltage doubler rectifier comprises: a voltage doubler circuit and a rectifier circuit connected in sequence, wherein rectifier tubes of each stage of the voltage doubler circuit and the rectifier circuit are respectively provided with NMOS diodes and PMOS diodes.

3. A passive RFID chip based on Internet of Things technology as claimed in claim 1, characterized in that: The input end of the amplitude keying circuit is provided with a wireless receiver.

4. A control method for a passive RFID chip based on Internet of Things technology using the chip as described in any one of claims 1 to 3, characterized in that: include: The RF energy received by the antenna from the electromagnetic field emitted by the reader is converted into a DC level for normal operation of the chip by using the rectifier of the passive RFID chip; The DC level signal uses a demodulation circuit to obtain a signal envelope; After acquiring the signal envelope, the modulation circuit backscatters the digital baseband signal to be returned to the reader.

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