Magnetic random access memory, storage array, and electronic device

Abstract

A magnetic random access memory, a storage array and an electronic device, comprising: a driving signal module for providing a read signal; a storage array comprising a plurality of storage cells; a storage cell for data to be read being a data cell for loading a read signal and outputting a data voltage; a storage cell for reading a reference being a reference cell, the reference cell comprising one or more parallel state reference cells, the magnetic free layer of the parallel state reference cell being used to form a reference output terminal; or the reference cell comprising one or more anti-parallel state reference cells, the magnetic fixed layer of the anti-parallel state reference cell being used to form a reference output terminal; the reference cell being used to load a read signal and output a reference voltage through the reference output terminal; and a comparison circuit being used to read the data of the data cell according to the relative size of the data voltage and the reference voltage. The present invention reduces the possibility of the resistance state of the reference cell being flipped during a read operation, ensures the reliability of the reference cell, and improves the performance of the MRAM.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a magnetic random access memory, a storage array and an electronic device. Background Art

[0002] Magnetic Random Access Memory (MRAM) is a non-volatile magnetic random access memory. MRAM devices have the high-speed read and write capabilities of static random access memory (SRAM) and the high integration of dynamic random access memory (DRAM). They can basically be rewritten infinitely. MRAM devices are a "full-kinetic" solid-state memory. Magnetic random access memory is considered to be the most widely used "general-purpose" processor in the future due to its advantages such as high read and write speed, long life and non-volatility, and is expected to dominate the next-generation memory market.

[0003] In MRAM devices, data is stored by the magnetic state of the storage element. An MRAM cell is usually composed of a transistor and a magnetic tunnel junction (MTJ) to form a storage cell. The MTJ structure includes at least two electromagnetic layers and an insulating layer for isolating the two electromagnetic layers. The two electromagnetic layers can maintain two magnetic polarization fields separated by an insulating layer, one of which is a fixed magnetic layer whose polarization direction is fixed, and the other is a free rotation magnetic layer whose polarization direction can change with the change of the external field. When the polarization directions of the two electromagnetic layers are parallel, the tunneling current flowing through the MTJ structure has a maximum value, and the MTJ structure unit resistance is low: when the polarization directions of the two magnetic layers are antiparallel, the tunneling current flowing through the MTJ structure has a minimum value, and the MTJ structure unit resistance is high. Information is read by measuring the resistance of the MRAM cell, which is the working principle of the MTJ structure.

[0004] However, the reliability of MRAM currently needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a magnetic random access memory, a storage array and an electronic device, which reduce the possibility of the resistance state of the reference unit being flipped during a read operation and improve the reliability of the MRAM.

[0006] To solve the above problems, an embodiment of the present invention provides a magnetic random access memory, comprising: a driving signal module for providing a read signal; a storage array, comprising a plurality of storage units arranged in an array, the storage unit comprising a magnetic tunnel junction, the magnetic tunnel junction comprising a magnetic fixed layer and a magnetic free layer arranged oppositely; a storage unit for data to be read is defined as a data unit, the data unit is used to load the read signal to output a data voltage; a storage unit used as a reference for data reading is defined as a reference unit, the reference unit comprises one or more parallel state reference units, the magnetic free layer of one of the parallel state reference units is used to form a reference output terminal, or the magnetic free layers of multiple parallel state reference units are coupled to form a reference output terminal; or, the reference unit comprises one or more anti-parallel state reference units, the magnetic fixed layer of one of the anti-parallel state reference units is used to form a reference output terminal, or the magnetic fixed layers of multiple anti-parallel state reference units are coupled to form a reference output terminal; the reference unit is used to load the read signal and output a reference voltage through the reference output terminal; a comparison circuit is used to read the data of the data unit according to the relative size of the data voltage and the reference voltage.

[0007] Correspondingly, an embodiment of the present invention further provides a storage array, which is applied to a magnetic random access memory, wherein the magnetic random access memory comprises: a driving signal module, which is used to provide a read signal to the storage array; a comparison circuit, which is used to read data of the storage array according to the relative size of the data voltage output by the storage array and the reference voltage; the storage array comprises: a plurality of storage cells arranged in an array, wherein the storage cells comprise a magnetic tunnel junction, wherein the magnetic tunnel junction comprises a relatively arranged magnetic fixed layer and a magnetic free layer; a storage cell for data to be read is defined as a data cell, wherein the data cell is used to load the read signal and output the data voltage ; A storage unit used as a reference for data reading is defined as a reference unit, wherein the reference unit includes one or more parallel state reference units, a magnetic free layer of the parallel state reference unit is used to form a reference output terminal, or a plurality of magnetic free layers of the parallel state reference units are coupled to form a reference output terminal; or, the reference unit includes one or more anti-parallel state reference units, a magnetic fixed layer of the anti-parallel state reference unit is used to form a reference output terminal, or a plurality of magnetic fixed layers of the anti-parallel state reference units are coupled to form a reference output terminal; the reference unit is used to load the read signal and output the reference voltage through the reference output terminal.

[0008] Correspondingly, an embodiment of the present invention further provides an electronic device, including: the magnetic random access memory provided by the embodiment of the present invention.

[0009] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0010] The embodiment of the present invention provides a magnetic random access memory, in which a storage unit is written into a high resistance state (R H ) or the antiparallel current direction is consistent with the direction of the magnetic fixed layer pointing to the magnetic free layer, writing the memory cell to a low resistance state (R L ) or the direction of the current in the parallel state is consistent with the direction in which the magnetic free layer points to the magnetic fixed layer. In the magnetic random access memory provided by the embodiment of the present invention, the reference unit includes one or more parallel state (Parallel, P state) reference units, the magnetic free layer of one of the parallel state reference units is used to form a reference output terminal, or the magnetic free layers of multiple parallel state reference units are coupled to form a reference output terminal. During the read operation, the direction of the read current passing through the parallel state reference unit is consistent with the direction in which the magnetic free layer points to the magnetic fixed layer, that is, the direction in which the storage unit is written to the low resistance state (R L ) or parallel state, thereby reducing the possibility of flipping the resistance state of the parallel state reference unit during the read operation; or, the reference unit is one or more anti-parallel state reference units, a magnetic fixed layer of the anti-parallel state reference unit is used to form a reference output terminal, or the magnetic fixed layers of multiple anti-parallel state (Anti-Parallel, AP state) reference units are coupled to form a reference output terminal, and during the read operation, the direction of the read current passing through the anti-parallel state reference unit is consistent with the direction of the magnetic fixed layer pointing to the magnetic free layer, that is, the direction of writing the storage unit to the high resistance state (R H ) or the antiparallel state, thereby reducing the possibility of the resistance state of the antiparallel reference cell being flipped during the read operation.

[0011] In summary, the embodiments of the present invention are conducive to ensuring that the resistance state of the reference unit is not easily flipped after a long period of read operation, reducing the possibility of flipping the resistance state of the reference unit during the read operation, and correspondingly providing a more reliable reference resistance for data reading of the data unit, thereby ensuring the reliability of the reference unit, thereby improving the data reading accuracy of the MRAM, and correspondingly improving the reliability of the MRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the structure of a magnetic random access memory;

[0013] Figures 2 to 4 It is a schematic structural diagram of an embodiment of a magnetic random access memory of the present invention;

[0014] Figure 5 It is a schematic structural diagram of another embodiment of the magnetic random access memory of the present invention. DETAILED DESCRIPTION

[0015] As can be seen from the background technology, the reliability of MRAM needs to be improved.

[0016] According to analysis, the standard MRAM reference resistance reading strategy uses multiple reference cells with magnetic tunnel junctions in antiparallel state (i.e. high resistance state) and parallel state (i.e. low resistance state) as references for data reading. Generally speaking, the number of times a reference cell is read is much greater than the number of times a data cell is read. If no special treatment is performed, after a long period of read operation, the resistance state of the reference cell is prone to flip, which will cause the reference resistance value to change, and the data read error rate will rise rapidly, reducing the reliability of MRAM.

[0017] The reasons why the reliability of MRAM needs to be improved are analyzed in combination with a magnetic random access memory. Figure 1 It is a structural diagram of a magnetic random access memory.

[0018] like Figure 1 As shown, the magnetic random access memory includes: a driving signal module 16 for providing a read signal; a storage array, including a plurality of storage units arranged in an array, wherein the storage unit includes a magnetic tunnel junction 10, wherein the magnetic tunnel junction 10 includes a magnetic fixed layer 101 and a magnetic free layer 102 located on the magnetic fixed layer 101; a storage unit for data to be read is defined as a data unit 11, and a storage unit used as a reference for data reading is defined as a reference unit 12, wherein the reference unit 12 includes an antiparallel state (i.e., a high resistance state R H ) reference unit 12H and parallel state (i.e. low resistance state R L ) reference unit 12L, the magnetic free layer 102 of the antiparallel reference unit 12H and the parallel reference unit 12L are coupled to form a reference output terminal 13A; a load circuit 14 is coupled to the data unit 11 and to the reference output terminal 13A of the reference unit 13; the load circuit 14 is used to convert the read current of the data unit 11 into a data voltage Vdata, and to convert the read current of the reference unit 13 into a reference voltage Vref; a comparison circuit 15, including a first input terminal 151, a second input terminal 152 and an output terminal 153, the first input terminal 151 is coupled to the data unit 11, the second input terminal 152 is coupled to the reference output terminal 13A, the comparison circuit 15 is used to read the information of the data unit 11 according to the relative sizes of the data voltage Vdata and the reference voltage Vref, and the output terminal 153 outputs a comparison result signal.

[0019] like Figure 1 As shown in the direction of the dashed arrow, when reading, the read current first passes through the magnetic free layer 102 of the MTJ 10 and then passes through the magnetic reference layer 101. The read current is antiparallel to the write 1 (Write 1 (R H), that is, the direction of the current is opposite to that of the write current for writing the antiparallel state reference unit 12H from the high resistance state to the low resistance state. When in the data reading state for a long time, the risk of the resistance state of the MTJ 10 of the antiparallel state reference unit 12H being flipped is high. The MTJ 10 in the antiparallel state reference unit 12H is easily flipped from the antiparallel (AP) state to the parallel (P) state, which causes the reference resistance value to change, reduces the accuracy of the MRAM reading data, and further reduces the reliability of the MRAM.

[0020] In order to solve the technical problem, an embodiment of the present invention provides a magnetic random access memory, which is conducive to ensuring that the resistance state of the reference unit is not easy to flip after a long read operation, reducing the possibility of flipping the resistance state of the reference unit during the read operation, and correspondingly providing a more reliable reference resistance for data reading of the data unit, ensuring the reliability of the reference unit, thereby improving the data reading accuracy of the MRAM, and correspondingly improving the reliability of the MRAM.

[0021] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figures 2 to 4 It is a schematic structural diagram of a magnetic random access memory according to an embodiment of the present invention.

[0022] In this embodiment, the magnetic random access memory (MRAM) 200 includes a driving signal module 180 for providing a read signal.

[0023] The memory array 400 includes a plurality of memory cells arranged in an array, wherein the memory cells include a magnetic tunnel junction (MTJ) 100, wherein the magnetic tunnel junction 100 includes a relatively arranged magnetic fixed layer (Pinned A storage unit for data to be read is defined as a data unit 110, and the data unit 110 is used to load the read signal to output a data voltage Vdata; a storage unit used as a reference for data reading is defined as a reference unit 120, and the reference unit 120 includes one or more parallel state (Parallel, P state) reference units 120L, and the magnetic free layer 1002 of one of the parallel state reference units 120L is used to form a reference output terminal 120A, or the magnetic free layers 1002 of multiple parallel state reference units 120L are coupled to form a reference output terminal 120A; or, the reference unit 120 includes one or more anti-parallel state (Anti-Parallel, AP state) reference units, and the magnetic fixed layer of one of the anti-parallel state reference units is used to form a reference output terminal, or the magnetic fixed layers of multiple anti-parallel state reference units are coupled to form a reference output terminal; the reference unit 120 is used to load the read signal and output a reference voltage Vref through the reference output terminal 120A.

[0024] The comparison circuit 150 is used to read the data of the data unit 110 according to the relative magnitudes of the data voltage Vdata and the reference voltage Vref.

[0025] In this embodiment, the “coupling” is a direct connection or an indirect connection. The meaning of “coupling” in the following text is consistent and will not be explained one by one.

[0026] In this embodiment, the reference unit 120 includes one or more parallel state reference units 120L, and the magnetic free layer 1002 of a parallel state reference unit 120L is used to form the reference output terminal 120A, or the magnetic free layers 1002 of multiple parallel state reference units 120L are coupled to form the reference output terminal 120A.

[0027] The drive signal module 180 is used to provide a read signal to the memory array 400 so that the memory array 400 outputs data based on the read signal. In this embodiment, the drive signal module 180 is used to provide a bit line voltage, the reference unit 120 is used to load the bit line voltage and output a reference current through the reference output terminal 120A, and the data unit 110 is used to load the bit line voltage and output a data current.

[0028] In this embodiment, the magnetic random access memory 200 further includes: a load circuit 140 coupled to the data unit 110 and to the reference output terminal 120A; the load circuit 140 is used to convert the read current of the data unit 110 into the data voltage Vdata, and to convert the read current of the reference unit 120 into the reference voltage Vref.

[0029] In this embodiment, the driving signal module 180 includes: a clamping circuit 160, coupled to the load circuit 140, and used to clamp the bit line voltages of the data unit 110 and the reference unit 120; a bit line selection circuit 170, one end of which is coupled to the clamping circuit 160, and the other end of which is respectively coupled to the reference output terminal 120A of the data unit 110 and the reference unit 120, and the bit line selection circuit 170 is suitable for selecting the data unit 110 and the reference unit 120 to be read.

[0030] The clamping circuit 160 is used to provide a bit line voltage to the data cell 110 and the reference cell 120, and to clamp the bit line voltage of the data cell 110 and the bit line voltage of the reference cell 120, so as to limit the bit line voltage of the data cell 110 and the reference cell 120 to a preset range, so as to prevent the bit line voltage of the data cell 110 and the reference cell 120 from being too large, thereby causing the magnetic tunnel junction 100 of the data cell 110 and the reference cell 120 to be damaged, thereby protecting the data cell 110 and the reference cell 120.

[0031] In this embodiment, the clamp circuit 160 includes an NMOS transistor, a drain of the NMOS transistor is coupled to the load circuit 140 , a source of the NMOS transistor is coupled to the bit line selection circuit 170 , and a gate of the NMOS transistor is used to load the clamp control signal VClamp.

[0032] During the read operation, the voltage loaded to the gate of the NMOS tube is: the sum of the threshold voltage of the NMOS tube and the bit line voltage, thereby ensuring that the bit line voltage loaded to the data unit 110 or the reference unit 120 is the preset bit line voltage, and when the voltage loaded to the gate of the NMOS tube is greater than the preset bit line voltage, the channel of the NMOS tube will be turned off, thereby protecting the circuit.

[0033] like Figure 3As shown, in a specific implementation, the clamp circuit 160 may include a first NMOS transistor N1 and a second NMOS transistor N2. The drain of the first NMOS transistor N1 is coupled to the first output terminal of the load circuit 140, the gate of the first NMOS transistor N1 is coupled to the clamp control signal VClamp, the drain of the second NMOS transistor N2 is coupled to the second output terminal of the load circuit 140, the gate of the second NMOS transistor N2 is suitable for coupling to the clamp control signal VClamp, and the first NMOS transistor N1 and the second NMOS transistor N2 are suitable for clamping the bit line voltage of the data unit 110 and the reference unit 120 under the control of the same clamp control signal VClamp, so as to avoid the data unit 110 and the reference unit 120 from being damaged due to excessive bit line voltage due to factors such as misoperation.

[0034] In a specific implementation, the bit line selection circuit 170 may include a first bit line selection switch MUX data And the second bit line selection switch MUX ref , the first line selection switch MUX data The first connection terminal of the first NMOS tube N1 is coupled to the source of the first NMOS tube N1, and the first bit line selection switch MUX data The second connection end of the first line selection switch MUX is coupled to the data unit 110. data Used to select a data unit 110 to be read.

[0035] In a specific implementation, the second bit line selection switch MUX ref The first connection end of the second bit line selection switch MUX is coupled to the source of the second NMOS tube N2. ref The second connection terminal of the second bit line selection switch MUX is coupled to the reference unit 120. ref The second bit line selection switch MUX is used to select the reference cell 120 to be read. ref The second connection terminal of is coupled to the reference output terminal 120A.

[0036] The storage cell is used to store data. The storage array 400 includes a plurality of storage cells arranged in a matrix. The plurality of storage cells are repeated cells, that is, the plurality of storage cells have the same structure. Therefore, the parallel reference cell 120L or the anti-parallel reference cell has the same structure as the data cell 110, which is beneficial to improve the accuracy of the reference cell 120 used as a reference for data reading.

[0037] In a specific implementation, the magnetic tunnel junction 100 in the storage unit is used to store data. Specifically, when the magnetic directions of the magnetic fixed layer 1001 and the magnetic free layer 1002 are parallel, the storage unit is in a parallel state, the tunneling current flowing through the magnetic tunnel junction 100 has a maximum value, and the magnetic tunnel junction 100 is in a low resistance state (RL); when the magnetic directions of the magnetic fixed layer 1001 and the magnetic free layer 1002 are antiparallel, the storage unit is in an antiparallel state, the tunneling current flowing through the magnetic tunnel junction 100 has a minimum value, and the magnetic tunnel junction 100 is in a high resistance state (RH).

[0038] The magnetization direction of the magnetic fixed layer 1001 is fixed, and is used as a magnetization direction reference layer for the magnetic free layer 1002. The magnetization direction of the magnetic free layer 1002 has two stable orientations, which are parallel or opposite to the magnetization direction of the magnetic fixed layer 1001, respectively, so that the magnetic tunnel junction 100 can be in a low resistance state (i.e., parallel state) or a high resistance state (i.e., anti-parallel state). The materials of the magnetic free layer 1002 and the magnetic fixed layer 1001 are both ferromagnetic metal materials, such as CoFeB or CoFe.

[0039] In this embodiment, the magnetic tunnel junction 100 further includes a tunneling barrier layer 1003 located between the magnetic fixed layer 1001 and the magnetic free layer 1002. The tunneling barrier layer 1003 is used to achieve electrical isolation between the magnetic fixed layer 1001 and the magnetic free layer 1002. The material of the tunneling barrier layer 1003 is an insulating material, such as MgO, SrO, BaO, RaO, SiO2, Al2O3, HfO2, NiO, GdO, Ta2O5, MoO2, TiO2 or WO2.

[0040] As an example, the magnetic tunnel junction 100 is bottom-pinned, and the magnetic tunnel junction 100 includes a magnetic pinned layer 1001 and a magnetic free layer 1002 located on the magnetic pinned layer 1001 .

[0041] The memory cell further includes a selection transistor N0 connected to the magnetic tunnel junction 100, and a gate of the selection transistor N0 is coupled to a word line WL (Word Line). Figure 4 As shown, in the memory array 400, a plurality of memory cells are arranged in an array, and the gate of the selection transistor of each memory cell is respectively connected to the corresponding word line WL <n>Coupling, wherein n is an integer greater than or equal to 0.

[0042] The selection transistor N0 is suitable for being turned on or off under the control of a signal connected to the word line WL to read data stored in the magnetic tunnel junction 100. In this embodiment, the selection transistor N0 is an NMOS transistor.

[0043] In this embodiment, the magnetic tunnel junction 100 is bottom magnetically fixed. Accordingly, in the data unit 110, the drain of the selection transistor N0 is coupled to the magnetic fixed layer 1002 of the magnetic tunnel junction 100, and the source SL (Source Line) of the selection transistor N0 is grounded to VSS.

[0044] The data unit 110 is a storage unit to be read, and the resistance state of the magnetic tunnel junction 100 in the data unit 110 is to be confirmed. The reference unit 120 is suitable for storing and outputting reference data, which is used as a reference for reading the data of the data unit 110.

[0045] The reference output terminal 120A is used to output a reference signal for reading data from the data unit 110. Specifically, during a read operation, the reference unit 120 outputs a reference signal through the reference output terminal 120A based on the read signal provided by the drive signal module 180.

[0046] In this embodiment, a standard resistor is formed by using the magnetic tunnel junction 100 in one or more parallel reference units 120L. By comparing the data unit 110 with the standard resistor, it is determined whether the data unit 110 is in a high resistance state or a low resistance state, thereby realizing data reading of the data unit 110.

[0047] In this embodiment, the parallel state reference unit 120L refers to that the magnetic tunnel junction 100 in the parallel state reference unit 120L is in the parallel (P) state, and the magnetic direction of the magnetic free layer 1002 is parallel to the magnetic direction of the magnetic fixed layer 1001; the antiparallel state reference unit refers to that the magnetic tunnel junction in the antiparallel state reference unit is in the antiparallel (AP) state, and the magnetic direction of the magnetic free layer is antiparallel to the magnetic direction of the magnetic fixed layer.

[0048] In this embodiment, for the convenience of illustration and description, the reference unit 120 includes two parallel reference units 120L as an example. However, the number of parallel reference units 120L included in the reference unit 120 is not limited thereto.

[0049] In MRAM, the direction of the write current for writing the magnetic tunnel junction 100 from a high resistance state to a low resistance state is consistent with the direction from the magnetic free layer 1002 to the magnetic fixed layer 1001, and the direction of the write current for writing the magnetic tunnel junction 1000 from a low resistance state to a high resistance state is consistent with the direction from the magnetic fixed layer 1001 to the magnetic free layer 1002.

[0050] In this embodiment, the reference unit 120 includes one or more parallel state reference units 120L, and the magnetic free layer 1002 of a parallel state reference unit 120L is used to form the reference output terminal 120A, or the magnetic free layers 1002 of multiple parallel state reference units 120L are coupled to form the reference output terminal 120A, so that during the read operation, the direction of the read current passing through the parallel state reference unit 120L is consistent with the direction of the magnetic free layer 1002 pointing to the magnetic fixed layer 1001, that is, the direction of the read current passing through the parallel state reference unit 120L is consistent with the current direction of write 0 (Write 0), and the parallel state reference unit 120L is already in a parallel state, thereby ensuring that after a long period of read operation, the resistance state of the parallel state reference unit 120L is not easily flipped.

[0051] Specifically, in this embodiment, the reference unit 120 includes a plurality of parallel-state reference units 120L, and the magnetic free layers 1002 of the plurality of parallel-state reference units 120L are coupled to form the reference output terminal 120A.

[0052] As an example, the magnetic tunnel junction 100 is bottom magnetically fixed, and the magnetic tunnel junction 100 includes a magnetic fixed layer 1001 and a magnetic free layer 1002 located on the magnetic fixed layer 1001 .

[0053] In the present embodiment, the magnetic tunnel junction 100 is bottom magnetically fixed, and the reference unit 120 includes one or more parallel state reference units 120L, and the magnetic free layer 1001 of the parallel state reference unit 120L is coupled to form a reference output terminal 120A. Therefore, when a read operation is performed, the direction of the read current passing through the magnetic tunnel junction 100 of the parallel state reference unit 120L is consistent with the direction of the magnetic free layer 1002 pointing to the magnetic fixed layer 1001, and there is no need to change the structure of the circuit, which is beneficial to reducing the complexity of the circuit design and improving the compatibility with the existing circuit structure.

[0054] Accordingly, in this embodiment, the magnetic free layer 1001 of the data unit 110 is coupled to the load circuit 140 .

[0055] Specifically, the drain of the selection transistor N0 in the data unit 110 is coupled to the magnetic fixed layer 1001 of the magnetic tunnel junction 100 , and the source of the selection transistor N0 in the data unit 110 is grounded to VSS.

[0056] Accordingly, in the present embodiment, in the parallel state reference unit 120L, the drain of the selection transistor N0 is coupled to the magnetic fixed layer 1001 of the magnetic tunnel junction 100 , and the source of the selection transistor N0 is grounded to VSS.

[0057] In this embodiment, during the read operation, the direction of the read current is the direction along the reference output terminal 120A pointing to the ground terminal VSS. Specifically, in the parallel state reference unit 120L, the direction of the read current passing through the magnetic tunnel junction 100 is consistent with the direction of the magnetic free layer 1002 pointing to the magnetic fixed layer 1001, that is, the same as the current direction of writing the magnetic tunnel junction 100 to the low resistance state or parallel state, and the magnetic tunnel junction 100 in the parallel state reference unit 120L is already in the low resistance state, thereby preventing the resistance state of the parallel state reference unit 120L from flipping.

[0058] The load circuit 120 is used to convert the read current of the data unit 110 into the data voltage Vdata, and to convert the read current of the reference unit 120 into the reference voltage Vref, so that the comparison circuit 150 can compare the relative magnitudes of the data voltage Vdata and the reference voltage Vref and read the information of the data unit 110.

[0059] In this embodiment, the load circuit 140 includes an input terminal (not labeled), a first output terminal (not labeled) and a second output terminal (not labeled), the input terminal of the load circuit 140 is coupled to the power supply VDD, the first output terminal of the load circuit 140 is coupled to the data unit 110, and the second output terminal of the load circuit 140 is coupled to the reference output terminal 120A.

[0060] like Figure 2 As shown, when data reading is not performed, the data voltage Vdata converted by the load circuit 140 is equal to the reference voltage Vref; when data reading is performed, if the resistance of the data unit 110 is in the low resistance state RL, the data voltage Vdata at the access point of the comparison circuit 150 and the load circuit 140 will be pulled down due to the resistance of the low resistance state RL. Compared with the state where data reading is not performed, the data voltage Vdata is reduced and shows a decreasing trend. The comparison circuit 150 can detect that the data voltage Vdata of the data unit 110 is less than the reference voltage Vref, thereby judging that the data bit stored in the data unit 110 is "0".

[0061] If the resistance of the data unit 110 is in the high-resistance state RH, the data voltage Vdata at the access point of the comparison circuit 150 and the load circuit 140 will be pulled up due to the resistance of the high-resistance state RH. Compared with the state where no data is read, the data voltage Vdata increases and shows an increasing trend. The comparison circuit 150 can detect that the data voltage Vdata of the data unit 110 is greater than the reference voltage Vref of the reference unit 120, thereby determining that the data bit stored in the data unit 110 is "1", or vice versa.

[0062] In this embodiment, the load circuit 140 is a current mirror for mirroring the read current generated in the reference unit 120 to the data unit 110 and converting the read current of the data unit 110 into a data voltage Vdata.

[0063] In this embodiment, the reference unit 120 includes one or more parallel reference units 120L; the number of the parallel reference units 120L is M, where M is a positive integer; in the current mirror, the mirror ratio from the reference unit 120 to the data unit 110 is x:1, where x is ±10% of the range; is the average resistance of the reference cell magnetic tunnel junction in the antiparallel state, is the average resistance of the parallel state reference unit magnetic tunnel junction. Specifically, in this embodiment, the Refers to the average resistance of the antiparallel reference unit magnetic tunnel junction obtained during the research and development stage. Refers to the average resistance of the parallel-state reference unit magnetic tunnel junction obtained during the research and development stage.

[0064] By setting the mirror ratio of the reference cell 120 to the data cell 110 at the above value, the equivalent reference resistance Rref is within ±10% of the average resistance of the magnetic tunnel junctions of the antiparallel state reference cell and the parallel state reference cell.

[0065] In other embodiments, the reference unit includes one or more parallel reference units; the number of the parallel reference units is M, where M is a positive integer; in the current mirror, the mirror ratio from the reference unit to the data unit is x:1; x is By determining the mirror ratio from the reference cell to the data cell by the above formula, the equivalent reference resistance Rref is within ±10% of the middle resistance Rm of the magnetic tunnel junction of the antiparallel state reference cell and the parallel state reference cell, wherein the middle resistance Rm satisfies:

[0066] As an example, the current mirror includes: a first PMOS tube group P_Cell and a second PMOS tube group PREF, wherein the first PMOS tube group P_Cell and the second PMOS tube group PREF each include one PMOS tube or a plurality of PMOS tubes connected in parallel.

[0067] In the first PMOS tube group P_Cell, the source of the PMOS tube is coupled to the power supply VDD, the drain of the PMOS tube is coupled to the gate of the PMOS tube, and the drain of the PMOS tube is coupled to the data unit 110. The first PMOS tube group P_Cell is suitable for converting the read current passing through the first PMOS tube group P_Cell into the data voltage Vdata.

[0068] In the second PMOS tube group PREF, the source of the PMOS tube is coupled to the power supply VDD, the drain of the PMOS tube is coupled to the gate, and the drain of the PMOS tube is coupled to the reference output terminal 120A. The second PMOS tube group PREF is suitable for converting the read current passing through the second PMOS tube group into the reference voltage Vref.

[0069] Correspondingly, the drain of the PMOS tube of the first PMOS tube group P_Cell is the first output end of the load circuit 140 , and the drain of the PMOS tube of the second PMOS tube group PREF is the second output end of the load circuit 140 .

[0070] In this embodiment, the number m of PMOS tubes in the second PMOS tube group PREF is determined by the formula (m*w2) / (n*w1)=x, wherein w2 is the channel width of the PMOS tubes in the second PMOS tube group, n is the number of PMOS tubes in the first PMOS tube group P_Cell, and w1 is the channel length of the PMOS tubes in the first PMOS tube group P_Cell.

[0071] Specifically, in this embodiment, the number of the parallel reference cells 120L is two, the second PMOS tube group includes two parallel PMOS tubes, and the channel length of the PMOS tube of the second PMOS tube group is adjusted so that the mirror ratio compensation factor x meets the above requirements. In this embodiment, the first PMOS tube group P_Cell includes one PMOS tube.

[0072] The comparison circuit 150 is used to read the information of the data unit 110 according to the relative size of the data voltage Vdata and the reference voltage Vref. In this embodiment, the comparison circuit 150 includes a first input terminal 1501, a second input terminal 1502 and an output terminal 1503, the first input terminal 1501 is coupled to the data unit 110, the second input terminal 1502 is coupled to the reference output terminal 120A, the comparison circuit 150 is used to read the information of the data unit 110 according to the relative size of the data voltage Vdata and the reference voltage Vref, and the output terminal 1503 outputs a comparison result signal.

[0073] In this embodiment, the comparison circuit 150 is a sense amplifier (SA). As an example, a non-inverting input terminal of the sense amplifier is coupled to the data unit 110 , and an inverting input terminal of the sense amplifier is coupled to the reference unit 120 .

[0074] In a specific implementation, if the data voltage Vdata is less than the reference voltage Vref, it can be determined that the data stored in the data unit 110 is "0", and the magnetic tunnel junction 100 of the data unit 110 is in a low resistance state (i.e., a parallel state); if the data voltage Vdata is greater than the reference voltage Vref, it can be determined that the data stored in the data unit 110 is "1", and the magnetic tunnel junction 100 of the data unit 110 is in a high resistance state (i.e., an anti-parallel state); or vice versa.

[0075] Figure 5 1 is a schematic diagram of the structure of another embodiment of the magnetic random access memory of the present invention. The similarities between the embodiment of the present invention and the above embodiment are not repeated here, and the difference is that:

[0076] In this embodiment, the magnetic tunnel junction 300 is top-pinned, and the magnetic tunnel junction 300 includes a magnetic free layer 3002 and a magnetic pinned layer 3001 located on the magnetic free layer 3002 .

[0077] In this embodiment, the reference unit 320 includes one or more antiparallel state reference units 320H, and the magnetic fixed layer 3002 of an antiparallel state reference unit 320H is used to form a reference output terminal 320A, or the magnetic fixed layers 3002 of multiple antiparallel state reference units 320H are coupled to form a reference output terminal 320A.

[0078] In this embodiment, the magnetic pinned layer 3001 of the data unit 310 is coupled to the load circuit 340 .

[0079] In this embodiment, the memory cell further includes a selection transistor N0 connected to the magnetic tunnel junction 300, and the gate of the selection transistor N0 is coupled to the word line WL. Accordingly, in this embodiment, in the data unit 310, the drain of the selection transistor N0 is coupled to the magnetic free layer 3002 of the magnetic tunnel junction 300, and the source of the selection transistor N0 is grounded.

[0080] In this embodiment, in the parallel state reference unit 320L, the drain of the selection transistor N0 is coupled to the magnetic free layer 3002 of the magnetic tunnel junction 300, the source of the selection transistor N0 is used to form the reference output terminal 320A, and the magnetic fixed layer 3001 of the magnetic tunnel junction 300 is grounded to VSS.

[0081] In this embodiment, in the antiparallel state reference unit 320H, the magnetic fixed layer 3001 of the magnetic tunnel junction 300 is used to form the reference output terminal 320A, the drain of the selection transistor N0 is coupled to the magnetic free layer 3002 of the magnetic tunnel junction 300, and the source of the selection transistor N0 is grounded to VSS.

[0082] In MRAM, the direction of the write current (writing "0") that writes the magnetic tunnel junction 300 from a high resistance state (i.e., an antiparallel state) to a low resistance state (i.e., a parallel state) is consistent with the direction of the magnetic free layer 3002 pointing to the magnetic fixed layer 3001, and the direction of the write current (writing "1") that writes the magnetic tunnel junction 300 from a low resistance state to a high resistance state is consistent with the direction of the magnetic fixed layer 3001 pointing to the magnetic free layer 3002.

[0083] In this embodiment, during the read operation, the direction of the read current is the direction along the reference output terminal 320A pointing to the ground terminal VSS. Specifically, in this embodiment, in the antiparallel state reference unit 320H, the direction of the read current passing through the magnetic tunnel junction 300 is consistent with the direction of the magnetic fixed layer 3001 pointing to the magnetic free layer 3002, that is, the same as the current direction of writing the magnetic tunnel junction 300 to the high resistance state, and the magnetic tunnel junction 300 in the antiparallel state reference unit 320H is already in the high resistance state, so that the resistance state of the antiparallel state reference unit 320H can be prevented from flipping.

[0084] In the present embodiment, the magnetic tunnel junction 300 is top magnetically fixed, and the reference unit 320 includes one or more antiparallel reference units 320H, and the magnetic fixed layer 3002 of the antiparallel reference unit 320H is coupled to form a reference output terminal 320A. Therefore, when a read operation is performed, the direction of the read current of the magnetic tunnel junction 300 passing through the antiparallel reference unit 320H is consistent with the direction of the magnetic fixed layer 3001 pointing to the magnetic free layer 3002, and there is no need to change the structure of the circuit, which is beneficial to reducing the complexity of the circuit design and improving the compatibility with the existing circuit structure.

[0085] In other embodiments, the reference unit is one or more antiparallel reference units, and in the current mirror, the mirror ratio from the reference unit to the data unit is x:1, where x is In the range; among them, is the average resistance of the reference cell magnetic tunnel junction in the antiparallel state, The mirror ratio of the reference cell to the data cell is set at the above value, so that the equivalent reference resistance Rref is within ±10% of the average resistance of the magnetic tunnel junction of the antiparallel reference cell and the parallel reference cell.

[0086] In some other embodiments, the reference unit includes one or more antiparallel reference units, and in the current mirror, the mirror ratio from the reference unit to the data unit is x:1; By determining the mirror ratio from the reference unit to the data unit by the above formula, the equivalent reference resistance Rref is within the range of ±10% of the intermediate resistance Rm of the magnetic tunnel junction of the antiparallel state reference unit and the parallel state reference unit, wherein the intermediate resistance Rm satisfies:

[0087] For the specific description of the magnetic random access memory described in this embodiment, reference may be made to the corresponding description in the aforementioned embodiment, and this embodiment will not be repeated here.

[0088] Accordingly, an embodiment of the present invention further provides a storage array. Figure 4 , showing a schematic structural diagram of a storage array according to an embodiment of the present invention.

[0089] In this embodiment, the memory array 400 is applied to a magnetic random access memory, which includes: a driving signal module, used to provide a read signal to the memory array 400; and a comparison circuit, used to read the data of the memory array 400 according to the relative size of the data voltage output by the memory array 400 and the reference voltage.

[0090] In this embodiment, the storage array 400 includes: a plurality of storage cells arranged in an array, the storage cell includes a magnetic tunnel junction (MTJ) 100, the magnetic tunnel junction 100 includes a magnetic fixed layer 1001 and a magnetic free layer 1002 arranged opposite to each other, the storage cell for data to be read is defined as a data cell 110, the data cell 110 is used to load a read signal to output a data voltage Vdata; the storage cell used as a data reading reference is defined as a reference cell 120, the reference cell 120 includes one or more parallel state reference cells 120L, one of the parallel state reference cells The magnetic free layer 1002 of element 120L is used to form a reference output terminal 120A, or the magnetic free layers 1002 of multiple parallel state reference units 120L are coupled to form a reference output terminal 120A; or, the reference unit 120 includes one or more anti-parallel state reference units, and the magnetic fixed layer of one anti-parallel state reference unit is used to form a reference output terminal, or the magnetic fixed layers of multiple anti-parallel state reference units are coupled to form a reference output terminal; the reference unit 120 is used to load the read signal and output the reference voltage Vref through the reference output terminal 120A.

[0091] In this embodiment, the reference unit 120 includes one or more parallel state reference units 120L. The magnetic free layer 1002 of a parallel state reference unit 120L is used to form a reference output terminal 120A, or the magnetic free layers 1001 of multiple parallel state reference units 120L are coupled to form a reference output terminal 120A. During a read operation, the direction of the read current passing through the parallel state reference unit 120L is consistent with the direction of the magnetic free layer 1001 pointing to the magnetic fixed layer 1002, that is, it is consistent with the current direction for writing the storage unit to a low resistance state or a parallel state, thereby reducing the possibility of the resistance state of the parallel state reference unit being flipped during a read operation.

[0092] Alternatively, the reference unit is one or more antiparallel state reference units, the magnetic fixed layer of an antiparallel state reference unit is used to form a reference output terminal or the magnetic fixed layers of multiple antiparallel state reference units are coupled to form a reference output terminal. During a read operation, the direction of the read current passing through the antiparallel state reference unit is consistent with the direction of the magnetic fixed layer pointing to the magnetic free layer, that is, it is consistent with the current direction for writing the storage unit to a high resistance state or an antiparallel state, thereby reducing the possibility of the resistance state of the antiparallel state reference unit being flipped during a read operation.

[0093] In summary, this embodiment reduces the possibility of the resistance state of the reference unit 120 flipping during the read operation, and accordingly provides a more reliable reference resistance for the data reading of the data unit 110, thereby ensuring the reliability of the reference unit 120, thereby improving the data reading accuracy of the MRAM, and correspondingly improving the reliability of the MRAM.

[0094] The storage unit is used to store data. The storage array 400 includes a plurality of storage units arranged in a matrix. The plurality of storage units are repeated units, that is, the plurality of storage units have the same structure. Therefore, the parallel reference unit 120L or the anti-parallel reference unit has the same structure as the data unit 110, which is beneficial to improve the accuracy of the reference unit 120 used as a reference for data reading.

[0095] In a specific implementation, the magnetic tunnel junction 100 in the storage unit is used to store data. Specifically, when the magnetic directions of the magnetic fixed layer 1001 and the magnetic free layer 1002 are parallel, the storage unit is in a parallel state, the tunneling current flowing through the magnetic tunnel junction 100 has a maximum value, and the magnetic tunnel junction 100 is in a low resistance state (RL); when the magnetic directions of the magnetic fixed layer 1001 and the magnetic free layer 1002 are antiparallel, the storage unit is in an antiparallel state, the tunneling current flowing through the magnetic tunnel junction 100 has a minimum value, and the magnetic tunnel junction 100 is in a high resistance state (RH).

[0096] The magnetization direction of the magnetic fixed layer 1001 is fixed, and is used as a magnetization direction reference layer for the magnetic free layer 1002. The magnetization direction of the magnetic free layer 1002 has two stable orientations, which are parallel or opposite to the magnetization direction of the magnetic fixed layer 1001, respectively, so that the magnetic tunnel junction 100 can be in a low resistance state (i.e., parallel state) or a high resistance state (i.e., anti-parallel state). The materials of the magnetic free layer 1002 and the magnetic fixed layer 1001 are both ferromagnetic metal materials, such as CoFeB or CoFe.

[0097] In this embodiment, the magnetic tunnel junction 100 further includes a tunnel barrier layer 1003 located between the magnetic fixed layer 1001 and the magnetic free layer 1002. The tunnel barrier layer 1003 is used to achieve electrical isolation between the magnetic fixed layer 1001 and the magnetic free layer 1002. The material of the tunnel barrier layer 1003 is an insulating material.

[0098] As an example, the magnetic tunnel junction 100 is bottom magnetically fixed, and the magnetic tunnel junction 100 includes a magnetic fixed layer 1001 and a magnetic free layer 1002 located on the magnetic fixed layer 1001 .

[0099] The memory cell further includes a selection transistor N0 connected to the magnetic tunnel junction 100, and a gate of the selection transistor N0 is coupled to a word line WL. The selection transistor N0 is adapted to be turned on or off under the control of a signal connected to the word line WL to read data stored in the magnetic tunnel junction 100. In this embodiment, the selection transistor N0 is an NMOS transistor.

[0100] In this embodiment, the magnetic tunnel junction 100 is bottom magnetically fixed. Accordingly, in the data unit 110, the drain of the selection transistor N0 is coupled to the magnetic fixed layer 1002 of the magnetic tunnel junction 100, and the source of the selection transistor N0 is grounded to VSS.

[0101] The data unit 110 is a storage unit to be read, and the resistance state of the magnetic tunnel junction 100 in the data unit 110 is to be confirmed. The reference unit 120 is suitable for storing and outputting reference data, which is used as a reference for reading the data of the data unit 110.

[0102] The reference output terminal 120A is used to output a reference signal for reading data from the data unit 110. Specifically, during a read operation, the reference unit 120 outputs a reference signal through the reference output terminal 120A based on the read signal provided by the drive signal module 180.

[0103] In this embodiment, a standard resistor is formed by using the magnetic tunnel junction 100 in one or more parallel reference units 120L. By comparing the data unit 110 with the standard resistor, it is determined whether the data unit 110 is in a high resistance state or a low resistance state, thereby realizing data reading of the data unit 110.

[0104] In this embodiment, the parallel state reference unit 120L refers to that the magnetic tunnel junction 100 in the parallel state reference unit 120L is in the parallel (P) state, and the magnetic direction of the magnetic free layer 1002 is parallel to the magnetic direction of the magnetic fixed layer 1001; the antiparallel state reference unit refers to that the magnetic tunnel junction in the antiparallel state reference unit is in the antiparallel (AP) state, and the magnetic direction of the magnetic free layer is antiparallel to the magnetic direction of the magnetic fixed layer.

[0105] In this embodiment, for the convenience of illustration and description, the reference unit 120 includes two parallel reference units 120L as an example. However, the number of parallel reference units 120L included in the reference unit 120 is not limited thereto.

[0106] In MRAM, the direction of the write current for writing the magnetic tunnel junction 100 from a high resistance state to a low resistance state is consistent with the direction from the magnetic free layer 1002 to the magnetic fixed layer 1001, and the direction of the write current for writing the magnetic tunnel junction 1000 from a low resistance state to a high resistance state is consistent with the direction from the magnetic fixed layer 1001 to the magnetic free layer 1002.

[0107] In this embodiment, the reference unit 120 includes one or more parallel state reference units 120L, and the magnetic free layer 1002 of a parallel state reference unit 120L is used to form a reference output terminal 120A, or the magnetic free layers 1002 of multiple parallel state reference units 120L are coupled to form a reference output terminal 120A, so that during a read operation, the direction of the read current passing through the parallel state reference unit 120L is consistent with the direction of the magnetic free layer 1002 pointing to the magnetic fixed layer 1001, that is, the direction of the read current passing through the parallel state reference unit 120L is consistent with the current direction of writing 0, and the parallel state reference unit 120L is already in a parallel state, thereby ensuring that after a long period of read operation, the resistance state of the parallel state reference unit 120L is not easily flipped.

[0108] In the present embodiment, the magnetic tunnel junction 100 is bottom magnetically fixed, and the reference unit 120 includes one or more parallel state reference units 120L, and the magnetic free layer 1002 of one of the parallel state reference units 120L is used to form a reference output terminal 120A, or the magnetic free layers 1001 of multiple parallel state reference units 120L are coupled to form a reference output terminal 120A. Therefore, when a read operation is performed, the direction of the read current passing through the magnetic tunnel junction 100 of the parallel state reference unit 120L is consistent with the direction of the magnetic free layer 1002 pointing to the magnetic fixed layer 1001, and there is no need to change the structure of the circuit, which is beneficial to reducing the complexity of the circuit design and improving the compatibility with the existing circuit structure.

[0109] Accordingly, in this embodiment, the magnetic free layer 1001 of the data unit 110 is coupled to the load circuit 140 .

[0110] Specifically, the drain of the selection transistor N0 in the data unit 110 is coupled to the magnetic fixed layer 1001 of the magnetic tunnel junction 100 , and the source of the selection transistor N0 in the data unit 110 is grounded to VSS.

[0111] Accordingly, in the present embodiment, in the parallel state reference unit 120L, the drain of the selection transistor N0 is coupled to the magnetic fixed layer 1001 of the magnetic tunnel junction 100 , and the source of the selection transistor N0 is grounded to VSS.

[0112] In this embodiment, during the read operation, the direction of the read current is the direction along the reference output terminal 120A pointing to the ground terminal VSS. Specifically, in the parallel state reference unit 120L, the direction of the read current passing through the magnetic tunnel junction 100 is consistent with the direction of the magnetic free layer 1002 pointing to the magnetic fixed layer 1001, that is, the same as the current direction of writing the magnetic tunnel junction 100 to a low resistance state or a parallel state, and the magnetic tunnel junction 100 in the parallel state reference unit 120L is already in a low resistance state, thereby preventing the resistance state of the parallel state reference unit 120L from flipping.

[0113] Accordingly, the present invention also provides a storage array according to another embodiment. The similarities between the embodiment of the present invention and the above embodiment are not repeated here. The difference between the embodiment of the present invention and the above embodiment is that:

[0114] The magnetic tunnel junction is top magnetically fixed, and the magnetic tunnel junction includes a magnetic free layer and a magnetic fixed layer located on the magnetic free layer. The reference unit includes one or more antiparallel state reference units, and the magnetic fixed layer of an antiparallel state reference unit is used to form a reference output terminal, or the magnetic fixed layers of multiple antiparallel state reference units are coupled to form a reference output terminal.

[0115] In a specific implementation, the reference unit includes a plurality of antiparallel state reference units, and the magnetic fixed layers of the plurality of antiparallel state reference units are coupled to form the reference output terminal.

[0116] In this embodiment, the magnetic fixed layer of the data unit is coupled to the load circuit. In this embodiment, the memory unit further comprises a selection transistor connected to the magnetic tunnel junction, and the gate of the selection transistor is coupled to the word line.

[0117] Accordingly, in this embodiment, in the data unit, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded. In this embodiment, in the antiparallel reference unit, the magnetic fixed layer of the magnetic tunnel junction is used to form a reference output terminal, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded.

[0118] In MRAM, the direction of the write current that writes the magnetic tunnel junction from a high resistance state to a low resistance state is consistent with the direction of the magnetic free layer pointing to the magnetic fixed layer, and the direction of the write current that writes the magnetic tunnel junction from a low resistance state to a high resistance state is consistent with the direction of the magnetic fixed layer pointing to the magnetic free layer.

[0119] In this embodiment, during the read operation, the direction of the read current is the direction from the reference output terminal to the ground terminal. Specifically, in the antiparallel state reference unit, the direction of the read current passing through the magnetic tunnel junction is consistent with the direction from the magnetic fixed layer to the magnetic free layer, that is, the same as the current direction for writing the magnetic tunnel junction to a high resistance state, and the magnetic tunnel junction in the antiparallel state reference unit is already in a high resistance state, thereby preventing the resistance state of the antiparallel state reference unit from flipping.

[0120] In the present embodiment, the magnetic tunnel junction is fixed in the top magnetic direction, and the reference unit includes one or more antiparallel reference units, and the magnetic fixed layer of an antiparallel reference unit is used to form a reference output terminal, or the magnetic fixed layers of multiple antiparallel reference units are coupled to form a reference output terminal. Therefore, when a read operation is satisfied, the direction of the read current passing through the magnetic tunnel junction of the antiparallel reference unit is consistent with the direction of the magnetic fixed layer pointing to the magnetic free layer, and there is no need to change the structure of the circuit, which is beneficial to reducing the complexity of the circuit design and improving the compatibility with the existing circuit structure.

[0121] For the specific description of the storage array described in this embodiment, reference may be made to the corresponding description in the aforementioned embodiments, and this embodiment will not be repeated here.

[0122] Correspondingly, an embodiment of the present invention further provides an electronic device, which includes: the magnetic random access memory provided by an embodiment of the present invention.

[0123] As can be seen from the above records, in the magnetic random access memory provided by the above embodiments, the resistance state of the reference unit is less likely to be flipped during a read operation, thereby providing a more reliable reference resistance for data reading of the data unit, ensuring the reliability of the reference unit, thereby improving the data reading accuracy of the MRAM, and correspondingly improving the reliability of the MRAM. Accordingly, the performance of the electronic device provided by the present embodiment is also improved, for example: improving the data reading accuracy is conducive to optimizing the user experience and perception.

[0124] In this embodiment, the electronic device may be an electronic device capable of storing and reading data, such as a chip, a mobile phone, a computer, a vehicle-mounted electronic product, and the like.

[0125] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.< / n>

Claims

1. A magnetic random access memory, characterized in that: include: A driving signal module, used for providing a reading signal; A memory array, comprising a plurality of memory cells arranged in an array, wherein the memory cells comprise a magnetic tunnel junction, and the magnetic tunnel junction comprises a magnetic fixed layer and a magnetic free layer arranged opposite to each other; Define a storage unit for data to be read as a data unit, and the data unit is used to load the read signal to output a data voltage; A storage unit used as a reference for data reading is defined as a reference unit, wherein the reference unit includes one or more parallel state reference units, a magnetic free layer of one of the parallel state reference units is used to form a reference output terminal, or a plurality of magnetic free layers of the parallel state reference units are coupled to form a reference output terminal; or, the reference unit includes one or more anti-parallel state reference units, a magnetic fixed layer of one of the anti-parallel state reference units is used to form a reference output terminal, or a plurality of magnetic fixed layers of the anti-parallel state reference units are coupled to form a reference output terminal; The reference unit is used to load the read signal and output a reference voltage through the reference output terminal; The comparison circuit is used to read the data of the data unit according to the relative magnitudes of the data voltage and the reference voltage.

2. The magnetic random access memory according to claim 1, wherein: The magnetic tunnel junction includes a magnetic fixed layer and a magnetic free layer located on the magnetic fixed layer; Alternatively, the magnetic tunnel junction includes a magnetic free layer and a magnetic fixed layer located on the magnetic free layer.

3. The magnetic random access memory according to claim 2, characterized in that: The magnetic tunnel junction includes a magnetic fixed layer and a magnetic free layer located on the magnetic fixed layer; The reference unit includes one or more parallel state reference units, the magnetic free layer of one of the parallel state reference units is used to form the reference output end, or the magnetic free layers of a plurality of the parallel state reference units are coupled to form the reference output end.

4. The magnetic random access memory according to claim 2, wherein: The magnetic tunnel junction includes a magnetic free layer and a magnetic fixed layer located on the magnetic free layer; The reference unit includes one or more antiparallel state reference units, and the magnetic fixed layer of one antiparallel state reference unit is used to form the reference output terminal, or the magnetic fixed layers of multiple antiparallel state reference units are coupled to form the reference output terminal.

5. The magnetic random access memory according to claim 3, characterized in that: The memory cell further comprises a selection transistor connected to the magnetic tunnel junction, wherein a gate of the selection transistor is coupled to a word line; In the data unit, the drain of the selection transistor is coupled to the magnetic fixed layer of the magnetic tunnel junction, and the source of the selection transistor is grounded; In the parallel state reference unit, the drain of the selection transistor is coupled to the magnetic fixed layer of the magnetic tunnel junction, and the source of the selection transistor is grounded.

6. The magnetic random access memory according to claim 4, characterized in that: The memory cell further comprises a selection transistor connected to the magnetic tunnel junction, wherein a gate of the selection transistor is coupled to a word line; In the data unit, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded; In the antiparallel state reference unit, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded.

7. The magnetic random access memory according to claim 1, wherein: The driving signal module is used to provide a bit line voltage, the reference unit is used to load the bit line voltage and output a reference current through the reference output terminal, and the data unit is used to load the bit line voltage and output a data current; The magnetic random access memory further comprises: a load circuit coupled to the data unit and to the reference output terminal; the load circuit is used to convert the data current of the data unit into a data voltage and to convert the reference current of the reference unit into a reference voltage.

8. The magnetic random access memory according to claim 7, wherein: The driving signal module comprises: A clamp circuit coupled to the load circuit, the clamp circuit being used to provide a bit line voltage to the data cell and the reference cell, and to clamp the bit line voltage of the data cell and the reference cell; A bit line selection circuit has one end coupled to the clamp circuit and the other end correspondingly coupled to the data unit and the reference output end. The bit line selection circuit is suitable for selecting the data unit to be read and the reference unit.

9. The magnetic random access memory according to claim 8, characterized in that: The clamp circuit comprises an NMOS tube, a drain of the NMOS tube is coupled to the load circuit, a source of the NMOS tube is coupled to the bit line selection circuit, and a gate is used to load a clamp control signal; During a read operation, the voltage applied to the gate of the NMOS tube is the sum of the threshold voltage of the NMOS tube and the bit line voltage.

10. The magnetic random access memory according to claim 7, wherein: The load circuit is a current mirror.

11. The magnetic random access memory according to claim 10, wherein: The reference unit includes one or more parallel reference units; the number of the parallel reference units is M, where M is a positive integer; in the current mirror, the mirror ratio from the reference unit to the data unit is x:1, where x is Within the range of ±10%; Alternatively, the reference unit includes one or more antiparallel reference units, and in the current mirror, the mirror ratio from the reference unit to the data unit is x:1, where x is Within the range of ±10%; in, is the average resistance of the reference cell magnetic tunnel junction in the antiparallel state, is the average resistance of the parallel state reference unit magnetic tunnel junction.

12. The magnetic random access memory according to claim 10, wherein: The reference unit includes one or more parallel reference units; the number of the parallel reference units is M, where M is a positive integer; in the current mirror, the mirror ratio from the reference unit to the data unit is x:1; x is Within the range of ±10%; Alternatively, the reference unit includes one or more antiparallel reference units, and in the current mirror, the mirror ratio from the reference unit to the data unit is x:1; Within the range of ±10%; in, is the average resistance of the reference cell magnetic tunnel junction in the antiparallel state, is the average resistance of the parallel state reference unit magnetic tunnel junction, and σ is the standard deviation.

13. The magnetic random access memory according to claim 1, wherein: The comparison circuit includes a first input terminal, a second input terminal and an output terminal, the first input terminal is coupled to the data unit, the second input terminal is coupled to the reference output terminal, and the output terminal is used to output a comparison result signal.

14. A storage array, applied to a magnetic random access memory, the magnetic random access memory comprising: A driving signal module, used for providing a read signal to the storage array; A comparison circuit, used for reading data of the storage array according to the relative magnitudes of the data voltage output by the storage array and the reference voltage; The storage array is characterized by comprising: A plurality of memory cells arranged in an array, wherein the memory cells include a magnetic tunnel junction, and the magnetic tunnel junction includes a magnetic fixed layer and a magnetic free layer arranged opposite to each other; Define a storage unit for data to be read as a data unit, and the data unit is used to load the read signal and output the data voltage; A storage unit used as a reference for data reading is defined as a reference unit, wherein the reference unit includes one or more parallel state reference units, a magnetic free layer of the parallel state reference unit is used to form a reference output terminal, or a plurality of magnetic free layers of the parallel state reference units are coupled to form a reference output terminal; or, the reference unit includes one or more anti-parallel state reference units, a magnetic fixed layer of the anti-parallel state reference unit is used to form a reference output terminal, or a plurality of magnetic fixed layers of the anti-parallel state reference units are coupled to form a reference output terminal; the reference unit is used to load the read signal and output the reference voltage through the reference output terminal.

15. The storage array according to claim 14, wherein: The magnetic tunnel junction includes a magnetic fixed layer and a magnetic free layer located on the magnetic fixed layer; or the magnetic tunnel junction includes a magnetic free layer and a magnetic fixed layer located on the magnetic free layer.

16. The storage array according to claim 15, wherein: The magnetic tunnel junction includes a magnetic fixed layer and a magnetic free layer located on the magnetic fixed layer; The reference unit includes one or more parallel state reference units, the magnetic free layer of one of the parallel state reference units is used to form the reference output end, or the magnetic free layers of a plurality of the parallel state reference units are coupled to form the reference output end.

17. The storage array according to claim 15, wherein: The magnetic tunnel junction includes a magnetic free layer and a magnetic fixed layer located on the magnetic free layer; The reference unit includes one or more antiparallel state reference units, and the magnetic fixed layer of one antiparallel state reference unit is used to form the reference output terminal, or the magnetic fixed layers of multiple antiparallel state reference units are coupled to form the reference output terminal.

18. The storage array according to claim 16, wherein: The memory cell further comprises a selection transistor connected to the magnetic tunnel junction, wherein a gate of the selection transistor is coupled to a word line; In the data unit, the drain of the selection transistor is coupled to the magnetic fixed layer of the magnetic tunnel junction, and the source of the selection transistor is grounded; In the parallel state reference unit, the drain of the selection transistor is coupled to the magnetic fixed layer of the magnetic tunnel junction, and the source of the selection transistor is grounded.

19. The storage array according to claim 17, wherein: The memory cell further comprises a selection transistor connected to the magnetic tunnel junction, wherein a gate of the selection transistor is coupled to a word line; In the data unit, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded; In the antiparallel state reference unit, the drain of the selection transistor is coupled to the magnetic free layer of the magnetic tunnel junction, and the source of the selection transistor is grounded.

20. An electronic device, characterized in that: It comprises the magnetic random access memory as claimed in any one of claims 1 to 13.

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