A calibration quantity determination method and a current sampling circuit of a chip

Abstract

The present application provides a calibration amount determination method and a current sampling circuit of a chip. The method is applied to the current sampling circuit of the chip, including: respectively obtaining a detection voltage of the current sampling circuit and an auxiliary detection voltage of the auxiliary detection circuit; the auxiliary detection circuit is constructed based on the current sampling circuit and is used to eliminate the proportional offset error existing in the I-V conversion resistor in the current sampling circuit; based on the detection voltage and the auxiliary detection voltage constructor, the proportional offset calibration amount and the DC offset calibration amount of the detection circuit are determined; that is, the calibration amount determination method provided in the present application can determine the proportional offset calibration amount required to eliminate the proportional offset error existing in the I-V conversion resistor in the current sampling circuit of the chip, and the DC offset calibration amount required to eliminate the DC offset error existing in the current sampling circuit of the chip through the constructor, thereby improving the accuracy of the current sampling circuit of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a calibration value determination method and a current sampling circuit of a chip. Background Art

[0002] In any mature circuit product, a high-performance power management system is required, and a high-performance power management system cannot be separated from a high-precision current sampling circuit. In a typical battery management system, it is necessary to monitor the current of the input bus (BUS) or the charge and discharge current of the battery terminal (BAT) in real time, and use this as a reference to adjust system parameters to improve the charge and discharge performance, and provide corresponding overcurrent, current limiting, undercurrent and reverse current protection functions. The accuracy of current sampling directly affects the performance and safety of the power management IC and the subsequent system.

[0003] like Figure 1 As shown, the existing current sampling scheme directly uses the virtual short characteristic of the op amp to clamp the MN working in the linear region. SNS Tube and MN POWER V at both ends of the tube DS The pressure drop is equal, so that the flow through MN SNS Tube and flow through MN POWER The current flowing through the tube is linearly proportional to SNS The detection current of the tube I SNS Through an IV conversion resistor R T Convert to V SNS voltage, so there is Among them, I POWER Represents flow through MN POWER The actual current of the tube, K represents MN SNS Tube and MN POWER The actual ratio of the on-resistance of the tube, V OS Represents the equivalent input offset voltage across the clamped op amp, R SNS Represents MN SNS The DC conduction resistance of the tube, R T Represents the actual resistance value of the IV conversion resistor. The inventor has found that the subsequent ADC quantification of V SNS Voltage and read the quantized data to the host computer, and when the data is processed by software, there is

[0004]

[0005] Among them, I POWER_CAL Represents the flow through MN obtained after detection POWER The current of the tube, K0 represents MN SNS Tube and MN POWER The design ratio of the on-resistance of the tube, RT0 Represents the design resistance value of the IV conversion resistor, Represents R T Relative R T0 The relative deviation of Represents the relative deviation of K from K0, R POWER Represents MN POWER The DC conduction impedance of the tube.

[0006] Ideally I POWER_CAL =I POWER However, due to the influence of temperature and process manufacturing deviation in the existing technology, there is an equivalent input offset voltage VOS at the input of the op amp, and the actual manufacturing value of the IV conversion resistor, MN SNS Tube and MN POWER There is a large deviation from the relative design value of the on-resistance of the tube, so the current detection accuracy represented by the traditional solution is low. Summary of the invention

[0007] In this regard, the present application provides a calibration value determination method and a current sampling circuit of a chip to solve the problem that the existing current sampling circuit is caused by the actual manufacturing value of the IV conversion resistor, MN SNS Tube and MN POWER There is a large deviation in the relative design value of the on-resistance of the tube, and the current sampling accuracy is low.

[0008] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0009] A first aspect of the present invention discloses a calibration value determination method, which is applied to a current sampling circuit of a chip, and the method comprises:

[0010] Respectively obtaining a sampling voltage of the current sampling circuit and an auxiliary detection voltage of the auxiliary detection circuit; the auxiliary detection circuit is constructed based on the current sampling circuit and is used to eliminate the proportional imbalance error of the IV conversion resistor in the current sampling circuit;

[0011] Based on the sampling voltage and the auxiliary detection voltage constructor, the proportional offset calibration amount and the DC offset calibration amount of the current sampling circuit are determined; wherein the proportional offset calibration amount is used to calibrate the proportional offset error of the IV conversion resistor, and the DC offset calibration amount is used to calibrate the DC offset error of the current sampling circuit.

[0012] Optionally, the calibration amount determination method described above, respectively obtaining the sampling voltage and the auxiliary detection voltage of the current sampling circuit, includes:

[0013] Collecting the voltage of the corresponding output port in the current sampling circuit to obtain the sampled voltage;

[0014] The voltage output by the auxiliary detection circuit is collected to obtain the auxiliary detection voltage.

[0015] Optionally, the calibration amount determination method, based on the sampled voltage and the auxiliary detection voltage constructor, determines the proportional offset calibration amount and the DC offset calibration amount of the detection circuit, including:

[0016] Based on the sampling voltage and the auxiliary detection voltage, respectively determining a calculation expression of the sampling voltage and an expression of the auxiliary detection voltage;

[0017] Based on the calculation expression of the sampling voltage and the calculation expression of the auxiliary detection voltage, construct a function expression of the current flowing through the power transistor in the chip;

[0018] The calculation expression of the sampling voltage, the calculation expression of the auxiliary detection voltage and the current function expression are processed to obtain the proportional offset calibration amount and the DC offset calibration amount of the detection circuit.

[0019] Optionally, the calibration amount determination method described above processes the calculation expression of the sampling voltage, the calculation expression of the auxiliary detection voltage, and the current function expression to obtain the proportional offset calibration amount and the DC offset calibration amount of the detection circuit, including:

[0020] Substituting the calculation expression of the sampling voltage and the calculation expression of the auxiliary detection voltage into the current function expression respectively to obtain a complete function expression;

[0021] The complete function expression is trimmed to obtain a trimmed complete function expression, and a proportional offset calibration amount and a DC offset calibration amount of the detection circuit are determined based on the trimmed complete function expression.

[0022] Optionally, in the above calibration value determination method, the calculation expression of the sampled voltage is: Among them, the V SNS_ADC represents the sampling voltage, m represents the proportional coefficient of the current unit in the current sampling circuit, I POWER represents the actual current flowing through the power transistor, K represents the actual ratio of the on-resistance of the current detection transistor in the current sampling circuit to that of the power transistor, V OS Represents the equivalent input offset voltage across the clamped op amp, R SNS represents the DC on-resistance of the current sensing transistor, R T Indicates the actual resistance value of the IV conversion resistor;

[0023] The auxiliary detection voltage expression is: VREF_ADC =I REF_ADC ·R REF_ADC ; Among them, V REF_ADC represents the auxiliary detection voltage, I REF_ADC Represents the zero temperature coefficient reference current, R REF_ADC Indicates the resistance value of a resistor of the same type as the IV conversion resistor;

[0024] The current function expression is: Among them, I POWER_ADL represents the detection current flowing through the power transistor, I REF_ADC0 Indicates I REF_ADC The design value, R REF_ADC0 Represents R REF_ADC The design value, R T0 Represents R T The design value of K0 is the design value of K, m o represents the design value of m.

[0025] Optionally, in the above calibration amount determination method, the complete function expression is:

[0026]

[0027] The complete function expression of the adjustment is:

[0028] in, represents the proportional imbalance calibration amount, I OS_TRIM represents the DC offset calibration amount.

[0029] The second aspect of the present invention discloses a current sampling circuit of a chip, comprising: a first current sampling circuit, a first current adjustment unit and a first IV conversion resistor;

[0030] Wherein, the first current sampling circuit is used to sample a first direction current flowing through a corresponding power transistor in the chip in a first direction;

[0031] The first current adjustment unit is used to adjust the first direction current; the DC offset calibration amount in the first current adjustment unit is determined by the calibration amount determination method described in any one of the first aspects disclosed, using the first direction voltage as the sampling voltage;

[0032] The first IV conversion resistor is used to convert the first direction current into a first direction voltage; the proportional imbalance calibration amount in the first IV conversion resistor is determined by any calibration amount determination method disclosed in the first aspect, using the first direction voltage as the sampling voltage.

[0033] Optionally, the current sampling circuit of the above chip further includes: a second current sampling circuit, a second current adjustment unit and a second IV conversion resistor;

[0034] Wherein, the second current sampling circuit is used to sample a second direction current flowing through the corresponding power transistor in the chip from a second direction; the first direction and the second direction are different directions;

[0035] The second current adjustment unit is used to adjust the second direction current; the DC offset calibration amount in the second current adjustment unit is the same as that in the first current adjustment unit;

[0036] The second IV conversion resistor is used to convert the second direction current into a second direction voltage; and the proportional imbalance calibration amount in the second IV conversion resistor is the same as that in the first IV conversion resistor.

[0037] Optionally, the current sampling circuit of the above chip further includes: a selector; wherein the selector is used to select to output the first direction voltage or the second direction voltage.

[0038] Optionally, in the current sampling circuit of the above chip, the first current adjustment unit and the second current adjustment unit are both two-stage adjustment type cascode current mirrors.

[0039] Optionally, the current sampling circuit of the above chip further includes: a filtering and buffering processing unit, configured to perform filtering and buffering processing on the first direction voltage.

[0040] Optionally, in the current sampling circuit of the above chip, the first current sampling circuit comprises: a first NMOS tube, a first PMOS tube and a first operational amplifier;

[0041] The second end of the first NMOS tube is connected to the power input end of the chip, and the first end of the first NMOS tube is connected to the first end of the first PMOS tube and the inverting input end of the first operational amplifier respectively;

[0042] The in-phase input terminal of the first operational amplifier is connected to the middle power node of the chip; the output terminal of the first operational amplifier is connected to the control terminal of the first PMOS tube, and the second terminal of the first PMOS tube serves as the output terminal of the first current sampling circuit to output the first direction current.

[0043] Optionally, in the current sampling circuit of the above chip, the second current sampling circuit comprises: a second NMOS tube, a second PMOS tube and a second operational amplifier;

[0044] The second end of the second NMOS tube is connected to the middle power node of the chip, and the first end of the second NMOS tube is connected to the first end of the second PMOS tube and the inverting input end of the second operational amplifier respectively;

[0045] The in-phase input terminal of the second operational amplifier is connected to the power input terminal of the chip; the output terminal of the second operational amplifier is connected to the control terminal of the second PMOS tube, and the second terminal of the second PMOS tube serves as the output terminal of the second current sampling circuit to output the second direction current.

[0046] The calibration amount determination method provided by the present invention is applied to the current sampling circuit of the chip, comprising: respectively obtaining the sampling voltage of the current sampling circuit and the auxiliary detection voltage of the auxiliary detection circuit; the auxiliary detection circuit is constructed based on the current sampling circuit and is used to eliminate the proportional offset error of the IV conversion resistor in the current sampling circuit; based on the sampling voltage and the auxiliary detection voltage constructor, the proportional offset calibration amount and the DC offset calibration amount of the current sampling circuit are determined; wherein the proportional offset calibration amount is used to calibrate the proportional offset error of the IV conversion resistor, and the DC offset calibration amount is used to calibrate the DC offset error of the current sampling circuit; that is, the calibration amount determination method provided by the present application can determine the proportional offset calibration amount required to eliminate the proportional offset error of the IV conversion resistor in the current sampling circuit of the chip and the DC offset calibration amount required to eliminate the DC offset error in the current sampling circuit of the chip through the constructor, thereby improving the accuracy of the current sampling circuit of the chip and avoiding the existing current sampling circuit being affected by the actual manufacturing value of the IV conversion resistor, MN SNS Tube and MN POWER There is a large deviation in the relative design value of the on-resistance of the tube, and the current sampling accuracy is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0048] Figure 1 A schematic diagram of the structure of an existing current sampling circuit provided in an embodiment of the present application;

[0049] Figure 2 A flowchart of a calibration amount determination method provided in an embodiment of the present application;

[0050] Figure 3A schematic diagram of the structure of an auxiliary detection circuit provided in an embodiment of the present application;

[0051] Figure 4 A schematic diagram of the structure of a current sampling circuit of a chip provided in an embodiment of the present application;

[0052] Figure 5 and Figure 6 Two flow charts for respectively determining a proportional offset calibration amount and a DC offset calibration amount are provided in the embodiments of the present application;

[0053] Figure 7 A schematic diagram of the structure of a current sampling circuit of a chip provided in an embodiment of the present application;

[0054] Figure 8 A schematic diagram of the structure of a current sampling circuit of another chip provided in an embodiment of the present application;

[0055] Fig. 9 A comparison diagram of the sampling current calibration straight line and the sampling current true straight line provided in the embodiment of the present application. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] The present application provides a calibration value determination method to solve the problem that the current sampling circuit of the existing current sampling circuit is caused by the actual manufacturing value of the IV conversion resistor, MN SNS Tube and MN POWER There is a large deviation in the relative design value of the on-resistance of the tube, and the current sampling accuracy is low.

[0058] See also Figure 2 and Figure 3 The calibration amount determination method is applied to the current sampling circuit of the chip, and the calibration amount determination method may include the following steps:

[0059] S100 , respectively obtaining a sampling voltage of a current sampling circuit and an auxiliary detection voltage of an auxiliary detection circuit.

[0060] Among them, the auxiliary detection circuit is constructed based on the current sampling circuit and is used to eliminate the proportional imbalance error existing in the IV conversion resistor in the current sampling circuit.

[0061] In practical applications, combined with Figure 3The auxiliary detection circuit may include: a third PMOS tube MP1, a fourth PMOS tube MP2, a fourth operational amplifier OP4, a third NMOS tube MN1, a first resistor R NTC , the second resistor R PTC And the third resistor R REF_ADC The first end of the third PMOS tube MP1 is connected to the first end of the fourth PMOS tube MP2 to receive the power supply voltage; the control end of the third PMOS tube MP1 is respectively connected to the control end of the fourth PMOS tube MP2, the second end of the third PMOS tube MP1 and the second end of the third NMOS tube MN1; the control end of the third NMOS tube MN1 is connected to the output end of the fourth operational amplifier OP4; the in-phase input end of the fourth operational amplifier OP4 receives the reference voltage V REFOP5 The inverting input terminal of the fourth operational amplifier OP4 is connected to the first terminal of the third NMOS tube MN1 and the first resistor R NTC One end of the first resistor R NTC The other end passes through the second resistor R PTC ground; the second end of the fourth PMOS tube MP2 and the third resistor R REF_ADC The connection point is used as the output end of the auxiliary detection circuit to output the auxiliary detection voltage; the third resistor R REF_ADC The other end is grounded.

[0062] It should be noted that the third resistor R REF_ADC The type is the same as the IV conversion resistor in the current detection chip of the chip. For example, both can be polysilicon resistors at the same time; of course, the resistor type can also be customized according to the specific application environment and user needs. This application does not make specific limitations on it and it all falls within the protection scope of this application.

[0063] In practical applications, in order to ensure the high accuracy of current detection of the chip's circuit detection circuit over the full temperature range, it is generally necessary to ensure that the detection current I flowing through the power transistor in the chip POWER_ADL is a zero temperature coefficient reference current. In order to meet this condition, a zero temperature coefficient reference voltage is generally loaded to the first resistor R after temperature compensation. NTC and the second resistor R PTC Produced on.

[0064] In practical applications, the sampling voltage can be obtained by collecting the voltage of the corresponding output port in the current sampling circuit. Figure 4 , the sampling voltage can be V SNS1 or V SNS_ADC The auxiliary detection voltage can be obtained by collecting the voltage output by the auxiliary detection circuit. Figure 3 , the auxiliary detection voltage can be VREF_ADC .

[0065] S102 : Determine a proportional offset calibration amount and a DC offset calibration amount of a detection circuit based on the sampling voltage and the auxiliary detection voltage constructor.

[0066] The proportional offset calibration value is used to calibrate the proportional offset error existing in the IV conversion resistor, and the DC offset calibration value is used to calibrate the DC offset error existing in the current sampling circuit.

[0067] In practical applications, the specific execution process of step S102, determining the proportional offset calibration amount and the DC offset calibration amount of the detection circuit based on the sampling voltage and the auxiliary detection voltage constructor, can be as follows: Figure 5 As shown, it mainly includes the following steps:

[0068] S200 , based on the sampling voltage and the auxiliary detection voltage, respectively determine a calculation expression of the sampling voltage and an expression of the auxiliary detection voltage.

[0069] In practical applications, combined with Figure 4 , the calculation expression of the sampling voltage can be: Among them, V SNS_ADC represents the sampling voltage, m represents the proportional coefficient of the current unit in the current sampling circuit, I POWER represents the actual current flowing through the power transistor, K represents the actual ratio of the on-resistance of the current detection transistor and the power transistor in the current sampling circuit, V OS Represents the equivalent input offset voltage across the clamped op amp, R SNS represents the DC on-resistance of the current sensing transistor, R T Indicates the actual resistance value of the IV conversion resistor.

[0070] In practical applications, combined with Figure 3 , the auxiliary detection voltage can be expressed as: V REF_ADC =I REF_ADC ·R REF_ADC Among them, V REF_ADC Indicates the auxiliary detection voltage, I REF_ADC Represents the zero temperature coefficient reference current, R REF_ADC Indicates the resistance value of a resistor of the same type as the IV conversion resistor.

[0071] S202: construct a function expression of the current flowing through the power transistor in the chip based on the calculation expression of the sampling voltage and the calculation expression of the auxiliary detection voltage.

[0072] Among them, the sampling voltage and the auxiliary detection voltage can be quantified by ADC to obtain the numerical value of the sampling voltage and the numerical value of the auxiliary detection voltage, and then the calculation expression of the sampling voltage and the calculation expression of the auxiliary detection voltage are used to obtain the current function expression flowing through the power transistor in the chip through software construction.

[0073] Specifically, the current function expression can be:

[0074] Among them, I POWER_ADL Represents the detection current flowing through the power transistor, I REF_ADC0 Indicates I REF_ADC The design value, R REF_ADC0 Represents R REF_ADC The design value, R T0 Represents R T The design value of K0 is the design value of K, m o represents the design value of m.

[0075] S204, processing the calculation expression of the sampling voltage, the calculation expression of the auxiliary detection voltage and the current function expression to obtain the proportional offset calibration amount and the DC offset calibration amount of the detection circuit.

[0076] In practical applications, the specific process of executing step S204, processing the calculation expression of the sampling voltage, the calculation expression of the auxiliary detection voltage and the current function expression to obtain the proportional offset calibration amount and the DC offset calibration amount of the detection circuit can be as follows: Figure 6 As shown, it mainly includes the following steps:

[0077] S300 , substituting the calculation expression of the sampling voltage and the calculation expression of the auxiliary detection voltage into the current function expression respectively to obtain a complete function expression.

[0078] Among them, the complete function expression can be:

[0079]

[0080] It should be noted that in the complete function expression, the same type of resistors are used, and the proportional vector is very small, and the 3-Sigma error is about 0.1%, so it can be approximately considered that Therefore, the I POWER_ADL Front Since a current mirror is used in the current sampling circuit and the area of ​​the current mirror transistor is increased, the vector of m is very small and the 3-Sigma error is about 0.1%. Therefore, it can be considered that In addition, in order to ensure high accuracy of current sampling over the entire temperature range, it is generally necessary to ensure that the detection current I flowing through the power transistor in the chipPOWER_ADL is a zero temperature coefficient reference current. In order to meet this condition, a zero temperature coefficient reference voltage is also loaded on the first resistor R after temperature compensation in the auxiliary detection circuit. NTC and the second resistor R PTC Produced on.

[0081] S302, performing trimming processing on the complete function expression to obtain a trimmed complete function expression, and determining a proportional offset calibration amount and a DC offset calibration amount of the detection circuit based on the trimmed complete function expression.

[0082] Among them, the modified complete function expression can be:

[0083] in, Indicates the proportional imbalance calibration amount, I OS_TRIM Indicates the DC offset calibration amount.

[0084] It should be noted that the proportional offset calibration amount is to adjust the IV conversion resistor due to process manufacturing error and temperature drift error, so as to eliminate the process manufacturing error and temperature drift error of the IV conversion resistor, thereby improving the sampling accuracy of the current sampling circuit of the chip.

[0085] Based on the above principles, the calibration amount determination method provided in this embodiment is applied to the current sampling circuit of the chip, including: respectively obtaining the detection voltage of the current sampling circuit and the auxiliary detection voltage of the auxiliary detection circuit; the auxiliary detection circuit is constructed based on the current sampling circuit, and is used to eliminate the proportional offset error of the IV conversion resistor in the current sampling circuit; based on the detection voltage and the auxiliary detection voltage constructor, the proportional offset calibration amount and the DC offset calibration amount of the detection circuit are determined; wherein the proportional offset calibration amount is used to calibrate the proportional offset error of the IV conversion resistor, and the DC offset calibration amount is used to calibrate the DC offset error of the current sampling circuit; that is, the calibration amount determination method provided in the present application can determine the proportional offset calibration amount required to eliminate the proportional offset error of the IV conversion resistor in the current sampling circuit of the chip, and the DC offset calibration amount required to eliminate the DC offset error in the current sampling circuit of the chip through the constructor, thereby improving the accuracy of the current sampling circuit of the chip and avoiding the existing current sampling circuit due to the actual manufacturing value of the IV conversion resistor, MN SNS Tube and MN POWER There is a large deviation in the relative design value of the on-resistance of the tube, and the current sampling accuracy is low.

[0086] Based on the calibration value determination method provided above, another embodiment of the present application further provides a current sampling circuit of a chip, see Figure 7The current sampling circuit mainly includes: a first current sampling circuit 101, a first current adjustment unit 102 and a first IV conversion resistor R T1 .

[0087] The first current sampling circuit 101 is used to sample a first direction current flowing through a corresponding power transistor in the chip in a first direction.

[0088] In practical applications, such as Figure 7 As shown, the first current sampling circuit 101 may include: a first NMOS transistor MN SNS1 , the first PMOS tube MP REG1 And the first operational amplifier HV_OP1. Among them, the first NMOS tube MN SNS1 The second end of the first NMOS tube MN is connected to the power input terminal of the chip (BUS in the figure). SNS1 The first end of the first PMOS tube MP REG1 The first end of the first operational amplifier HV_OP1 is connected to the inverting input end of the first operational amplifier HV_OP1; the non-inverting input end of the first operational amplifier HV_OP1 is connected to the middle power node of the chip (PMID in the figure); the output end of the first operational amplifier HV_OP1 is connected to the first PMOS tube MP REG1 The control end of the first PMOS tube MP REG1 The second end of the first current sampling circuit 101 is used as the output end of the first current sampling circuit 101 to output the first direction current I SNS1_INI .

[0089] It should be noted that the first end in this embodiment represents the source, that is, Figure 8 The first end is the end with an arrow in the figure; the second end represents the drain, that is, the end without an arrow in the figure; the control end represents the gate.

[0090] The first current adjustment unit 102 is used to adjust the current in the first direction. The DC offset calibration value in the first current adjustment unit 102 is determined by the calibration value determination method provided by any of the above embodiments, using the first direction voltage as the detection voltage.

[0091] In practical applications, such as Figure 7 As shown, the first current adjustment unit 102 may be a two-stage adjustable cascode current mirror. The proportional coefficient of the first stage adjustable cascode current mirror of the first current adjustment unit 102 may be 1:m1, and the proportional coefficient of the second stage adjustable cascode current mirror of the first current adjustment unit 102 may be 1:m2. Wherein, m=m1·m2.

[0092] It should be noted that by adjusting the ratio between the two-stage adjustable cascode current mirrors according to the DC offset calibration amount, the DC vector error caused by the first current adjustment unit 102 in the current sampling circuit can be eliminated. The two-stage adjustable cascode current mirrors in the first current adjustment unit 102 are generally controlled by controlling the current source ( Figure 7 The current source between the two) is turned on and off, which affects the fixed offset current of the current sampling circuit (V OS ) to perform trim calibration.

[0093] The first IV conversion resistor R T1 The first IV conversion resistor R is used to convert the first direction current into the first direction voltage. T1 The proportional imbalance calibration amount is determined by the calibration amount determination method provided by any of the above embodiments, using the first direction voltage as the detection voltage.

[0094] In practical applications, such as Figure 7 As shown, the first IV conversion resistor R T1 One end of the current mirror is connected to the output end of the second-stage adjustable cascode current mirror, and the connection point is used as the output end to output the first direction voltage V SNS1 The first IV conversion resistor R T1 The other end is grounded.

[0095] It should be noted that the first direction voltage V SNS1 It is directly transmitted to the subsequent ADC for quantization to obtain the current detection value of the chip. However, under normal circumstances, the current to be sampled in the chip is not a DC current waveform with a constant amplitude, but a current waveform with a certain ripple similar to a sine wave. Therefore, in order to eliminate the influence of the ripple on the current detection value, Figure 7 As shown, a filter buffer processing unit 301 may be provided to perform filter buffer processing on the first direction voltage. The filter buffer processing unit 301 may include a low-pass filter LPF_1 and a buffer 401, wherein the input end of the low-pass filter LPF_1 receives the first direction voltage, the output end of the low-pass filter LPF_1 is connected to the positive phase input end of the buffer 401, the negative phase input end of the buffer 401 is connected to its output end, and the output end of the buffer 401 serves as the output end of the filter buffer processing unit 301.

[0096] It should also be noted that the ripple information can be eliminated by the low-pass filter in the filter buffer processing unit 301, and the average information of the current to be sampled is retained as the input current for subsequent ADC quantization. In addition, the buffer can be used to isolate the first direction voltage and the subsequent switch. When the subsequent switch is turned on, the first direction voltage is sent to the ADC for digital processing.

[0097] In practical applications, in addition to sending the first direction voltage processed by the filter buffer processing unit 301 to the ADC for quantization, the first direction voltage that has not been processed (ie, Figure 7 The signal V SNS FWD NF ) is sent to the subsequent peak overcurrent protection module. When the peak current of the first direction voltage is greater than the threshold, the peak overcurrent protection module is triggered to implement overcurrent protection of the first direction voltage. In addition, the first direction current (i.e. Figure 8 The signal V SNS FWD ) is sent to the subsequent corresponding processing module to perform corresponding processing using the average value information of the first direction current.

[0098] It should be noted that after the buffer is set for isolation, it is also possible to avoid the introduction of voltage ripple at the moment the switch is turned on, thereby avoiding false triggering of the peak overcurrent protection.

[0099] Based on the above, the first direction voltage obtained by the current sampling circuit of the chip provided by this embodiment, because a DC offset calibration amount is introduced in the first current adjustment unit to calibrate the DC offset error of the current sampling circuit, and a proportional vector calibration amount is introduced in the first IV conversion resistor to calibrate the proportional offset error of the current sampling circuit, the current sampling value obtained by the current sampling circuit can be made more accurate.

[0100] Optionally, in another embodiment provided in the present application, also refer to Figure 7 The current sampling circuit of the chip further includes: a second current sampling circuit 201, a second current adjustment unit 202 and a second IV conversion resistor R T2 .

[0101] The second current sampling circuit 201 is used to sample the second direction current flowing through the corresponding power transistor in the chip from the second direction. The first direction and the second direction are different directions.

[0102] In practical applications, the first direction may be a positive direction, and the second direction may be a negative direction; in other words, the positive direction may be Figure 7 In the direction from BUS node to PIMD node, the reverse direction can be Figure 7 The direction from the PIMD node to the BUS node.

[0103] In practical applications, Figure 7 As shown, the second current sampling circuit 201 includes: a second NMOS tube MN SNS2 , the second PMOS tube MP REG2 and a second operational amplifier HV_OP2.

[0104] Among them, the second NMOS tube MN SNS2 The second end of the second NMOS tube MN is connected to the middle power node of the chip (PIMD in the figure). SNS2 The first end of the second PMOS tube MP REG2 The first end of is connected to the inverting input end of the second operational amplifier HV_OP2.

[0105] The in-phase input terminal of the second operational amplifier HV_OP2 is connected to the power input terminal of the chip (BUS in the figure); the output terminal of the second operational amplifier HV_OP2 is connected to the second PMOS tube MP REG2 The control end of the second PMOS tube MP REG2 The second end of the second current sampling circuit 201 is used as the output end of the second current sampling circuit 201 to output the second direction current I SNS2_INI .

[0106] It should be noted that, in this embodiment, the first end represents the source, that is, the end with an arrow in the figure; the second end represents the drain, that is, Figure 7 The end without an arrow in the figure; the control end represents the gate.

[0107] The second current adjustment unit 202 is used to adjust the current in the second direction; the DC offset calibration amount in the second current adjustment unit 202 is the same as that in the first current adjustment unit 102 .

[0108] In practical applications, such as Figure 7 As shown, the structure of the second current adjustment unit 202 is the same as that of the first current adjustment unit 102, and is also a two-stage adjustable cascode current mirror. The proportional coefficient of the first stage adjustable cascode current mirror in the second current adjustment unit 202 can be 1:m1, and the proportional coefficient of the second stage adjustable cascode current mirror in the second current adjustment unit 202 can be 1:m2. Wherein, m=m1·m2.

[0109] It should be noted that by adjusting the ratio between the two-stage adjustable cascode current mirrors according to the DC offset calibration amount, the DC vector error caused by the second current adjustment unit 202 in the current sampling circuit can be eliminated. The two-stage adjustable cascode current mirrors in the second current adjustment unit 202 are generally controlled by controlling the current source ( Figure 7 The current source between the two) is turned on and off, which affects the fixed offset current of the current sampling circuit (V OS ) to perform trim calibration.

[0110] The second IV conversion resistor R T2The second IV conversion resistor R is used to convert the second direction current into the second direction voltage. Generally, if the parameters of the components in the first current adjustment unit 102 are the same as the parameters of the components in the second current adjustment unit 202, the second IV conversion resistor R T2 The ratio of the offset calibration amount to the first IV conversion resistor R T1 On the contrary, the proportional imbalance calibration amounts of the two may also be different, which can be determined according to the specific application environment and user needs, and all belong to the protection scope of this application.

[0111] In practical applications, such as Figure 7 As shown, the second IV conversion resistor R T2 One end of is connected to the output end of the second stage adjustment type common source and common gate current mirror in the second current adjustment unit 202, and the connection point is used as the output end to output the first direction voltage V SNS2 The second IV conversion resistor R T2 The other end is grounded.

[0112] It should be noted that the second direction voltage can be directly transmitted to the subsequent ADC for quantization to obtain the current detection value of the chip.

[0113] It should also be noted that after setting up bidirectional current detection in the current sampling circuit of the chip, Figure 7 As shown, a selector CSS may also be provided in the current sampling circuit to select output of the first direction voltage or the second direction voltage.

[0114] Combination Figure 7 The selector CSS can be set at the output end of the first direction voltage and the second direction voltage. In practical applications, the selector can be controlled to work in different modes through a digital control signal to output corresponding detection currents in different working modes. Figure 7 The FWD_MODE / RVS_MODE received by the selector CSS represents different digital control signal names, indicating that the SC Cahrger operates in different modes.

[0115] In the current sampling circuit of the chip provided in this embodiment, an additional current sampling loop in the opposite direction is provided. Compared with the traditional solution that can only sample single-sided current, the present application can not only sample bidirectional current, but also provide backflow protection for the chip, thus meeting the needs of high-performance power management applications.

[0116] Based on the calibration amount determination method and the current sampling circuit of the chip provided in the above embodiment, corresponding embodiments are provided for the above embodiment content. For ease of understanding, it is assumed that it is applied to SC (Switched-Capacitor, switched capacitor) Charger power management IC, combined with Figure 8 The present invention specifically includes the following implementation process:

[0117] In the SC Charger power management IC, the input current I POWER The USB node is transmitted to the BUS node through an OVP_FET, and then through the NMOS transistor MN to prevent backflow. POWER It is transmitted to the PMID node and finally converted by the SC 4x1 module, outputting the current I from the VOUT node. OUT transferred to the load.

[0118] In the typical working mode, both BUS and PMID nodes are high voltage, and the POWER transistor MN working in the linear region is clamped through the loop regulation of the negative feedback amplifier HV_OP. POWER and SNS tube MN SNS The VDS pressure drop at both ends is approximately equal, so that the current flowing through the SNS tube MN SNS The current I SNS With the flow through the POWER tube MN POWER The current I POWER In linear proportion, I SNS After passing through a two-stage Regulated-CM, it flows through the IV conversion resistor RT and is converted to V SNS Voltage, V SNS The voltage is buffered by the low-pass filter LPF and BUFFER to obtain V for quantization of the subsequent ADC. SNS_ADC The subscript suffixes 1 and 2 represent two opposite current sampling directions, ignoring the adjustment term and the V OS_BUFFER The obtained V SNS_ADC The expression is similar to formula (1):

[0119]

[0120] In formula (3), m=m1·m2 represents the current mirror proportional coefficient of the two-stage Regulated-CM, and the meanings of the other terms are consistent with those in formula (1).

[0121] and Figure 1 The difference between the traditional scheme and the detection V SNS_ADC At the same time, an additional detection signal V REF_ADC , its expression is as follows:

[0122] V REF_ADC =I REF_ADC ·R REF_ADC ——(4)

[0123] Use ADC to quantify V REF_ADC and V SNS_ADC The value of I is constructed by software using equations (3) and (4) POWER_CALThe function expression is:

[0124]

[0125] In formula (5), I REF_ADC0 , R REF_ADC0 , R T0 , K0 and m0 represent I REF_ADC , R REF_ADC , R T , K and m, and substitute equations (3) and (4) into equation (5) to obtain the complete functional expression of IPOWER_CAL:

[0126]

[0127] In formula (6), the same type of resistors are used, and the ratio mismatch is very small, and the 3-Sigma error is about 0.1%, so it can be approximately considered that Therefore, the I POWER_CAL Previous Item; Due to the use of Regulated-CM and the increase in the area of ​​the current mirror transistor, the mismatch of m is very small, and the 3-Sigma error is about 0.1%, so it can be approximately considered In order to ensure high accuracy of current sampling over the entire temperature range, it is necessary to ensure that I POWER_CAL The zero temperature coefficient reference current is obtained by adding a zero temperature coefficient reference voltage to the temperature compensated R NTC and R PTC The final expression containing the adjustment term is as follows:

[0128]

[0129] In formula (7), Represents the proportional imbalance calibration amount introduced by adjusting RT; I OS_TRIM It represents the DC offset calibration amount introduced by the current source DAC at the output node of the first stage Regulated-CM.

[0130] Therefore, I is adjusted by the two-point method. POWER The process is divided into three steps. First, adjust V REF0P5 Make Then use I OS_TRIM Adjustment Item; finally use RT to adjust Item; after adjustment, I POWER_CAL ≈I POWER , the current sampling accuracy is guaranteed.

[0131] Based on the above, the I in the traditional current detection scheme can be eliminated through the constructor.POWER_CAL In Then only through R T Adjustment Make I POWER_CAL The accuracy is improved, the adjustment range is reduced, and the R T There is no requirement for the temperature coefficient, and the design of the adjustment network is simpler. In addition, forward and reverse current sampling can be realized simultaneously without mode selection, providing real-time backflow protection.

[0132] It should be noted that the above example is only a specific implementation method of the present application. In practical applications, any direct or indirect detection of R T Arrow matching The methods can all be used to implement function construction and can achieve similar purposes, but the adjustment time and cost are different, and all belong to the protection scope of this application.

[0133] It should also be noted that in actual applications, bidirectional current sampling of the current sampling circuit of the chip can also be achieved through mode selection, but real-time sampling and backflow protection cannot be achieved.

[0134] In addition, by changing the current into the IV conversion resistor R T The current I SNS size, enabling The calibration is performed by synchronously changing the IV conversion resistor R T The resistance value can achieve proportional changes, eliminating Finally, the sampling current obtained by the sampling circuit is Fig. 9 The straight line with a slope of 1 passing through the zero point is also the Target line. Fig. 9 The straight line Real in represents the real sampling circuit.

[0135] It should be noted that Figure 8 The OVP_FET (Over-Voltage-Protection Field Effect Transistor) in the figure represents a back-to-back NMOS tube outside the SC Charger chip, which is used to prevent the BUS node voltage from overvoltage. Figure 8 NM START It is a slow-start tube used in the startup phase. Since the SC Charger chip used in the present invention includes 6 working modes, including 3 forward charging modes and 3 reverse charging modes, when working in the reverse charging mode, V PMID High pressure appears first. If you open the large MN directly, POWER , then due to V PMID -V BUS If the voltage difference is too large, a large transient current will be generated, which will affect V BUS Port and MNPOWER The MN tube causes great electrical stress damage, resulting in chip reliability risk. Therefore, in the early stage of reverse mode startup of the Charger chip, a small size MN START Slowly V BUS The node is charged and waits until V PMID -V BUS When the pressure difference is less than a certain range, switch to MN POWER Turn on to improve chip reliability. Figure 8 The Charger Pump in the MN POWER The gate voltage is raised to V BUS +5V, making MN POWER Works in the linear resistance region with low on-resistance. Figure 8 The SC4×1 in the figure indicates the name of the power conversion module, which is similar to a transformer and can achieve a 4:1 conversion of input and output voltages.

[0136] Based on the above, the current detection establishment of the chip provided by the present invention can realize full-set high-precision current detection on the chip, and its detection accuracy is approximately independent of temperature and IV conversion resistor process manufacturing deviation; and it can effectively calibrate the DC offset error and proportional offset error introduced in the current link, while ensuring the accuracy of the current detection absolute value and the protection circuit threshold point.

[0137] It should be noted that the SNS tube mentioned in this application represents a current detection transistor, and the POWER tube represents a power transistor.

[0138] The features recorded in the various embodiments in this specification can be replaced or combined with each other, and the same and similar parts between the various embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative work.

[0139] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0140] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0141] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

Claims

1. A method for determining a calibration amount, characterized in that: A current sampling circuit applied to a chip, the method comprising: Respectively obtaining a sampling voltage of the current sampling circuit and an auxiliary detection voltage of the auxiliary detection circuit; the auxiliary detection circuit is constructed based on the current sampling circuit and is used to eliminate the proportional imbalance error of the IV conversion resistor in the current sampling circuit; Based on the sampling voltage and the auxiliary detection voltage constructor, a proportional offset calibration amount and a DC offset calibration amount of the current sampling circuit are determined; wherein the proportional offset calibration amount is used to calibrate the proportional offset error of the IV conversion resistor, and the DC offset calibration amount is used to calibrate the DC offset error of the current sampling circuit; Based on the sampling voltage and the auxiliary detection voltage constructor, determining a proportional offset calibration amount and a DC offset calibration amount of the current sampling circuit, including: Based on the sampling voltage and the auxiliary detection voltage, respectively determining a calculation expression of the sampling voltage and an expression of the auxiliary detection voltage; Based on the calculation expression of the sampling voltage and the calculation expression of the auxiliary detection voltage, construct a function expression of the current flowing through the power transistor in the chip; The calculation expression of the sampling voltage, the calculation expression of the auxiliary detection voltage and the current function expression are processed to obtain the proportional offset calibration amount and the DC offset calibration amount of the detection circuit.

2. The calibration amount determination method according to claim 1, characterized in that: Respectively obtaining a sampling voltage of the current sampling circuit and an auxiliary detection voltage of the auxiliary detection circuit, comprising: Collecting the voltage of the corresponding output port in the current sampling circuit to obtain the sampled voltage; The voltage output by the auxiliary detection circuit is collected to obtain the auxiliary detection voltage.

3. The calibration amount determination method according to claim 1, characterized in that: The calculation expression of the sampling voltage, the calculation expression of the auxiliary detection voltage and the current function expression are processed to obtain the proportional offset calibration amount and the DC offset calibration amount of the detection circuit, including: Substituting the calculation expression of the sampling voltage and the calculation expression of the auxiliary detection voltage into the current function expression respectively to obtain a complete function expression; The complete function expression is trimmed to obtain a trimmed complete function expression, and a proportional offset calibration amount and a DC offset calibration amount of the current sampling circuit are determined based on the trimmed complete function expression.

4. The calibration amount determination method according to claim 3, characterized in that: The calculation expression of the sampling voltage is: Among them, the V SNS_ADC represents the sampling voltage, m represents the proportional coefficient of the current unit in the current sampling circuit, I POWER represents the actual current flowing through the power transistor, K represents the actual ratio of the on-resistance of the current detection transistor in the current sampling circuit to that of the power transistor, V OS Represents the equivalent input offset voltage across the clamped op amp, R SNS represents the DC on-resistance of the current sensing transistor, R T Indicates the actual resistance value of the IV conversion resistor; The auxiliary detection voltage expression is: V REF_ADC =I REF_ADC ·R REF_ADC ; Among them, V REF_ADC represents the auxiliary detection voltage, I REF_ADC Represents the zero temperature coefficient reference current, R REF_ADC Indicates the resistance value of a resistor of the same type as the IV conversion resistor; The current function expression is: Among them, I POWER_ADL represents the detection current flowing through the power transistor, I REF_ADC0 I REF_ADC The design value, R REF_ADC0 Represents R REF_ADC The design value, R T0 Represents R T The design value of K0 is the design value of K, m o represents the design value of m.

5. The calibration amount determination method according to claim 4, characterized in that: The complete function expression is: The complete function expression of the adjustment is: in, represents the proportional imbalance calibration amount, I OS_TRIM represents the DC offset calibration amount.

6. A current sampling circuit of a chip, characterized in that: include: A first current sampling circuit, a first current adjustment unit and a first IV conversion resistor; Wherein, the first current sampling circuit is used to sample a first direction current flowing through a corresponding power transistor in the chip in a first direction; The first current adjustment unit is used to adjust the first direction current; the DC offset calibration amount in the first current adjustment unit is determined by the calibration amount determination method according to any one of claims 1 to 5, using the first direction voltage as the sampling voltage; The first IV conversion resistor is used to convert the first direction current into a first direction voltage; The proportional imbalance calibration amount in the first IV conversion resistor is determined by the calibration amount determination method according to any one of claims 1 to 5, using the first direction voltage as the sampling voltage.

7. The current sampling circuit of the chip according to claim 6, characterized in that: Also includes: A second current sampling circuit, a second current adjustment unit and a second IV conversion resistor; Wherein, the second current sampling circuit is used to sample a second direction current flowing through the corresponding power transistor in the chip from a second direction; the first direction and the second direction are different directions; The second current adjustment unit is used to adjust the second direction current; the DC offset calibration amount in the second current adjustment unit is the same as that in the first current adjustment unit; The second IV conversion resistor is used to convert the second direction current into a second direction voltage; and the proportional imbalance calibration amount in the second IV conversion resistor is the same as that in the first IV conversion resistor.

8. The current sampling circuit of the chip according to claim 7, characterized in that: Also includes: Selector; wherein the selector is used to select to output the first direction voltage or the second direction voltage.

9. The current sampling circuit of the chip according to claim 7, characterized in that: The first current adjustment unit and the second current adjustment unit are both two-stage adjustment type cascode current mirrors.

10. The current sampling circuit of the chip according to claim 6, characterized in that: Also includes: The filtering and buffering processing unit is used to perform filtering and buffering processing on the first direction voltage.

11. The current sampling circuit of the chip according to claim 6, characterized in that: The first current sampling circuit includes: a first NMOS tube, a first PMOS tube and a first operational amplifier; The second end of the first NMOS tube is connected to the power input end of the chip, and the first end of the first NMOS tube is connected to the first end of the first PMOS tube and the inverting input end of the first operational amplifier respectively; The in-phase input terminal of the first operational amplifier is connected to the middle power node of the chip; the output terminal of the first operational amplifier is connected to the control terminal of the first PMOS tube, and the second terminal of the first PMOS tube serves as the output terminal of the first current sampling circuit to output the first direction current.

12. The current sampling circuit of the chip according to claim 7, characterized in that: The second current sampling circuit includes: a second NMOS tube, a second PMOS tube and a second operational amplifier; The second end of the second NMOS tube is connected to the middle power node of the chip, and the first end of the second NMOS tube is connected to the first end of the second PMOS tube and the inverting input end of the second operational amplifier respectively; The in-phase input terminal of the second operational amplifier is connected to the power input terminal of the chip; the output terminal of the second operational amplifier is connected to the control terminal of the second PMOS tube, and the second terminal of the second PMOS tube serves as the output terminal of the second current sampling circuit to output the second direction current.

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