Oscillator of switching converter and switching converter

Abstract

The present invention discloses an oscillator and a switching converter of a switching converter. The oscillator includes a charging current generating circuit and a clock signal generating circuit, and the clock signal generating circuit generates a clock signal according to the charging current provided by the charging current generating circuit. The charging current generating circuit includes an adjusting resistor and a current limiting module, and the current limiting module is used to limit the current value of the charging current to a preset current when the adjusting resistor is short-circuited or open-circuited, thereby avoiding a drastic change in the switching frequency of the circuit when the external adjusting resistor is short-circuited or open-circuited, and improving the stability of the system.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and more particularly to an oscillator and a switching converter of a switching converter. Background Art

[0002] With the popularity of portable electronic products, switching power supplies are becoming more and more important. The power supplies used in modern electronic devices are roughly divided into linear regulated power supplies and switching regulated power supplies. The adjustment tube of the linear regulated power supply works in the amplification area, which has the advantages of not introducing additional interference, good reliability and low cost, but it also has the disadvantages of large size and low conversion efficiency. Compared with the linear regulated power supply, the switching regulated power supply has the characteristics of boosting and bucking and high power supply efficiency. However, when the switching regulated power supply adjusts the voltage and current, it will generate electromagnetic interference noise (EMI). This electrical noise can be transmitted to the AC power line, which will not only affect the operation of other electronic devices near the power supply through conduction, but also radiate or leak from the power line, affecting devices not connected to the power line. These interferences will increase significantly with the increase of switching frequency and output power, posing a potential threat to the normal operation of electronic equipment.

[0003] In order to suppress the electromagnetic interference of the switching converter and make it meet the requirements of relevant electromagnetic compatibility standards, the switching converter in the prior art uses frequency jitter technology to increase the harmonic order so that the frequency can be dispersed, that is, by changing the switching frequency periodically, the noise harmonic frequency is dispersed, the noise energy is dispersed and reduced, and the amplitude margin is guaranteed over the entire frequency band, thereby meeting the electromagnetic compatibility requirements.

[0004] Figure 1 FIG. 1 shows a schematic diagram of the structure of a switching converter in the prior art. Figure 1 As shown, the switching converter 100 includes a control circuit and a power stage circuit integrated in the same integrated circuit chip. The control circuit includes an error amplifier EA, a logic drive circuit 110 , an oscillator 120 and a PWM comparator 130 .

[0005] The error amplifier EA is used to obtain an error signal Verr according to the feedback voltage Vfb of the output voltage Vout and the reference voltage Vref. The PWM comparator 130 compares the error signal Verr with the slope voltage Vslope, and generates a pulse width modulation signal PWM according to the comparison result. The logic drive circuit 110 generates a switch drive signal according to the pulse width modulation signal PWM and the clock signal CLK provided by the oscillator 120 to control the on and off of the power switch tubes MD1 and MD2.

[0006] The switching converters in the prior art usually use analog methods to adjust the frequency, for example, by adjusting the size of the charging current of the oscillator through an external adjustment resistor, so as to obtain a clock signal CLK with a frequency variation. The disadvantage of this method is that the range of frequency variation is particularly large in actual application. For example, when the external adjustment resistor is short-circuited or open-circuited, the switching frequency will become particularly fast or slow, reducing the stability of the system and even causing damage to the chip. Summary of the invention

[0007] In view of this, an object of the present invention is to provide an oscillator and a switching converter of a switching converter, which avoid drastic changes in the circuit switching frequency when an external regulating resistor is short-circuited or open-circuited, thereby improving the stability of the system.

[0008] According to one aspect of the present invention, an oscillator of a switching converter is provided, comprising: a charging current generating circuit for generating a charging current; a clock signal generating circuit for generating a ramp voltage according to the charging current, and comparing the ramp voltage with a first reference voltage, and generating a clock signal according to the comparison result, wherein the charging current generating circuit comprises an adjusting resistor and a current limiting module, and the current limiting module is used to limit the current value of the charging current to a preset current when the adjusting resistor is short-circuited or open-circuited.

[0009] Optionally, the charging current generating circuit also includes: a first transistor and a second transistor connected in series between the power supply voltage and the adjustment resistor; a fourth transistor connected between the power supply voltage and the clock signal generating circuit, the fourth transistor and the first transistor forming a current mirror, and the second end of the fourth transistor is used to provide the charging current; and an operational amplifier, whose non-inverting input terminal is used to receive a second reference voltage, whose inverting input terminal is connected to a first node with the first end of the adjustment resistor, and whose output terminal is connected to the control end of the second transistor, wherein the operational amplifier is used to provide a node feedback adjustment signal to the second transistor according to the node voltage of the first node and the second reference voltage, so as to adjust the current value of the charging current.

[0010] Optionally, the current limiting module is used to adjust the node feedback adjustment signal when the adjustment resistor is short-circuited or open-circuited, so as to limit the current value of the charging current to the preset current.

[0011] Optionally, the current limiting module includes: a first current source, a first end of which is connected to the power supply voltage, and a second end of which is connected to the first node; and a second current source, a first end of which is connected to the control end of the first transistor, and a second end of which is connected to ground; a third transistor and a sixth transistor connected between the power supply voltage and ground, the third transistor and the first transistor forming a current mirror; and a fifth transistor connected between the output end of the operational amplifier and ground, the fifth transistor and the sixth transistor forming a current mirror.

[0012] Optionally, the charging current generating circuit further includes a third current source connected in parallel between the first end and the second end of the sixth transistor.

[0013] Optionally, the output currents of the first current source and the second current source are equal.

[0014] Optionally, the clock signal generating circuit includes: a charging capacitor connected between the output end of the charging current generating circuit and ground; a controllable switch, a first end of which is connected to the first end of the charging capacitor and a second end is grounded; and a comparator, a non-inverting input end is connected to the connection node between the controllable switch and the charging capacitor to receive the ramp voltage, an inverting input end is used to receive the first reference voltage, and an output end is used to output the clock signal, wherein the conduction and shutdown of the controllable switch are controlled by the clock signal.

[0015] Optionally, the first transistor, the third transistor and the fourth transistor are respectively P-type metal oxide semiconductor field effect transistors, and the second transistor, the fifth transistor and the sixth transistor are respectively N-type metal oxide semiconductor field effect transistors.

[0016] According to another aspect of the present invention, a switching converter is provided, comprising: a power stage circuit, comprising a power switch tube, for converting an input voltage into an output voltage; an error amplifier, for generating an error signal based on a feedback voltage of the output voltage and a third reference voltage; a PWM comparator, for comparing the error signal with a ramp voltage to generate a pulse width modulation signal; a logic drive circuit, for generating a switch drive signal based on the pulse width modulation signal and a clock signal to control the on and off of the power switch tube; and the above-mentioned oscillator, for generating the clock signal.

[0017] Optionally, the topology of the power stage circuit is selected from Buck topology, Boost topology or Buck-Boost topology.

[0018] The oscillator of the embodiment of the present invention includes a charging current generating circuit and a clock signal generating circuit. The charging current generating circuit includes an adjusting resistor and a current limiting module, and the current limiting module is used to limit the current value of the charging current to a preset current when the adjusting resistor is short-circuited or open-circuited, thereby avoiding a drastic change in the switching frequency of the circuit when the external adjusting resistor is short-circuited or open-circuited, and improving the stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0020] Figure 1 A schematic diagram of the structure of a switching converter in the prior art is shown;

[0021] Figure 2 A circuit diagram of an oscillator of a switching converter according to a first embodiment of the present invention is shown;

[0022] Figure 3 A schematic structural diagram of a switching converter according to a second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0023] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0024] Many specific details of the present invention are described below, such as component structures, materials, dimensions, processing techniques and technologies, in order to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0025] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits and / or elements that can store instructions executed by programmable circuits. When an element or circuit is said to be "connected to" or "coupled to" another element, or an element / circuit is said to be "connected to" or "coupled between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element between the two, and the connection or coupling between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0026] In the present application, a switch tube is a transistor that operates in a switch mode to provide a current path, including one selected from a bipolar transistor or a field effect transistor. The first end and the second end of the switch tube are respectively a high potential end and a low potential end on the current path, and the control end is used to receive a drive signal to control the on and off of the switch tube.

[0027] Figure 2 FIG. 2 is a schematic circuit diagram of an oscillator of a switching converter according to a first embodiment of the present invention. Figure 2 As shown, the oscillator 200 includes a charging current generating circuit 210 and a clock signal generating circuit 220 .

[0028] The charging current generating circuit 210 includes transistors Mp1 to Mp3, transistors Mn1 to Mn3, current sources 211 to 213, an operational amplifier OP1, and an adjusting resistor Rset. The transistor Mp1, the transistor Mn1, and the adjusting resistor Rset are connected in series between the power supply voltage VDD and the ground. The transistor Mp3 and the transistor Mp1 form a current mirror, the first end of the transistor Mp3 is connected to the power supply voltage VDD, and the second end is used to provide the charging current Ich. The first end of the current source 211 is connected to the power supply voltage VDD, and the second end is connected to the node A. The first end of the current source 212 is connected to the control end of the transistor Mp1, and the second end is grounded. The non-inverting input end of the operational amplifier OP1 is used to receive the second reference voltage Vref2, the inverting input end is connected to the first end of the adjusting resistor Rset at the node A, and the output end is connected to the control end of the transistor Mn1. The operational amplifier OP1 is used to provide a feedback adjustment signal Vadj to the transistor Mn1 according to the voltage VA of the node A and the second reference voltage Vref2. The feedback adjustment signal Vadj is used to control the current flowing through the transistor Mn1 according to the resistance value of the adjustment resistor Rset, and then adjust the current value of the charging current Ich to achieve the purpose of changing the frequency of the clock signal CLK.

[0029] The clock signal generating circuit 220 includes a charging capacitor C0, a controllable switch K1, and a comparator comp1. The charging capacitor C0 is connected between the output terminal of the charging current generating circuit 210 and the ground, the first terminal of the controllable switch K1 is connected to the first terminal of the charging capacitor C0, and the second terminal is grounded, for providing a discharge path from the first terminal of the charging capacitor C0 to the ground. The comparator comp1 has a non-inverting input terminal connected to a connection node between the controllable switch K1 and the charging capacitor C0 to receive a slope voltage Vslope, an inverting input terminal receiving a first reference voltage Vref, and an output terminal for outputting a clock signal CLK.

[0030] In the initial state, the charge on the charging capacitor C0 is zero, the slope voltage Vslope is less than the first reference voltage Vref1, the output of the comparator comp1 is low, the controllable switch K1 is turned off, and the charging current Ich charges the charging capacitor C0. When the slope voltage Vslope is greater than the first reference voltage Vref1, the output of the comparator comp1 flips, and the controllable switch K1 is turned on at this time, and the charging capacitor C0 begins to discharge to the ground. Because the discharge current of the charging capacitor C0 is much greater than the charging current Ich, the slope voltage Vslope begins to decrease. When the slope voltage Vslope drops to slightly less than the first reference voltage Vref1, the output of the comparator comp1 flips again, the controllable switch K1 is turned off, and the charging current Ich starts to charge the charging capacitor C0 again, and the next oscillation cycle begins.

[0031] The transistor Mp2, transistors Mn2 and Mn3 and current sources 211-213 in the charging current generating circuit 210 constitute a current limiting module, which is used to limit the current value of the charging current Ich to a preset current when the regulating resistor Rset is short-circuited or open-circuited. The first end of the transistor Mn2 is connected to the output end of the operational amplifier OP1, and the second end is grounded. The transistor Mp2 and the transistor Mn3 are connected between the power supply voltage VDD and the ground in sequence. The transistor Mp2 and the transistor Mp1 constitute a current mirror, and the transistor Mn3 and the transistor Mn2 constitute a current mirror. The current source 211 is connected between the power supply voltage VDD and the second end of the transistor Mn1, the current source 212 is connected between the control end of the transistor Mp1 and the ground, and the current source 213 is connected in parallel between the first end and the second end of the transistor Mn3.

[0032] In this embodiment, transistors Mp1 to Mp3 are implemented, for example, by P-type MOSFET (P-Metal-Oxide-Semiconductor Field-Effect Transistor), and the first end, the second end and the control end of the P-type MOSFET are the source, the drain and the gate, respectively. Transistors Mn1 to Mn3 are implemented, for example, by N-type MOSFET (N-Metal-Oxide-Semiconductor Field-Effect Transistor), and the first end, the second end and the control end of the N-type MOSFET are the drain, the source and the gate, respectively.

[0033] Refer to the following Figure 2 The working principle of the oscillator of the first embodiment of the present invention is described in detail. Figure 2 As shown, when the oscillator 200 operates normally, the charging current Ich generated by the charging current generating circuit 210 is:

[0034] Ich=I Mp1 =I Mn1 +I2

[0035] Among them, I Mp1 represents the current flowing through transistor Mp1, I Mn1 I represents the current flowing through the transistor Mn1 , and I2 represents the current of the current source 212 .

[0036] Furthermore, the current I flowing through transistor Mn1 Mn1 for:

[0037] I Mn1 =Vref2 / Rset-I1

[0038] Wherein, I1 represents the current of the current source 211. Combining the above formula, the charging current Ich generated by the charging current generating circuit 210 can be obtained as follows:

[0039] Ich=Vref2 / Rset+I2-I1

[0040] If the output currents of the current source 211 and the current source 212 are equal, the charging current Ich can be obtained as:

[0041] Ich=Vref2 / Rset

[0042] When the oscillator 200 works abnormally, for example, when the adjustment resistor Rset is short-circuited (Rset=0), the transistor Mn2 in the current limiting circuit 240 is turned on, and the transistor Mn2 pulls down the node to feedback the adjustment signal Vadj, limiting the maximum value of the charging current Ich to:

[0043] Ich,max=I3

[0044] The current I3 represents the output current of the current source 213 .

[0045] When the regulating resistor Rset is disconnected (Rset=∞), the transistor Mn1 is turned off, and the current source 212 limits the minimum value of the charging current Ich to:

[0046] Ich,min=I2

[0047] In summary, the oscillator 200 of the embodiment of the present invention limits the maximum and minimum values ​​of the charging current Ich, thereby limiting the frequency variation range of the clock signal, avoiding drastic changes in the circuit switching frequency when the external adjustment resistor is short-circuited or open-circuited, and is beneficial to improving the stability of the system.

[0048] Figure 3 FIG. 2 shows a schematic diagram of the structure of a switching converter according to a second embodiment of the present invention. Figure 3As shown, the switching converter 300 includes a control circuit and a power stage circuit. The control circuit includes an error amplifier EA, a logic drive circuit 310 , a PWM comparator 320 and an oscillator 200 .

[0049] The error amplifier EA is used to obtain the error signal Verr according to the feedback voltage Vfb of the output voltage Vout and the reference voltage Vref. The PWM comparator compares the slope voltage Vslope with the error signal Verr, and generates a pulse width modulation signal PWM according to the comparison result. The logic drive circuit 310 generates a switch drive signal according to the pulse width modulation signal PWM and the clock signal CLK provided by the oscillator 200 to control the on and off of the power switch tubes MD1 and MD2. It should be understood by those skilled in the art that the logic control circuit 310 can be implemented through different architectures. At the same time, the control principle of the synchronous rectifier buck switching converter 300 should be well known to those skilled in the art.

[0050] The oscillator 200 is implemented, for example, by the oscillator of the first embodiment, which limits the maximum and minimum values ​​of the charging current Ich, thereby limiting the frequency variation range of the clock signal, avoiding drastic changes in the circuit switching frequency when the external adjustment resistor is short-circuited or open-circuited, and is beneficial to improving the stability of the system.

[0051] The power switch tubes MD1 and MD2 in the above embodiments can be various transistors, such as NPN Darlington transistors, NPN bipolar transistors, PNP bipolar transistors, N-type MOSFETs and P-type MOSFETs, etc. The control circuit is packaged into a chip IC, for example. In some embodiments, the power switch tubes MD1 and MD2 in the power stage circuit are also packaged in a chip IC.

[0052] In summary, the embodiments of the present invention provide an oscillator and a switching converter of a switching converter, wherein the oscillator includes a charging current generating circuit and a clock signal generating circuit. The charging current generating circuit includes an adjusting resistor and a current limiting module, and the current limiting module is used to limit the current value of the charging current to a preset current when the adjusting resistor is short-circuited or open-circuited, thereby avoiding a drastic change in the switching frequency of the circuit when the external adjusting resistor is short-circuited or open-circuited, and improving the stability of the system.

[0053] In the above-mentioned embodiment, although the combination Figure 3 A switching converter of a buck topology is described, however, it can be understood that the oscillator 200 of the embodiment of the present invention can also be used in switching converters of other topologies, including but not limited to Buck topology, Boost topology or Buck-Boost topology.

[0054] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0055] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An oscillator for a switching converter, comprising: A charging current generating circuit, used for generating a charging current; The clock signal generating circuit generates a ramp voltage according to the charging current, compares the ramp voltage with a first reference voltage, and generates a clock signal according to the comparison result. The charging current generating circuit includes an adjusting resistor and a current limiting module, wherein the current limiting module is used to limit the current value of the charging current to a preset current when the adjusting resistor is short-circuited or open-circuited. The charging current generating circuit further includes a first transistor and a second transistor connected in series between the power supply voltage and the regulating resistor; a fourth transistor connected between the power supply voltage and the clock signal generating circuit, the fourth transistor and the first transistor forming a current mirror, the second end of the fourth transistor being used to provide the charging current; and an operational amplifier, wherein the non-inverting input terminal is used to receive the second reference voltage, the inverting input terminal is connected to the first end of the regulating resistor at a first node, and the output terminal is connected to the control end of the second transistor, The operational amplifier is used to provide a node feedback regulation signal to the second transistor according to the node voltage of the first node and the second reference voltage to adjust the current value of the charging current, and the current limiting module is used to adjust the node feedback regulation signal when the regulating resistor is short-circuited or open-circuited to limit the current value of the charging current to the preset current. Wherein, the current limiting module includes: a first current source, a first terminal of which is connected to the power supply voltage, and a second terminal of which is connected to the first node; and a second current source, a first end of which is connected to the control end of the first transistor, and a second end of which is grounded; a third transistor and a sixth transistor connected between the power supply voltage and ground, the third transistor and the first transistor forming a current mirror; and A fifth transistor is connected between the output terminal of the operational amplifier and the ground, and the fifth transistor and the sixth transistor form a current mirror.

2. The oscillator according to claim 1, wherein The charging current generating circuit further includes a third current source connected in parallel between the first terminal and the second terminal of the sixth transistor.

3. The oscillator according to claim 1, wherein The output currents of the first current source and the second current source are equal.

4. The oscillator according to claim 1, wherein the clock signal generating circuit comprises: a charging capacitor connected between the output terminal of the charging current generating circuit and ground; A controllable switch, a first end of which is connected to the first end of the charging capacitor and a second end of which is grounded; as well as a comparator, wherein a non-inverting input terminal is connected to a connection node between the controllable switch and the charging capacitor to receive the ramp voltage, an inverting input terminal is used to receive the first reference voltage, and an output terminal is used to output the clock signal, The on and off of the controllable switch is controlled by the clock signal.

5. The oscillator according to claim 1, wherein The first transistor, the third transistor and the fourth transistor are P-type metal oxide semiconductor field effect transistors respectively. The second transistor, the fifth transistor and the sixth transistor are respectively N-type metal oxide semiconductor field effect transistors.

6. A switching converter, comprising: A power stage circuit, including a power switch tube, for converting an input voltage into an output voltage; an error amplifier, configured to generate an error signal according to a feedback voltage of the output voltage and a third reference voltage; A PWM comparator, used for comparing the error signal with a ramp voltage to generate a pulse width modulation signal; A logic drive circuit, used to generate a switch drive signal according to the pulse width modulation signal and a clock signal, and control the on and off of the power switch tube; as well as The oscillator according to any one of claims 1 to 5, used to generate the clock signal.

7. The switching converter according to claim 6, wherein: The topology of the power stage circuit is selected from Buck topology, Boost topology or Buck-Boost topology.

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