A double-fault error calculation method for binary all-optical comparator

Abstract

The present invention proposes a method for calculating dual-fault errors in a binary all-optical comparator. This method primarily relates to the field of optical on-chip networks, and specifically to analyzing and calculating errors caused by two MRR faults in a logic calculation circuit based on microring resonators (MRRs). The method includes obtaining the correct output results of a fault-free model device and the erroneous output results of a dual-fault model device, comparing the relationship between each correct output result and each erroneous output result, and calculating the bit flip error, maximum bit flip error, and error probability of the entire logic calculation circuit between the correct and erroneous output results. The embodiment of the present invention is used to calculate errors caused by dual faults during the actual production and use of a logic calculation circuit composed of n MRRs. Specifically, a dual-fault simulation device for a binary all-optical comparator composed of three MRRs is used as an example for implementation.

Description

Technical Field

[0001] The present invention relates to the field of on-chip optical networks, and in particular to the field of error analysis and calculation caused by double faults in MRR-based logic calculation circuits. Background Art

[0002] As the number of processors integrated on a single chip increases, and the operating frequency of chip circuits rapidly increases to several GHz or even higher, traditional electrical interconnect networks will no longer be able to efficiently transmit signals. Electrically interconnected networks on a chip (NOCs) have encountered bottlenecks in power consumption, performance, bandwidth, and latency, failing to meet the performance requirements of interconnected networks. Therefore, a new interconnection method is needed, and thus optical interconnect technology has emerged. Compared with electrical interconnects, optical interconnects offer many advantages that dielectrics cannot match. As a new interconnection method, they offer unparalleled advantages in NOCs, such as low loss, high throughput, and low latency. Lightwaves offer advantages such as high transmission bandwidth, low inter-signal delay, low optical loss, and interference resistance when used for high-speed transmission and processing. Based on these advantages, on-chip optical networks have emerged. Microring resonators (MRRs) are one of the key components of on-chip optical networks. However, they are sensitive to process drift and temperature, making them prone to failure. Therefore, researchers have built fault simulation devices to simulate MRR failures in order to improve the reliability of integrated optics.

[0003] However, the output results caused by microring resonator failures are not necessarily incorrect. Therefore, it is necessary to study, analyze, and calculate the errors caused by MRR double failures. This involves performing double-fault simulation analysis on a certain logic calculation circuit composed of MRRs to determine which errors are acceptable. Therefore, this patent, based on the establishment of an all-optical binary comparator using optical devices, achieves the calculation and analysis of the fault errors of the all-optical binary comparator under actual operating conditions, which will provide positive guidance for the future research and development of optical computing devices with similar functions. Summary of the Invention

[0004] The present invention studies, analyzes and calculates errors caused by MRR double faults, and provides a double fault error calculation method for a binary all-optical comparator.

[0005] The present invention adopts the following technical solutions to achieve the above-mentioned purpose:

[0006] A double-fault error calculation method for a binary all-optical comparator includes a logic calculation circuit composed of n MRRs, wherein the circuit includes N input combinations, each combination can generate an m-bit output result. The logic calculation circuit composed of the n MRRs can be divided into a fault-free analog equivalent circuit and a double-fault analog equivalent circuit. A correct output result can be obtained according to the fault-free analog equivalent circuit, and an erroneous output result can be obtained according to the double-fault analog equivalent circuit. Based on the correct output result and the erroneous output result, the relationship between each correct output result and each erroneous output result is compared, and the bit flip error (BFE) between the two, the maximum bit flip error (MAXBFE), and the error probability (EP) in the N input combinations are calculated.

[0007] Compare the relationship between each correct output result and each incorrect output result in each input combination, and calculate the bit flip error (BFE) between the correct output result and the incorrect output result. The specific expression of BFE is shown in formula (1):

[0008]

[0009] The i represents the i-th input combination, the i is included in N, the For XOR, the Represents the j-th logical value of the error output under the i-th input combination, Represents the j-th logical value of the correct output under the i-th input combination.

[0010] The maximum value of all the BFEs generated by the N input combinations is calculated as the maximum bit flip error (MAXBFE), that is, the worst result caused by double faults in the N input combinations. The specific expression of MAXBFE is shown in formula (2):

[0011]

[0012] The probability of an error occurring due to a double fault in the N input combinations is calculated, that is, the error probability (EP). The specific expression of the EP is shown in formula (3):

[0013] BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention will be further described below with reference to the accompanying drawings and examples.

[0015] Figure 1 The figure is a flow chart of a double-fault error calculation method for a binary all-optical comparator.

[0016] Figure 2 The figure is a structural diagram of a fault simulation device for a binary all-optical comparator.

[0017] Figure 3 Schematic diagram of the structure of the parallel MRR switch. DETAILED DESCRIPTION

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0019] Embodiment 1: The embodiment of the present invention provides a method for calculating double fault errors of a binary all-optical comparator. Figure 1 Shown include:

[0020] S101 . Based on a logic calculation circuit composed of n MRRs, enumerate N input combinations of the circuit.

[0021] S102 , calculating respectively the correct output result of the fault-free analog equivalent circuit and the erroneous output result of the double-fault analog equivalent circuit according to N input combinations, and each combination can generate an m-bit output result.

[0022] S103: Compare the correct output result of each bit in each input combination with the incorrect output result of each bit.

[0023] and calculating a bit flip error (BFE) between the correct output result and the erroneous output result.

[0024] Furthermore, the specific expression of the BFE is shown in formula (1):

[0025]

[0026] The i represents the i-th input combination, the i is included in N, the For XOR, the Represents the j-th logical value of the error output under the i-th input combination, Represents the j-th logical value of the correct output under the i-th input combination.

[0027] S104: Calculate the maximum value of all the BFEs generated by the N input combinations as the maximum bit flip error (MAXBFE).

[0028] Furthermore, the worst result caused by double faults in the N input combinations is specifically expressed as shown in formula (2):

[0029]

[0030] S105 : Calculate the probability of errors occurring in the N input combinations due to double faults, that is, the error probability (EP).

[0031] Furthermore, the specific expression of the EP is shown in formula (3):

[0032]

[0033] For example, the patent of a binary all-optical comparator fault simulation device (CN201821995423.1) disclosed a utility model of a binary all-optical comparator fault simulation device (CN201821995423.1) in the specification of the patent is “ Figure 1 "For example, Figure 2 The device is now defined as a double fault simulation, and the specific operation steps of the double fault error calculation method of the binary all-optical comparator of the present invention in practical application are further supplemented:

[0034] Here we first show the working principle of the microring resonator (MRR) in the fault-free and faulty conditions:

[0035] A modulation voltage signal X is added to the microring resonator. When the modulation voltage signal X is at a low level, the microring resonator resonates. Conversely, when the modulation voltage signal X is at a high level, the microring resonator does not resonate.

[0036] Specifically, if Figure 3 As shown in the figure, the optical signal is input from the input end of the MRR's input optical waveguide. When the modulation voltage signal X is at a low level "0", the MRR resonates, and the optical signal is output from the Drop end of the MRR's download optical waveguide, with a logic state of "1", while the Through end of the MRR's straight optical waveguide has no optical signal output, and the logic state is "0". When the modulation voltage signal X is at a high level "1", the MRR does not resonate, and the optical signal is output from the Through end of the MRR's straight optical waveguide, with a logic state of "1", while the Drop end of the MRR's download optical waveguide has no optical signal output, and the logic state is "0".

[0037] Specifically, if Figure 3As shown, assume that the MRR has a stuck-at-0 fault. The optical signal is input from the Input end of the input optical waveguide of the MRR, and the modulation voltage signal X is in the low-level "0" state. The MRR should be in the resonant on state, and the Drop end of the download optical waveguide should output an optical signal. However, due to the fault, no optical signal is output, and the optical signal is output from the Through end of the through optical waveguide.

[0038] Specifically, as Figure 3 shown, assume that the MRR has a stuck-at-1 fault. The optical signal is input from the Input end of the input optical waveguide of the MRR, and the modulation voltage signal X is in the high-level "1" state. The MRR should be in the resonant off state, and the Through end of the through optical waveguide should output an optical signal. However, due to the fault, no optical signal is output, and the optical signal is output from the Drop end of the download optical waveguide.

[0039] Specifically, as Figure 2 shown, Figure 2 The function of the structural device in Figure 2 is a one-bit binary all-optical comparator, which consists of 3 MRRs. Their modulation voltage signals are A, B1, and B2 respectively. The states of the modulation voltage signals B1 and B2 are always the same, so there are 4 input combinations. Assume that Figure 2 the MRR1, MRR2, and MRR are all fault-free, and the states of the modulation voltage signals A, B1, and B2 are 0, 1, and 1 respectively. Therefore, both MRR2 and MRR3 are in the resonant off state, and MRR1 is in the resonant on state. The optical signal is input from the 1 end of the input optical waveguide of MRR1. First, it is output from the 3 end of the download optical waveguide of MRR1, and there is no optical signal output from the 2 end of the through optical waveguide of MRR1. So, no optical signal enters the 4 end of the input optical waveguide of MRR2, and there is no optical signal output from the 5 end and the 6 end of the download optical waveguide of MRR2. Then, there is no optical signal output at the output end 11 either. Then, the optical signal is input from the 7 end of the input optical waveguide of MRR3 and is output from the 8 end of the through optical waveguide of MRR3. So, there is an optical signal output at the output end 12, and there is no optical signal output from the 9 end of the download optical waveguide of MRR3. Secondly, since there is no optical signal output from both the 5 end and the 9 end, no optical signal is superposed and input to the Y-branch coupler 10. So, there is no optical signal output at the output end 13. Finally, Figure 2 the logical states of F(A>B), F(A = B), and F(A<B) in

[0040] are 0, 0, and 1 respectively.

[0040] Similarly, when the modulation voltage signals A, B1, and B2 are the remaining 3 input combinations and MRR1, MRR2, and MRR3 are all fault-free, F (A>B) , F (A＝B) and F (A<B) can all output the corresponding logical state values at the ends.

[0041] Figure 2When there are no faults in MRR1, MRR2, and MRR3, the output truth table of the binary all-optical comparator is as shown in the following table:

[0042] Table 1. Truth table of the binary all-optical comparator when there are no faults in MRR1, MRR2, and MRR3

[0043]

[0044] Specifically, assume Figure 2 there is no fault in MRR1, MRR2 has a stuck-at-0 fault, and MRR3 has a stuck-at-1 fault, and the states of the modulation voltage signals A, B1, and B2 are 0, 1, and 1 respectively. The optical signal is input from the 1 end of the input optical waveguide of MRR1. Since there is no fault in MRR1 and the modulation voltage signal A = 0, the optical signal is output from the 3 end of the download optical waveguide of MRR1, and there is no optical signal output from the 2 end of the through optical waveguide of MRR1. Then, no optical signal enters the 4 end of the input optical waveguide of MRR2, so there is no optical signal output from the 5 end of the through optical waveguide of MRR2 and the 6 end of the download optical waveguide of MRR2, and there is no optical signal output at the output end 11 either; then the optical signal is input from the 7 end of the input optical waveguide of MRR3. Since MRR3 has a stuck-at-1 fault and the modulation voltage signal B2 = 1, the optical signal is output from the 9 end of the download optical waveguide of MRR3, and there is no optical signal output from the 8 end of the through optical waveguide of MRR3, so there is no optical signal output at the output end 12; secondly, since there is no optical signal output at the 5 end but there is an optical signal output at the 9 end, there is an optical signal input to the Y-branch coupler 10, so there is an optical signal output at the output end 13; finally, Figure 2 the logical states of F(A>B), F(A = B), and F(A<B) in

[0045] are 0, 1, and 0 respectively. (A>B) F (A＝B) and F (A<B) can output the corresponding logical state values at the ends.

[0046] Figure 2 When there is no fault in MRR1, MRR2 has a stuck-at-0 fault, and MRR3 has a stuck-at-1 fault, the output truth table of the binary all-optical comparator is as shown in the following table:

[0047] Table 2. Truth table of the binary all-optical comparator when there is no fault in MRR1, MRR2 has a stuck-at-0 fault, and MRR3 has a stuck-at-1 fault

[0048]

[0049] Combine the results in Table 1 and Table 2 into Table 3.

[0050] Table 3. Truth table of the binary all-optical comparator with and without faults

[0051]

[0052] Then, based on the results in Table 3, the relationship between each correct output result and each erroneous output result is compared, and the bit flip error (BFE), the maximum bit flip error (MAXBFE), and the error probability (EP) between the correct output result and the erroneous output result are calculated.

[0053] ① According to the results in Table 3, the bit flip error BFE between the correct output result and the incorrect output result in each input combination is calculated using formula (1), as shown in Table 4 below:

[0054] Table 4. Bit Flip Error (BFE) between the correct and incorrect output results for each input combination

[0055]

[0056] ② According to the results in Table 4, the maximum value of all the BFEs generated by the eight input combinations is calculated using formula (2): the maximum bit flip error MAXBFE, therefore,

[0057]

[0058] ③ According to the results in Table 4, the probability of error due to double faults for the eight input combinations is calculated using formula (3): error probability EP, therefore,

[0059]

[0060] In summary, MRR1, MRR2 and MRR3 can be combined in pairs to simultaneously cause the same or different fault input combinations, which is similar to the above-mentioned situation where MRR1 has no fault, MRR2 has a sluggish 0 fault, and MRR3 has a sluggish 1 fault, so it will not be repeated here.

[0061] The technical content and technical features of the present invention have been disclosed as above. However, those skilled in the art may still make various substitutions and modifications based on the disclosure of the present invention without departing from the intention of the present invention. Therefore, the scope of protection of the present invention should not be limited to the contents disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention and be covered by the claims of this patent application.

Claims

1. A double fault error calculation method for a binary all-optical comparator, characterized in that: A logic calculation circuit is provided, comprising n MRRs, the circuit including N input combinations, each combination capable of generating an m-bit output result; the binary all-optical comparator logic calculation circuit, comprising the n MRRs, can be divided into a fault-free analog equivalent circuit and a double-fault analog equivalent circuit, wherein a correct output result can be obtained according to the fault-free analog equivalent circuit, and an erroneous output result can be obtained according to the double-fault analog equivalent circuit; Comparing the relationship between each correct output result and each erroneous output result based on the correct output result and the erroneous output result, calculating a bit flip error (BFE) between the two, a maximum bit flip error (MAXBFE), and an error probability (EP) in N input combinations; Bit flip error (BFE): For each input combination, the correct output result is bitwise XORed with the incorrect output result and summed. The resulting value is the BFE for that input combination. Maximum bit flip error (MAXBFE): The maximum bit flip error (BFE) among all N input combinations is the MAXBFE. Error probability (EP): Among N input combinations, count the number of input combinations for which BFE is not 0 under each combination. The ratio of this number to the total number of input combinations N is the EP.

2. The double fault error calculation method of a binary all-optical comparator according to claim 1, characterized in that: Compare the relationship between each correct output result and each incorrect output result in each input combination, and calculate the bit flip error (BFE) between the correct output result and the incorrect output result. The specific expression of BFE is as follows: The i represents the i-th input combination, the i is included in N, the For XOR, the Represents the j-th logical value of the error output under the i-th input combination, the O i correct The jth logical value of the correct output under the i-th input combination; 3. The double fault error calculation method of a binary all-optical comparator according to claim 1, characterized in that: The maximum value of all the BFEs generated by the N input combinations is calculated as the maximum bit flip error (MAXBFE), that is, the worst result caused by double faults in the N input combinations. The specific expression of MAXBFE is as follows:

4. The double fault error calculation method of a binary all-optical comparator according to claim 1, characterized in that: The probability of an error occurring due to a double fault in the N input combinations is calculated, that is, the error probability (EP). The specific expression of EP is as follows:

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