Display method and device based on SoC cascade, electronic device and storage medium
By storing the video input data in different parts of the main SoC memory in the SoC cascade and encoding and decoding, the problem of delayed display in the prior art is solved, efficient video display is realized, and SoC resources are saved.
Patent Information
- Application Number
- CN202210332585.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-03-30
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2042-03-30
AI Technical Summary
The existing video display solution based on multi-SoC cascade needs to rely on external devices, and there is a problem of delayed display delivery.
The main SoC reads the video input data and stores it in the first part of memory, and sends it to the sub-SoC for encoding and decoding. The sub-SoC stores the codec data in the second part of memory, and the main SoC encodes the first part of data. Implement video output processing, avoid waiting between different SoCs, and directly display video.
It reduces the delay in sending video, improves the efficiency of SoC cascading video display, saves SoC resources, and does not require the participation of CPU or GPU.
Smart Images
Figure CN114745554B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of video coding and decoding, and in particular to a display method and device based on SoC cascade, an electronic device and a storage medium. Background Art
[0002] System-on-chip (SoC) has been widely used in various signal processing fields. In order to meet the growing performance requirements, a solution of cascading multiple SoCs has been proposed. At present, for codecs based on multi-SoC cascades, sub-SoCs usually need to be connected to external devices to implement codecs. In addition, for unified video display based on multi-SoC cascades, the participation of modules such as GPU is required. Therefore, the existing video display solutions based on multi-SoC cascades need to rely on external devices and have delayed display. Summary of the invention
[0003] Exemplary embodiments of the present invention provide a display method and apparatus based on SoC cascading, an electronic device, and a storage medium, which can improve the video display efficiency through SoC cascading.
[0004] In one aspect of the present invention, a display method based on SoC cascading is provided. The method comprises the steps of: the main SoC stores the received video input data in the first part of the main SoC memory, and sends the video input data to at least one sub-SoC cascaded with the main SoC; at least one sub-SoC encodes and decodes the video input data to obtain first codec data, and stores the first codec data in the second part sent to the main SoC for storage in the main SoC memory; the main SoC encodes and decodes the video input data stored in the first part to obtain second codec data, and performs video output processing based on the first codec data and the second codec data.
[0005] In another aspect of the present invention, a display device based on SoC cascade is provided. The device includes a main SoC and at least one sub-SoC cascaded with the main SoC. The main SoC is configured to: receive video input data, store the video input data in a first part of the main SoC memory, and send the video input data to at least one sub-SoC; at least one sub-SoC is configured to: encode and decode the video input data to generate first codec data, and send the first codec data to the main SoC to be stored in the second part of the main SoC memory; and the main SoC is further configured to: encode and decode the video input data stored in the first part of the main SoC memory to generate second codec data, and perform video output processing based on the first codec data and the second codec data.
[0006] In another aspect of the present invention, an electronic device is provided, comprising a memory configured to store a computer program and a processor configured to execute the computer program to perform the above display method.
[0007] In another aspect of the present invention, a storage medium is provided, wherein a computer program is stored on the medium, and the computer program is executed by a processor to implement the above display method.
[0008] According to an embodiment of the present invention, the video input data read by the main SoC is stored in the first part of the main SoC memory, and the sub-SoC of the main SoC is used to encode and decode the video input data and store the encoded and decoded data in the second part of the main SoC memory, so that different SoC encodings and decodings do not need to wait for each other. The data of the first part is encoded and decoded by the main SoC, and the encoded and decoded data of the first part and the second part are respectively displayed as videos, so that the encoded and decoded data of the main SoC and the sub-SoC are displayed respectively. Compared with the prior art that requires the encoded and decoded data of the main SoC and the sub-SoC to be merged and displayed, the data of the main SoC and the sub-SoC are displayed separately in the present invention, without the participation of modules such as CPU or GPU, saving SoC resources and reducing the display delay, thereby improving the video display efficiency of the SoC cascade. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 is a flow chart of a display method based on SoC cascade according to an embodiment of the present invention;
[0010] Figure 2 A schematic diagram for illustrating a display method based on SoC cascading according to an embodiment of the present invention;
[0011] Figure 3 is a flow chart of a display method based on SoC cascade according to an embodiment of the present invention;
[0012] Figure 4 is a flow chart of a display method based on SoC cascade according to an embodiment of the present invention;
[0013] Figure 5 is a structural diagram of a display device based on SoC cascade according to an embodiment of the present invention;
[0014] Figure 6 is a block diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0015] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.
[0016] In the existing technology, the video display solution based on multi-SoC cascade needs to rely on external devices and requires the use of modules such as GPU for display, which has the problem of delayed display.
[0017] In order to solve at least the above technical problems, the present disclosure provides a display method based on SoC cascade, wherein the video input data read by the main SoC is stored in the first part of the main SoC memory, and the video input data is sent to the sub-SoC cascaded with the main SoC, so that the sub-SoC encodes and decodes the video input data to obtain first codec data, and stores the first codec data in the second part of the main SoC memory, and the main SoC encodes and decodes the data in the first part to obtain second codec data, and performs video output processing based on the first codec data and the second codec data. In this way, according to the embodiments of the present disclosure, the display transmission delay can be reduced and the video display efficiency of the SoC cascade can be improved.
[0018] Hereinafter, the technical solution according to the present disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings.
[0019] Figure 1 is a flow chart showing a display method 100 based on SoC cascading according to an embodiment of the present disclosure. Figure 1 The method 100 includes the following steps 102 to 110.
[0020] In step 102, the main SoC receives the video input data and stores it in the first part of the memory of the main SoC. In some embodiments, the memory of the main SoC is first divided into a preset number of memory blocks, where the number of memory blocks is twice the number of sub-SoCs. In some embodiments, the memory is divided into a first part and a second part, the first part is the memory blocks of the first half of the memory, and the second part is the memory blocks of the second half of the memory. In this way, memory blocks matching the number of sub-SoCs can be preset for data storage, ensuring that there is enough storage space for data storage of the main SoC and encoding and decoding of the sub-SoCs.
[0021] In step 104, the main SoC sends the video input data to at least one sub-SoC cascaded with the main SoC. In some embodiments, at least one sub-SoC is cascaded with the main SoC.
[0022] In step 106, the sub-SoC encodes and decodes the video input data to obtain first codec data, and sends the codec data to the main SoC to be stored in the second part of the memory of the main SoC. In some embodiments, the sub-SoC corresponds to the memory block in the first part one-to-one, and the sub-SoC corresponds to the memory block in the second part one-to-one, so that the sub-SoC obtains the video input data in the corresponding memory block from the first part for encoding and decoding, and transmits the codec data to the corresponding memory block in the second part. In this way, both the video input data and the codec data can be stored in the main SoC, and the sub-SoC only needs to perform encoding and decoding, so that the sub-SoC does not need to be connected to an external device.
[0023] In some embodiments, the memory blocks to which the sub-SoC belongs in the first part and the second part are specified. In some embodiments, the memory blocks of the first part of each main SoC are sent to the corresponding sub-SoC through the fast peripheral component interconnect (PCIe) for encoding and decoding, and the encoded and decoded data obtained by encoding and decoding each sub-SoC are sent to the corresponding memory blocks of the second part of the main SoC through the fast peripheral component interconnect. It can be understood that the fast peripheral component interconnect interface is a high-speed serial computer expansion bus. In this way, it is ensured that the sub-SoC corresponds to the memory blocks in the first part and the second part one by one.
[0024] In step 108, the main SoC encodes and decodes the video input data stored in the first part of the memory to obtain second encoded data. In some embodiments, the display area is initialized, and the second encoded and decoded data is loaded into the first layer of the display area according to the address data corresponding to the first part, and the first encoded and decoded data is loaded into the second layer of the display area according to the address data corresponding to the second part. In this way, the encoded and decoded data of multiple SoCs does not need to synthesize the encoded and decoded data of the main SoC and the sub-SoC, but is displayed by sending them to the display separately, thereby improving display efficiency.
[0025] In step 110, the main SoC performs video output processing based on the first codec data and the second codec data. In some embodiments, first display data corresponding to the first picture is output based on the first codec data; and second display data corresponding to the second picture is output based on the second codec data, wherein the first picture and the second picture are combined into a target display picture. In this way, by sending and displaying the first coded data and the second coded data separately, and combining different pictures, the GPU and CPU modules in the SoC are not required to perform operations such as combining pictures, thereby saving SoC resources.
[0026] Hereinafter, application scenarios of the display method and device based on SoC cascading according to embodiments of the present invention will be described by way of examples.
[0027] Figure 2 FIG. 4 is a schematic diagram for illustrating a display method based on SoC cascading according to an embodiment of the present invention.
[0028] like Figure 2 As shown, the memory of the main SoC module is divided into 2N memory blocks, the 1st to Nth memory blocks are the memory blocks of the first part, and the N+1th to 2Nth memory blocks are the memory blocks of the second part.
[0029] The main SoC stores the video input data in the memory block of the first part through the video input module.
[0030] The main SoC is cascaded with at least one sub-SoC, and the video input data is sent to the sub-SoC cascaded with the main SoC through the main SoC. In some embodiments, the video input data of the first part in the memory block of the main SoC is transmitted to the sub-SoC through the first peripheral component interconnect express interface, and the sub-SoC obtains the video input data through the second peripheral component interconnect express interface, and uses the second codec module to encode and decode the video data into the first codec data.
[0031] The sub-SoC transmits the first codec data to the main SoC through the second peripheral component interconnect express interface, and the main SoC obtains the first codec data through the first peripheral component interconnect express interface and stores it in the memory block of the second part.
[0032] In some embodiments, each sub-SoC corresponds one-to-one to each memory block in the first part and each memory block in the second part, so that each sub-SoC encodes and decodes the video input data in the corresponding memory block from the first part to obtain first encoded and decoded data, and stores the first encoded and decoded data in the corresponding memory block of the second part.
[0033] The main SoC encodes and decodes the video input data in the memory block of the first part according to the second codec module to obtain second codec data, and transmits the second codec data to layer Layer0, and transmits the first codec data in the memory block of the second part to layer Layer1, thereby obtaining first display data corresponding to the first picture based on the first codec data, obtaining second display data corresponding to the second picture based on the second codec data, and combining the first picture and the second picture for display through the video output processing module (Video Output Processor, VOP).
[0034] Figure 3 is a flowchart showing the encoding and decoding of the display method based on SoC cascade according to an embodiment of the present invention, including the following steps 302 to 314.
[0035] In step 302, the video input module of the main SoC transmits the video input data to the main SoC in the format of H264 or H265.
[0036] At step 304, the video input data is transferred and stored in the first N memory blocks of the main SoC.
[0037] In step 306, each memory block in the first N memory blocks is matched to a sub-SoC one by one, and the data in the memory block is sent to the corresponding sub-SoC through PCIE.
[0038] In step 308, encoding and decoding of the video input data is performed in the sub-SoC.
[0039] In step 310, the encoded and decoded data is sent to the main SoC via PCIE.
[0040] In step 312, each memory block in the N memory blocks after the main SoC is matched with the sub-SoC one by one, and the encoded and decoded data is sent to the corresponding memory block through PCIE.
[0041] In step 314, the data in the last N memory blocks are displayed.
[0042] Figure 4 4 is a flowchart showing a unified display of a display method based on SoC cascade according to an embodiment of the present invention, including the following steps 402 to 408.
[0043] In step 402, the display areas of all SoCs are initialized.
[0044] In step 404, the encoded data of the first part of the memory block in the main SoC is loaded into the designated layer.
[0045] In step 406, the data of the second part of the memory block in the main SoC is loaded into the designated layer.
[0046] In step 408, display is performed on a physical display device.
[0047] According to another aspect of the present invention, Figure 5 is a block diagram showing a display device 500 based on SoC cascade connection according to an embodiment of the present invention. The display device 500 based on SoC cascade connection includes a main SoC 502 and at least one sub-SoC 504 cascaded with the main SoC.
[0048] The main SoC 502 is configured to: receive video input data and store the video input data in a first portion of a memory of the main SoC 502 ; and send the video input data to at least one sub-SoC 504 .
[0049] The at least one sub-SoC 504 is configured to encode and decode the video input data to generate first coded data, and send the first coded data to the main SoC 502 to be stored in the second portion of the memory.
[0050] In some embodiments, the main SoC 502 is further configured to: encode and decode the video input data stored in the first portion of the memory to generate second codec data, and perform video output processing based on the first codec data and the second codec data.
[0051] In some embodiments, the main SoC 502 includes a first peripheral component interconnect express (PCIe) interface, which is configured to send video input data to at least one sub-SoC 504 and receive the first codec data from at least one sub-SoC 504. The sub-SoC 504 in at least one sub-SoC 504 includes a second peripheral component interconnect express interface, which is configured to receive the video input data from the main SoC 502 and send the first codec data to the main SoC 502. It can be understood that the PCIe interface is a high-speed serial computer expansion bus. In this way, it is ensured that the sub-SoC 504 corresponds to the memory blocks in the first part of the memory of the main SoC 502 and the memory blocks in the second part.
[0052] In some embodiments, the main SoC 502 further includes a video input module, a memory, a first codec module, and a video output processing module.
[0053] The video input module is configured to receive video input data. The memory includes a first part of memory blocks and a second part of memory blocks, and the first part of memory blocks and the second part of memory blocks correspond to each sub-SoC504 in at least one sub-SoC. The first codec module is configured to encode and decode the video input data stored in the first part of the memory to generate second codec data. The video output processing module is configured to output first display data corresponding to the first picture and second display data corresponding to the second picture based on the first codec data and the second codec data, respectively, and the first picture and the second picture are combined into a target display picture.
[0054] In some embodiments, the video output processing module is further configured to: be able to initialize the display area, load the second codec data into the first layer of the display area according to the address data corresponding to the first part; and load the first codec data into the second layer of the display area according to the address data corresponding to the second part.
[0055] In some embodiments, the sub-SoC 504 in the at least one sub-SoC further includes a second codec module, and the second codec module is configured to encode and decode the video input data from the first portion of the memory to generate first codec data.
[0056] According to yet another aspect of the present invention, Figure 6 is a schematic diagram showing an electronic device 600 according to an embodiment of the present invention. Figure 6 The electronic device 600 includes a memory 602, a processor 604, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the various steps of the display method described above are implemented.
[0057] According to another aspect of the present invention, a computer readable medium is provided, wherein a computer program is stored on the computer readable medium, and the computer program is executed by a processor to implement the various steps of the display method described above.
[0058] In summary, the display method and device, electronic device and storage medium based on SoC cascade provided by the present invention store the video input data read by the main SoC in the first part of the main SoC memory, use the sub-SoC of the main SoC to encode and decode the video input data and store the encoded and decoded data in the second part of the main SoC memory, so different SoC encoding and decoding do not need to wait for each other. Among them, the video input data and the encoded and decoded data are stored in the main SoC, and the sub-SoC only needs to perform encoding and decoding, so that the sub-SoC can abandon external devices such as emmc to save hardware costs and improve the overall encoding and decoding performance. The data of the first part is encoded and decoded by the main SoC, and the encoded and decoded data of the first part and the data of the second part are respectively displayed as videos, so that the display is directly based on the encoded and decoded data of the main SoC and the sub-SoC, and there is no need to merge the encoded and decoded data of the main SoC and the sub-SoC, that is, there is no need to participate in modules such as GPU, which saves SoC resources and reduces the display transmission delay, thereby improving the video display efficiency of the SoC cascade.
[0059] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A display method based on SoC cascade, characterized in that: include: Receiving video input data by a master SoC and storing the video input data in a first portion of a memory of the master SoC; The main SoC sends the video input data to at least one sub-SoC cascaded with the main SoC; Encoding and decoding the video input data by the at least one sub-SoC to generate first coded data, and sending the first coded data to the main SoC to be stored in the second part of the memory; The main SoC encodes and decodes the video input data stored in the first part of the memory to generate second encoded data; as well as The main SoC performs video output processing based on the first codec data and the second codec data, including: outputting first display data corresponding to a first picture based on the first codec data, and outputting second display data corresponding to a second picture based on the second codec data, wherein the first picture and the second picture are combined into a target display picture.
2. The display method according to claim 1, characterized in that: Also includes: Dividing the memory of the main SoC into a preset number of memory blocks, the number of the memory blocks being twice the number of the at least one sub-SoC; The memory includes the first part and the second part, the first part is the memory blocks of the first half of the memory, the second part is the memory blocks of the second half of the memory, and the number of memory blocks in the first part and the second part is the same.
3. The display method according to claim 2, characterized in that: The second part of encoding and decoding the video input data by the at least one sub-SoC to generate first encoded and decoded data, and sending the first encoded and decoded data to the main SoC to store in the memory includes: Aligning the at least one sub-SoC with the memory blocks in the first part and the memory blocks in the second part one by one; and Each of the at least one sub-SoC encodes and decodes the video input data in the corresponding memory block from the first part to obtain corresponding coded data, and stores the corresponding coded data in the corresponding memory block of the second part.
4. The display method according to claim 3, characterized in that: The one-to-one correspondence between the at least one sub-SoC and the memory blocks in the first part and the memory blocks in the second part comprises: The memory block to which the at least one sub-SoC belongs in the first part and the second part is specified.
5. The display method according to claim 3, characterized in that: The step of encoding and decoding the video input data in the corresponding memory block from the first part by each of the at least one sub-SoC to obtain corresponding encoded and decoded data, and storing the corresponding encoded and decoded data in the corresponding memory block of the second part comprises: The main SoC sends the video input data in each memory block of the first part to the corresponding sub-SoC through the peripheral component interconnect fast interface for encoding and decoding; and The at least one sub-SoC sends each piece of codec data obtained by coding and decoding to the corresponding memory block of the second part of the main SoC through a peripheral component interconnect express interface.
6. The display method according to claim 1, characterized in that: The main SoC performs video output processing based on the first codec data and the second codec data, including: Initializing a display area, and loading the second codec data into a first layer of the display area according to address data corresponding to the first part; and The first codec data is loaded into a second layer of the display area according to address data corresponding to the second part.
7. A display device, characterized in that: comprising a main SoC and at least one sub-SoC cascaded with the main SoC, The main SoC is configured to: receive video input data and store the video input data in a first portion of a memory of the main SoC; and send the video input data to the at least one sub-SoC, The at least one sub-SoC is configured to: encode and decode the video input data to generate first codec data, and send the first codec data to the main SoC to be stored in the second part of the memory, The main SoC is further configured to: encode and decode the video input data stored in the first part of the memory to generate second encoded data; and performing video output processing based on the first codec data and the second codec data, The main SoC further comprises: A video input module, configured to receive the video input data; A memory, comprising memory blocks of the first part and memory blocks of the second part, wherein the memory blocks of the first part and the memory blocks of the second part correspond one-to-one to each sub-SoC in the at least one sub-SoC; a first codec module configured to encode and decode the video input data stored in the first portion of the memory to generate the second codec data; The video output processing module is configured to output first display data corresponding to a first picture and second display data corresponding to a second picture respectively based on the first codec data and the second codec data, and the first picture and the second picture are combined into a target display picture.
8. The display device according to claim 7, characterized in that: The main SoC includes a first peripheral component interconnect express interface, the first peripheral component interconnect express interface being configured to send the video input data to the at least one sub-SoC and receive the first codec data from the at least one sub-SoC; The sub-SoC of the at least one sub-SoC includes a second peripheral component interconnect express interface configured to receive the video input data from the main SoC and to send the first codec data to the main SoC.
9. The display device according to claim 7, characterized in that: The video output processing module is further configured to: Initializing a display area, and loading the second codec data into a first layer of the display area according to address data corresponding to the first part; and The first codec data is loaded into a second layer of the display area according to address data corresponding to the second part.
10. The display device according to claim 7, characterized in that: The sub-SoC in the at least one sub-SoC further comprises: The second codec module is configured to encode and decode the video input data from the first part of the memory to generate the first codec data.
11. An electronic device, characterized in that: include: a memory configured to store a computer program; as well as A processor configured to execute the computer program to perform the display method according to any one of claims 1 to 6.
12. A storage medium having a computer program stored thereon, characterized in that: The computer program is executed by a processor to implement the display method according to any one of claims 1 to 6.