GOA circuit and display panel

Abstract

In the GOA circuit and display panel provided in the embodiment of the present application, the first scan signal of this level, the second scan signal of this level, and the third scan signal of this level share a pull-up control module, a level transmission module, and a pull-down module, the fourth scan signal of this level, the fifth scan signal of this level, and the sixth scan signal of this level share a pull-up control module, a level transmission module, and a pull-down module, and the first scan signal of this level, the second scan signal of this level, the third scan signal of this level, the fourth scan signal of this level, the fifth scan signal of this level, and the sixth scan signal of this level share a pull-down control module, thereby reducing the number of modules of the GOA circuit, further reducing the design space of the GOA circuit, which is beneficial to the narrow frame design of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a GOA circuit and a display panel. Background Art

[0002] At present, GOA (English full name: Gate Driver on Array, Chinese full name: integrated gate drive circuit) technology integrates the gate drive circuit on the array substrate of the display panel, thereby eliminating the gate drive integrated circuit part to reduce product costs in terms of material cost and manufacturing process, and at the same time makes the display panel more suitable for making narrow-frame display products.

[0003] Among them, large-size, high-definition, narrow-frame LCD panels have become the mainstream development trend in the industry. However, as the panel size and resolution increase, the GOA load also increases accordingly, so the size of each GOA thin-film transistor and the panel frame will also increase, which is not conducive to the narrow-frame design of the LCD panel. Especially for tri-gate drive architecture products, since the number of data lines is reduced to one-third of the normal drive architecture, the number of scan lines is increased to three times the normal drive architecture. Therefore, the GOA load is further increased, and the narrow-frame design requirements are more difficult to achieve.

[0004] Therefore, how to propose a GOA circuit that can meet the narrow frame design of existing three-gate drive architecture products is a difficult problem that existing panel manufacturers need to work hard to overcome. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a GOA circuit and a display panel, which can solve the technical problem that the existing GOA circuit cannot meet the narrow frame design of the existing three-gate drive architecture product.

[0006] The embodiment of the present application provides a GOA circuit, including: a cascaded multi-stage GOA circuit sharing unit, each stage of the GOA circuit sharing unit includes: a first pull-up control module, a first stage transmission module, a first output module, a first pull-down module, a second pull-up control module, a second stage transmission module, a second output module, a second pull-down module and a pull-down maintaining module;

[0007] The first pull-up control module is connected to the first-stage transmission signal of the previous stage and the reference high-level signal, and is electrically connected to the first node. The first pull-up control module is used to pull the potential of the first node to the potential of the reference high-level under the control of the first-stage transmission signal of the previous stage.

[0008] The first output module receives the first clock signal, the second clock signal and the third clock signal and is electrically connected to the first node. The first output module is used to output the first scanning signal of the current level, the second scanning signal of the current level and the third scanning signal of the current level under the potential control of the first node.

[0009] The first-stage transmission module is connected to the third clock signal and is electrically connected to the first node. The first-stage transmission module is used to output the first-stage transmission signal of the current stage under the potential control of the first node.

[0010] The first pull-down module is connected to the fourth scan signal of the next level, the first reference low-level signal, the first-level transmission signal of the current level, the first scan signal of the current level, the second scan signal of the current level, and the third scan signal of the current level, and is electrically connected to the first node. The first pull-down module is used to pull down the potential of the first node, the first-level transmission signal of the current level, the first scan signal of the current level, the second scan signal of the current level, and the third scan signal of the current level to the first reference low-level signal under the control of the fourth scan signal of the next level.

[0011] The second pull-up control module is connected to the second-stage transmission signal of the previous stage and the reference high-level signal, and is electrically connected to the third node. The second pull-up control module is used to pull the potential of the third node to the potential of the reference high-level under the control of the second-stage transmission signal of the previous stage.

[0012] The second output module receives the fourth clock signal, the fifth clock signal and the sixth clock signal and is electrically connected to the third node. The second output module is used to output the fourth scanning signal of the current level, the fifth scanning signal of the current level and the sixth scanning signal of the current level under the potential control of the third node.

[0013] The second-stage transmission module is connected to the sixth clock signal and is electrically connected to the third node. The second-stage transmission module is used to output the second-stage transmission signal of the current stage under the potential control of the third node.

[0014] The second pull-down module is connected to the first scanning signal of the next second level, the first reference low-level signal, the second-level transmission signal of the current level, the fourth scanning signal of the current level, the fifth scanning signal of the current level, and the sixth scanning signal of the current level, and is electrically connected to the third node. The second pull-down module is used to pull down the potential of the third node, the second-level transmission signal of the current level, the fourth scanning signal of the current level, the fifth scanning signal of the current level, and the sixth scanning signal of the current level to the potential of the first reference low-level signal under the control of the first scanning signal of the next second level.

[0015] The pull-down maintaining module is connected to the first reference low-level signal and is electrically connected to the first node, the second node, the third node and the fourth node. The pull-down maintaining module is used to maintain the potential of the first node, the third node, the first-level transmission signal of the current level, the second-level transmission signal of the current level, the first scan signal of the current level, the second scan signal of the current level, the third scan signal of the current level, the fourth scan signal of the current level, the fifth scan signal of the current level and the sixth scan signal of the current level at the potential of the first reference low-level signal under the potential control of the second node. The pull-down maintaining module is used to maintain the potential of the first node, the third node, the first-level transmission signal of the current level, the second-level transmission signal of the current level, the first scan signal of the current level, the second scan signal of the current level, the third scan signal of the current level, the fourth scan signal of the current level, the fifth scan signal of the current level and the sixth scan signal of the current level at the potential of the first reference low-level signal under the potential control of the fourth node; wherein,

[0016] The pulse periods of the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are the same, and the falling edge of each clock signal is aligned with the rising edge of its adjacent subsequent clock signal.

[0017] In the GOA driving circuit described in the present application, each level of the GOA circuit sharing unit further includes a first bootstrap capacitor, a second bootstrap capacitor, a third bootstrap capacitor, a fourth bootstrap capacitor, a fifth bootstrap capacitor and a sixth bootstrap capacitor, one end of the first bootstrap capacitor is electrically connected to the first node, and the other end of the first bootstrap capacitor is electrically connected to the first scan signal of the current level, one end of the second bootstrap capacitor is electrically connected to the first node, and the other end of the second bootstrap capacitor is electrically connected to the second scan signal of the current level, one end of the third bootstrap capacitor is electrically connected to the first node, and the other end of the third bootstrap capacitor is electrically connected to the third scan signal of the current level, one end of the fourth bootstrap capacitor is electrically connected to the third node, and the other end of the fourth bootstrap capacitor is electrically connected to the fourth scan signal of the current level, one end of the fifth bootstrap capacitor is electrically connected to the third node, and the other end of the fifth bootstrap capacitor is electrically connected to the fifth scan signal of the current level, one end of the sixth bootstrap capacitor is electrically connected to the first node, and the other end of the sixth bootstrap capacitor is electrically connected to the sixth scan signal of the current level.

[0018] In the GOA driving circuit described in the present application, the first pull-up control module includes a first pull-up thin film transistor, the gate of the first pull-up thin film transistor is connected to the first-stage transmission signal of the previous stage, one of the source and the drain of the first pull-up thin film transistor is connected to the reference high-level signal, and the other of the source and the drain of the first pull-up thin film transistor is electrically connected to the first node;

[0019] The second pull-up control module includes a second pull-up thin film transistor, a gate of the second pull-up thin film transistor is connected to the second-stage transmission signal of the previous stage, one of the source and the drain of the second pull-up thin film transistor is connected to the reference high-level signal, and the other of the source and the drain of the second pull-up thin film transistor is electrically connected to the third node.

[0020] In the GOA driving circuit described in the present application, the first output module includes a first output thin film transistor, a second output thin film transistor and a third output thin film transistor, the gate of the first output thin film transistor is connected to the first node, one of the source and the drain of the first output thin film transistor is connected to the first clock signal, the other of the source and the drain of the first output thin film transistor is connected to the first scan signal of the current stage, the gate of the second output thin film transistor is connected to the first node, one of the source and the drain of the second output thin film transistor is connected to the second clock signal, the other of the source and the drain of the second output thin film transistor is connected to the second scan signal of the current stage, the gate of the third output thin film transistor is connected to the first node, one of the source and the drain of the third output thin film transistor is connected to the third clock signal, and the other of the source and the drain of the third output thin film transistor is connected to the third scan signal of the current stage;

[0021] The second output module includes a fourth output thin film transistor, a fifth output thin film transistor and a sixth output thin film transistor, the gate of the fourth output thin film transistor is electrically connected to the third node, one of the source and the drain of the fourth output thin film transistor is connected to the fourth clock signal, and the other of the source and the drain of the fourth output thin film transistor is connected to the fourth scan signal of this level, the gate of the fifth output thin film transistor is electrically connected to the third node, one of the source and the drain of the fifth output thin film transistor is connected to the fifth clock signal, and the other of the source and the drain of the fifth output thin film transistor is connected to the fifth scan signal of this level, the gate of the sixth output thin film transistor is electrically connected to the third node, one of the source and the drain of the sixth output thin film transistor is connected to the sixth clock signal, and the other of the source and the drain of the sixth output thin film transistor is connected to the sixth scan signal of this level.

[0022] In the GOA driving circuit described in the present application, the first-stage transmission module includes a first-stage transmission thin film transistor, the gate of the first-stage transmission thin film transistor is electrically connected to the first node, one of the source and the drain of the first-stage transmission thin film transistor is connected to the third clock signal, and the other of the source and the drain of the first-stage transmission thin film transistor is connected to the first-stage transmission signal of the current stage;

[0023] The second-level transmission module includes a second-level transmission thin film transistor, the gate of the second-level transmission thin film transistor is electrically connected to the third node, one of the source and the drain of the second-level transmission thin film transistor is connected to the sixth clock signal, and the other of the source and the drain of the second-level transmission thin film transistor is connected to the second-level transmission signal of this level.

[0024] In the GOA driving circuit described in the present application, the first pull-down module includes a first pull-down thin film transistor, the gate of the first pull-down thin film transistor is connected to the fourth scan signal of the next stage, one of the source and the drain of the first pull-down thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the first pull-down thin film transistor is electrically connected to the first node, and the other of the source and the drain of the first pull-down thin film transistor is connected to the first stage transmission signal of the current stage, the first scan signal of the current stage, the second scan signal of the current stage, and the third scan signal of the current stage;

[0025] The second pull-down module includes a second pull-down thin film transistor, a gate of the second pull-down thin film transistor is connected to the first scanning signal of the next second level, one of the source and the drain of the second pull-down thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the second pull-down thin film transistor is electrically connected to the third node, and the other of the source and the drain of the second pull-down thin film transistor is connected to the second-level transmission signal of the current level, the fourth scanning signal of the current level, the fifth scanning signal of the current level and the sixth scanning signal of the current level.

[0026] In the GOA driving circuit described in the present application, the first pull-down module is also connected to the second-level transmission signal of the next level, and the first pull-down module is also used to pull down the potential of the first node, the first-level transmission signal of the current level, the first scanning signal of the current level, the second scanning signal of the current level, and the third scanning signal of the current level to the first reference low-level signal under the control of the second-level transmission signal of the next level;

[0027] The second pull-down module is also connected to the first-level transmission signal of the next two levels, and the first pull-down module is also used to pull down the potential of the first node, the first-level transmission signal of the current level, the first scan signal of the current level, the second scan signal of the current level and the third scan signal of the current level to the first reference low-level signal under the control of the first-level transmission signal of the next two levels.

[0028] In the GOA driving circuit described in the present application, the first pull-down module further includes a third pull-down thin film transistor, the gate of the third pull-down thin film transistor is connected to the second-level transmission signal of the next level, one of the source and the drain of the third pull-down thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the third pull-down thin film transistor is electrically connected to the first node, and the other of the source and the drain of the third pull-down thin film transistor is connected to the first-level transmission signal of the current level, the first scan signal of the current level, the second scan signal of the current level, and the third scan signal of the current level;

[0029] The second pull-down module includes a fourth pull-down thin film transistor, a gate of the fourth pull-down thin film transistor is connected to the first-level transmission signal of the next two levels, one of the source and the drain of the fourth pull-down thin film transistor is connected to the first reference low-level signal, the other of the source and the drain of the fourth pull-down thin film transistor is electrically connected to the third node, and the other of the source and the drain of the fourth pull-down thin film transistor is connected to the second-level transmission signal of the current level, the fourth scanning signal of the current level, the fifth scanning signal of the current level, and the sixth scanning signal of the current level.

[0030] In the GOA driving circuit described in the present application, the pull-down maintenance module includes a first pull-down maintenance thin film transistor, a second pull-down maintenance thin film transistor, a third pull-down maintenance thin film transistor and a fourth pull-down maintenance thin film transistor; wherein,

[0031] The gate of the first pull-down sustaining thin film transistor is electrically connected to the second node, one of the source and the drain of the first pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the first pull-down sustaining thin film transistor is electrically connected to the first node, and the other of the source and the drain of the first pull-down sustaining thin film transistor is connected to the first level transmission signal of the current stage, the first scan signal of the current stage, the second scan signal of the current stage, and the third scan signal of the current stage; the gate of the second pull-down sustaining thin film transistor is electrically connected to the fourth node, one of the source and the drain of the second pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the second pull-down sustaining thin film transistor is electrically connected to the first node, and the other of the source and the drain of the second pull-down sustaining thin film transistor is connected to the first level transmission signal of the current stage, the first scan signal of the current stage, the second scan signal of the current stage, and the third scan signal of the current stage;

[0032] The gate of the third pull-down sustaining thin film transistor is electrically connected to the second node, one of the source and the drain of the third pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the third pull-down sustaining thin film transistor is electrically connected to the third node, and the other of the source and the drain of the third pull-down sustaining thin film transistor is connected to the second level transmission signal of this level, the fourth scan signal of this level, the fifth scan signal of this level and the sixth scan signal of this level; the gate of the fourth pull-down sustaining thin film transistor is electrically connected to the fourth node, one of the source and the drain of the fourth pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the fourth pull-down sustaining thin film transistor is electrically connected to the third node, and the other of the source and the drain of the fourth pull-down sustaining thin film transistor is connected to the second level transmission signal of this level, the fourth scan signal of this level, the fifth scan signal of this level and the sixth scan signal of this level.

[0033] In the GOA driving circuit described in the present application, the pull-down maintaining module is also connected to a second reference low level signal, and the pull-down maintaining module is used to maintain the potential of the first node, the first-level transmission signal of the current level, the third node, and the second-level transmission signal of the current level at the second reference low level under the potential control of the second node, and is used to maintain the potential of the first scan signal of the current level, the second scan signal of the current level, the third scan signal of the current level, the fourth scan signal of the current level, the fifth scan signal of the current level, and the sixth scan signal of the current level at the first reference low level signal under the potential control of the second node, and is used to maintain the potential of the first node, the first-level transmission signal of the current level, the third node, and the second-level transmission signal of the current level at the second reference low level under the potential control of the fourth node, and is used to maintain the potential of the first scan signal of the current level, the second scan signal of the current level, the third scan signal of the current level, the fourth scan signal of the current level, the fifth scan signal of the current level, and the sixth scan signal of the current level at the first reference low level signal under the potential control of the fourth node.

[0034] In the GOA driving circuit described in the present application, the pull-down maintenance module includes a fifth pull-down maintenance thin film transistor, a sixth pull-down maintenance thin film transistor, a seventh pull-down maintenance thin film transistor, an eighth pull-down maintenance thin film transistor, a ninth pull-down maintenance thin film transistor, a tenth pull-down maintenance thin film transistor, an eleventh pull-down maintenance thin film transistor and a twelfth pull-down maintenance thin film transistor; wherein,

[0035] The gate of the fifth pull-down sustaining thin film transistor is electrically connected to the second node, one of the source and the drain of the fifth pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the fifth pull-down sustaining thin film transistor is electrically connected to the first node, and the other of the source and the drain of the fifth pull-down sustaining thin film transistor is connected to the first stage transmission signal of the current level, the gate of the sixth pull-down sustaining thin film transistor is electrically connected to the second node, one of the source and the drain of the sixth pull-down sustaining thin film transistor is connected to the second reference low level signal, and the other of the source and the drain of the sixth pull-down sustaining thin film transistor is connected to the first scan signal of the current level, the second scan signal of the current level, and the third scan signal of the current level;

[0036] The gate of the seventh pull-down sustaining thin film transistor is electrically connected to the fourth node, one of the source and the drain of the seventh pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the seventh pull-down sustaining thin film transistor is electrically connected to the first node, and the other of the source and the drain of the seventh pull-down sustaining thin film transistor is connected to the first level transmission signal of the current stage, the gate of the eighth pull-down sustaining thin film transistor is electrically connected to the fourth node, one of the source and the drain of the eighth pull-down sustaining thin film transistor is connected to the second reference low level signal, and the other of the source and the drain of the eighth pull-down sustaining thin film transistor is connected to the first scan signal of the current stage, the second scan signal of the current stage, and the third scan signal of the current stage;

[0037] The gate of the ninth pull-down sustaining thin film transistor is electrically connected to the second node, one of the source and the drain of the ninth pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the ninth pull-down sustaining thin film transistor is electrically connected to the third node, and the other of the source and the drain of the ninth pull-down sustaining thin film transistor is connected to the second level transmission signal of the current stage; the gate of the tenth pull-down sustaining thin film transistor is electrically connected to the second node, one of the source and the drain of the tenth pull-down sustaining thin film transistor is connected to the second reference low level signal, and the other of the source and the drain of the tenth pull-down sustaining thin film transistor is connected to the fourth scan signal of the current stage, the fifth scan signal of the current stage, and the sixth scan signal of the current stage;

[0038] The gate of the eleventh pull-down maintenance thin film transistor is electrically connected to the fourth node, one of the source and the drain of the eleventh pull-down maintenance thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the eleventh pull-down maintenance thin film transistor is electrically connected to the third node, and the other of the source and the drain of the eleventh pull-down maintenance thin film transistor is connected to the second level transmission signal of the current level; the gate of the twelfth pull-down maintenance thin film transistor is electrically connected to the fourth node, one of the source and the drain of the twelfth pull-down maintenance thin film transistor is connected to the second reference low level signal, and the other of the source and the drain of the twelfth pull-down maintenance thin film transistor is connected to the fourth scan signal of the current level, the fifth scan signal of the current level, and the sixth scan signal of the current level.

[0039] In the GOA driving circuit described in the present application, the pull-down maintenance module includes a thirteenth pull-down maintenance thin film transistor, a fourteenth pull-down maintenance thin film transistor, a fifteenth pull-down maintenance thin film transistor, a sixteenth pull-down maintenance thin film transistor, a seventeenth pull-down maintenance thin film transistor, an eighteenth pull-down maintenance thin film transistor, a nineteenth pull-down maintenance thin film transistor, a twentieth pull-down maintenance thin film transistor, a twenty-first pull-down maintenance thin film transistor, a twenty-second pull-down maintenance thin film transistor, a twenty-third pull-down maintenance thin film transistor, a twenty-fourth pull-down maintenance thin film transistor, a twenty-fifth pull-down maintenance thin film transistor, a twenty-sixth pull-down maintenance thin film transistor, a twenty-seventh pull-down maintenance thin film transistor, a twenty-eighth pull-down maintenance thin film transistor, a twenty-ninth pull-down maintenance thin film transistor, a thirtieth pull-down maintenance thin film transistor, a thirty-first pull-down maintenance thin film transistor, and a thirty-second pull-down maintenance thin film transistor; wherein,

[0040] The gates of the thirteenth pull-down sustaining thin film transistor and the fourteenth pull-down sustaining thin film transistor are electrically connected to the second node, the source and the drain of the thirteenth pull-down sustaining thin film transistor and the fourteenth pull-down sustaining thin film transistor are both connected to the first reference low level signal, the other of the source and the drain of the thirteenth pull-down sustaining thin film transistor is electrically connected to the first node, the other of the source and the drain of the fourteenth pull-down sustaining thin film transistor is connected to the first stage transmission signal of the current stage, the fifteenth pull-down sustaining thin film transistor, the sixteenth pull-down sustaining thin film transistor and the The gates of the seventeenth pull-down sustaining thin film transistors are all electrically connected to the second node, the source and the drain of the fifteenth pull-down sustaining thin film transistor, the sixteenth pull-down sustaining thin film transistor and the seventeenth pull-down sustaining thin film transistor are all connected to the second reference low level signal, the other of the source and the drain of the fifteenth pull-down sustaining thin film transistor is connected to the first scan signal of the current stage, the other of the source and the drain of the sixteenth pull-down sustaining thin film transistor is connected to the second scan signal of the current stage, and the other of the source and the drain of the seventeenth pull-down sustaining thin film transistor is connected to the third scan signal of the current stage;

[0041] The gates of the eighteenth pull-down sustaining thin film transistor and the nineteenth pull-down sustaining thin film transistor are electrically connected to the fourth node, one of the source and the drain of the eighteenth pull-down sustaining thin film transistor and the nineteenth pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the eighteenth pull-down sustaining thin film transistor is electrically connected to the first node, the other of the source and the drain of the nineteenth pull-down sustaining thin film transistor is connected to the first stage transmission signal of the current stage, the 20th pull-down sustaining thin film transistor, the 21st pull-down sustaining thin film transistor and the 20th The gates of the second pull-down sustaining thin film transistors are electrically connected to the fourth node, one of the source and the drain of the 20th pull-down sustaining thin film transistor, the 21st pull-down sustaining thin film transistor and the 22nd pull-down sustaining thin film transistor is connected to the second reference low level signal, the other of the source and the drain of the 20th pull-down sustaining thin film transistor is connected to the first scan signal of the current stage, the other of the source and the drain of the 21st pull-down sustaining thin film transistor is connected to the second scan signal of the current stage, and the other of the source and the drain of the 22nd pull-down sustaining thin film transistor is connected to the third scan signal of the current stage;

[0042] The gates of the twenty-third pull-down sustaining thin film transistor and the twenty-fourth pull-down sustaining thin film transistor are both electrically connected to the second node, the source and the drain of the twenty-third pull-down sustaining thin film transistor and the twenty-fourth pull-down sustaining thin film transistor are both connected to the first reference low level signal, the other of the source and the drain of the twenty-third pull-down sustaining thin film transistor is electrically connected to the third node, the other of the source and the drain of the twenty-fourth pull-down sustaining thin film transistor is connected to the second stage transmission signal of the current stage, the twenty-fifth pull-down sustaining thin film transistor, the twenty-sixth pull-down sustaining thin film transistor and the The gates of the twenty-seventh pull-down sustaining thin film transistors are all electrically connected to the second node, the source and the drain of the twenty-fifth pull-down sustaining thin film transistor, the twenty-sixth pull-down sustaining thin film transistor, and the twenty-seventh pull-down sustaining thin film transistor are all connected to the second reference low level signal, the other of the source and the drain of the twenty-fifth pull-down sustaining thin film transistor is connected to the fourth scan signal of the current stage, the other of the source and the drain of the twenty-sixth pull-down sustaining thin film transistor is connected to the fifth scan signal of the current stage, and the other of the source and the drain of the twenty-seventh pull-down sustaining thin film transistor is connected to the sixth scan signal of the current stage;

[0043] The gates of the twenty-eighth pull-down maintenance thin film transistor and the twenty-ninth pull-down maintenance thin film transistor are both electrically connected to the fourth node, the source and the drain of the twenty-eighth pull-down maintenance thin film transistor and the twenty-ninth pull-down maintenance thin film transistor are both connected to the first reference low level signal, the other of the source and the drain of the twenty-eighth pull-down maintenance thin film transistor is electrically connected to the third node, the other of the source and the drain of the twenty-ninth pull-down maintenance thin film transistor is connected to the second stage transmission signal of the current stage, the thirtieth pull-down maintenance thin film transistor, the thirty-first pull-down maintenance thin film transistor and the The gates of the thirty-second pull-down maintaining thin film transistor are all electrically connected to the fourth node, the source and the drain of the thirtieth pull-down maintaining thin film transistor, the thirty-first pull-down maintaining thin film transistor and the thirty-second pull-down maintaining thin film transistor are all connected to the second reference low level signal, the other of the source and the drain of the thirtieth pull-down maintaining thin film transistor is connected to the fourth scan signal of this level, the other of the source and the drain of the thirty-first pull-down maintaining thin film transistor is connected to the fifth scan signal of this level, and the other of the source and the drain of the thirty-second pull-down maintaining thin film transistor is connected to the sixth scan signal of this level.

[0044] In the GOA driving circuit described in the present application, each level of the GOA circuit sharing unit further includes a first inverter module and a second inverter module; wherein,

[0045] The first inverter module is electrically connected to the first node and the second node, the first inverter module is connected to the first-stage transmission signal of the previous stage, the first scanning signal of the current stage, the fourth scanning signal of the current stage and the first low-frequency clock signal, and the first inverter module is used to invert the potential of the second node and the first node;

[0046] The second inverter module is electrically connected to the third node and the fourth node. The second inverter module is connected to the second-stage transmission signal of the previous level, the first scanning signal of the current level, the fourth scanning signal of the current level and the second low-frequency clock signal. The second inverter module is used to invert the potentials of the fourth node and the second node.

[0047] In the GOA driving circuit described in the present application, the first inverter module includes a first inverting thin film transistor, a second inverting thin film transistor, a third inverting thin film transistor, a fourth inverting thin film transistor, a fifth inverting thin film transistor and a sixth inverting thin film transistor, the gate of the first inverting thin film transistor is connected to the first low-frequency clock signal, one of the source and the drain of the first inverting thin film transistor is connected to the first low-frequency clock signal, the other of the source and the drain of the first inverting thin film transistor is electrically connected to the fifth node, the gate of the second inverting thin film transistor is electrically connected to the fifth node, one of the source and the drain of the second inverting thin film transistor is connected to the first low-frequency clock signal, the other of the source and the drain of the second inverting thin film transistor is electrically connected to the second node, the gate of the third inverting thin film transistor is connected to the first scan signal of the current stage, and one of the source and the drain of the third inverting thin film transistor is connected to the first The reference low level signal, the other of the source and the drain of the third inverting thin film transistor is electrically connected to the fifth node, the gate of the fourth inverting thin film transistor is connected to the first scanning signal of the current stage, one of the source and the drain of the fourth inverting thin film transistor is electrically connected to the second node, the other of the source and the drain of the fourth inverting thin film transistor is connected to the first reference low level signal, the gate of the fifth inverting thin film transistor is connected to the fourth scanning signal of the current stage, one of the source and the drain of the fifth inverting thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the fifth inverting thin film transistor is electrically connected to the fifth node, the gate of the sixth inverting thin film transistor is connected to the first stage transmission signal of the previous stage, one of the source and the drain of the sixth inverting thin film transistor is connected to the first reference low level signal, and the other of the source and the drain of the sixth inverting thin film transistor is electrically connected to the second node;

[0048] The second inverter module includes a seventh inversion thin film transistor, an eighth inversion thin film transistor, a ninth inversion thin film transistor, a tenth inversion thin film transistor, an eleventh inversion thin film transistor and a twelfth inversion thin film transistor, the gate of the seventh inversion thin film transistor is connected to the second low-frequency clock signal, one of the source and the drain of the seventh inversion thin film transistor is connected to the second low-frequency clock signal, the other of the source and the drain of the seventh inversion thin film transistor is electrically connected to the sixth node, the gate of the eighth inversion thin film transistor is electrically connected to the sixth node, one of the source and the drain of the eighth inversion thin film transistor is connected to the second low-frequency clock signal, the other of the source and the drain of the eighth inversion thin film transistor is electrically connected to the fourth node, the gate of the ninth inversion thin film transistor is connected to the first scan signal of the current stage, one of the source and the drain of the ninth inversion thin film transistor is connected to the first reference low level signal, the The other of the source and the drain of the ninth inverted thin film transistor is electrically connected to the sixth node, the gate of the tenth inverted thin film transistor is connected to the first scan signal of the current stage, one of the source and the drain of the tenth inverted thin film transistor is electrically connected to the fourth node, the other of the source and the drain of the tenth inverted thin film transistor is connected to the first reference low level signal, the gate of the eleventh inverted thin film transistor is connected to the fourth scan signal of the current stage, one of the source and the drain of the eleventh inverted thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the eleventh inverted thin film transistor is electrically connected to the sixth node, the gate of the twelfth inverted thin film transistor is connected to the second stage transmission signal of the previous stage, one of the source and the drain of the twelfth inverted thin film transistor is connected to the first reference low level signal, and the other of the source and the drain of the twelfth inverted thin film transistor is electrically connected to the fourth node.

[0049] In the GOA driving circuit described in the present application, each level of the GOA circuit sharing unit also includes a first reset module and a second reset module, the first reset module is electrically connected to the first node, the first reset module is connected to the reset signal and the first reference low level signal, the first reset module is used to reset the potential of the first node to the potential of the first reference low level signal under the control of the reset signal, the second reset module is electrically connected to the third node, the second reset module is connected to the reset signal and the first reference low level signal, and the second reset module is used to reset the potential of the third node to the potential of the first reference low level signal under the control of the reset signal.

[0050] In the GOA driving circuit described in the present application, the first reset module includes a first reset thin film transistor, a gate of the first reset thin film transistor is connected to the reset signal, one of a source and a drain of the first reset thin film transistor is electrically connected to the first node, and the other of the source and the drain of the first reset thin film transistor is connected to the first reference low level signal;

[0051] The second reset module includes a second reset thin film transistor, a gate of the second reset thin film transistor is connected to the reset signal, one of the source and the drain of the second reset thin film transistor is electrically connected to the third node, and the other of the source and the drain of the second reset thin film transistor is connected to the first reference low level signal.

[0052] An embodiment of the present application further provides a display panel, comprising a display area and a non-display area arranged around the display area, wherein the non-display area is integrated with the GOA circuit described above.

[0053] In the GOA circuit and display panel provided in the embodiment of the present application, a three-gate drive architecture is adopted, wherein the GOA circuit includes a multi-level GOA circuit sharing unit, in each level of the GOA sharing unit, the first scan signal of this level, the second scan signal of this level and the third scan signal of this level share a pull-up control module, a level transmission module and a pull-down module, the fourth scan signal of this level, the fifth scan signal of this level and the sixth scan signal of this level share a pull-up control module, a level transmission module and a pull-down module, the first scan signal of this level, the second scan signal of this level, the third scan signal of this level, the fourth scan signal of this level, the fifth scan signal of this level and the sixth scan signal of this level share a pull-down maintenance module, thereby reducing the number of modules of the GOA circuit, further reducing the design space of the GOA circuit, which is beneficial to the narrow frame design of the display panel. In addition, since the design space of the GOA circuit is greatly reduced, the size of the key thin film transistor can be increased, such as the size of the output thin film transistor can be increased, thereby ensuring the thrust of the large-size high-definition narrow-frame liquid crystal display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0055] Figure 1 A schematic diagram of the structure of the GOA circuit provided in an embodiment of the present application.

[0056] Figure 2 This is a schematic structural diagram of a first implementation of a GOA unit in a GOA circuit provided in an embodiment of the present application.

[0057] Figure 3 This is a circuit diagram of a first implementation of a GOA unit in a GOA circuit provided in an embodiment of the present application.

[0058] Figure 4 A schematic structural diagram of a second implementation manner of a GOA unit in a GOA circuit provided in an embodiment of the present application.

[0059] Figure 5 A circuit diagram of a second implementation of a GOA unit in a GOA circuit provided in an embodiment of the present application.

[0060] Figure 6 This is a schematic structural diagram of a third implementation manner of a GOA unit in a GOA circuit provided in an embodiment of the present application.

[0061] Figure 7 This is a first circuit schematic diagram of a third implementation manner of a GOA unit in a GOA circuit provided in an embodiment of the present application.

[0062] Figure 8 A second circuit diagram of a third implementation manner of a GOA unit in a GOA circuit provided in an embodiment of the present application.

[0063] Fig. 9 This is a signal timing diagram of a GOA unit in the GOA circuit provided in an embodiment of the present application.

[0064] Fig.10 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0066] The transistors used in all embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present application, in order to distinguish the two poles of the transistor other than the gate, one of the poles is called the source and the other is called the drain. According to the form in the accompanying drawings, the middle end of the switching transistor is defined as the gate, the signal input end is the source, and the output end is the drain. In addition, the transistor used in the embodiments of the present application is an N-type transistor, wherein the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.

[0067] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of the GOA circuit provided in the embodiment of the present application. Figure 1 As shown, the GOA circuit provided in the embodiment of the present application includes multiple stages of cascaded GOA units. Figure 1 Take the cascaded N-1th level GOA unit, Nth level GOA unit and N+1th level GOA unit as an example.

[0068] When the Nth-level GOA unit is working, the scanning signal output by the Nth-level GOA unit is a high potential, which is used to turn on the transistor switch of each pixel in a row of the display panel and charge the pixel electrode in each pixel through the data signal; the Nth-level transmission signal is used to control the operation of the N+1th-level GOA unit; when the N+1th-level GOA unit is working, the scanning signal output by the N+1th-level GOA unit is a high potential, and the scanning signal output by the Nth-level GOA unit is a low potential.

[0069] See also Figure 2 , Figure 2 This is a schematic diagram of the structure of a first implementation of a GOA unit in a GOA circuit provided in an embodiment of the present application. Figure 2 As shown, the GOA unit includes: a first pull-up control module 101, a first output module 103, a first stage transmission module 102, a first pull-down module 104, a second pull-up control module 105, a second output module 106, a second stage transmission module 107, a second pull-down module 108, a pull-down maintaining module 109, a first inverter module 110, a second inverter module 111, a first reset module 112 and a second reset module 113.

[0070] Among them, the first pull-up control module 101 is connected to the previous level first-level transmission signal ST(n-4) and the reference high level signal VGH, and is electrically connected to the first node P. The first pull-up control module 101 is used to pull the potential of the first node P to the potential of the reference high level VGH under the control of the previous level first-level transmission signal ST(n-4).

[0071] Among them, the first output module 103 is connected to the first clock signal Ck(n), the second clock signal Ck(n+1) and the third clock signal Ck(n+2), and is electrically connected to the first node P. The first output module 103 is used to output the first scanning signal G(n) of this level, the second scanning signal G(n+1) of this level and the third scanning signal G(n+2) of this level under the potential control of the first node P.

[0072] The first-stage transmission module 102 receives the third clock signal Ck(n+2) and is electrically connected to the first node P. The first-stage transmission module 102 is used to output the first-stage transmission signal ST(n+2) of this stage under the potential control of the first node P.

[0073] Among them, the first pull-down module 104 is connected to the fourth scan signal G(n+9) of the next level, the first reference low-level signal VSSQ, the first-level transmission signal ST(n+2) of the current level, the first scan signal G(n) of the current level, the second scan signal G(n+1) of the current level and the third scan signal G(n+2) of the current level, and is electrically connected to the first node P. The first pull-down module 104 is used to pull down the first node P, the first-level transmission signal ST(n+2) of the current level, the first scan signal G(n) of the current level, the second scan signal G(n+1) of the current level and the third scan signal G(n+2) of the current level to the potential of the first reference low-level signal VSSQ under the control of the fourth scan signal G(n+9) of the next level.

[0074] Among them, the second pull-up control module 105 is connected to the previous level second-level transmission signal ST(n-1) and the reference high level signal VGH, and is electrically connected to the third node M. The second pull-up control module 105 is used to pull the potential of the third node M to the potential of the reference high level VGH under the control of the previous level second-level transmission signal ST(n-1).

[0075] Among them, the second output module 106 is connected to the fourth clock signal Ck(n+3), the fifth clock signal Ck(n+4) and the sixth clock signal Ck(n+5), and is electrically connected to the third node M. The second output module 106 is used to output the fourth scanning signal G(n+3), the fifth scanning signal G(n+4) and the sixth scanning signal G(n+5) of this level under the potential control of the third node M.

[0076] The second-stage transmission module 107 receives the sixth clock signal Ck(n+5) and is electrically connected to the third node M. The second-stage transmission module 107 is used to output the second-stage transmission signal ST(n+5) of this stage under the potential control of the third node M.

[0077] Among them, the second pull-down module 108 is connected to the first scanning signal G(n+12) of the next two levels, the first reference low-level signal VSSQ, the second-level transmission signal ST(n+5) of this level, the fourth scanning signal G(n+3) of this level, the fifth scanning signal G(n+4) of this level and the sixth scanning signal G(n+5) of this level, and is electrically connected to the third node M. The second pull-down module 108 is used to pull down the third node M, the second-level transmission signal ST(n+5) of this level, the fourth scanning signal G(n+3) of this level, the fifth scanning signal G(n+4) of this level and the sixth scanning signal G(n+5) of this level to the potential of the first reference low-level signal VSSQ under the control of the first scanning signal G(n+12) of the next two levels.

[0078] The pull-down maintaining module 109 is connected to the first reference low-level signal VSSQ and is electrically connected to the first node P, the second node Q, the third node M and the fourth node N. The pull-down maintaining module 109 is used to maintain the first node P, the third node M, the first-level transmission signal ST(n+2) of this level, the second-level transmission signal ST(n+5) of this level, the first scanning signal G(n) of this level, the second scanning signal G(n+1) of this level, the third scanning signal G(n+2) of this level, the fourth scanning signal G(n+3) of this level, the fifth scanning signal G(n+4) of this level and the fourth scanning signal G(n+5) of this level under the potential control of the second node Q. The sixth scan signal G(n+5) is at the potential of the first reference low-level signal VSSQ, and the pull-down maintaining module 109 is used to maintain the potential of the first node P, the third node M, the first-level transmission signal ST(n+2) of this level, the second-level transmission signal ST(n+5) of this level, the first scan signal G(n) of this level, the second scan signal G(n+1) of this level, the third scan signal G(n+2) of this level, the fourth scan signal G(n+3) of this level, the fifth scan signal G(n+4) of this level and the sixth scan signal G(n+5) of this level at the potential of the first reference low-level signal VSSQ under the potential control of the fourth node N.

[0079] Among them, the first inverter module 110 is electrically connected to the first node P and the second node Q. The first inverter module 110 is connected to the first-level transmission signal ST(n-4) of the previous level, the first scanning signal G(n) of this level, the fourth scanning signal G(n+3) of this level and the first low-frequency clock signal LC1. The first inverter module 110 is used to invert the potentials of the second node Q and the first node P.

[0080] Among them, the second inverter module 111 is electrically connected to the third node M and the fourth node N, the second inverter module 111 is connected to the second-level transmission signal ST(n-1) of the previous level, the first scanning signal G(n) of this level, the fourth scanning signal G(n+3) of this level and the second low-frequency clock signal LC2, and the second inverter module 111 is used to invert the potential of the fourth node N and the second node M.

[0081] Among them, the first reset module 112 is electrically connected to the first node P, the first reset module 112 is connected to the reset signal STV and the first reference low level signal VSSQ, and the first reset module 112 is used to reset the potential of the first node P to the potential of the first reference low level signal VSSQ under the control of the reset signal STV.

[0082] Among them, the second reset module 113 is electrically connected to the third node M, the second reset module 113 is connected to the reset signal STV and the first reference low level signal VSSQ, and the second reset module 113 is used to reset the potential of the third node M to the potential of the first reference low level signal VSSQ under the control of the reset signal STV.

[0083] The GOA circuit sharing unit further includes a first bootstrap capacitor Cst1, a second bootstrap capacitor Cst2, a third bootstrap capacitor Cst3, a fourth bootstrap capacitor Cst4, a fifth bootstrap capacitor Cst5 and a sixth bootstrap capacitor Cst6, one end of the first bootstrap capacitor Cst1 is electrically connected to the first node P, the other end of the first bootstrap capacitor Cst1 is electrically connected to the first scan signal G(n) of the current stage, one end of the second bootstrap capacitor Cst2 is electrically connected to the first node P, the other end of the second bootstrap capacitor Cst2 is electrically connected to the second scan signal G(n+1) of the current stage, and one end of the third bootstrap capacitor Cst3 is electrically connected to the first node P. At the first node P, the other end of the third bootstrap capacitor Cst3 is electrically connected to the third scan signal G(n+2) of this level, one end of the fourth bootstrap capacitor Cst4 is electrically connected to the third node M, the other end of the fourth bootstrap capacitor Cst4 is electrically connected to the fourth scan signal G(n+3) of this level, one end of the fifth bootstrap capacitor Cst5 is electrically connected to the third node M, the other end of the fifth bootstrap capacitor Cst5 is electrically connected to the fifth scan signal G(n+4) of this level, one end of the sixth bootstrap capacitor Cst6 is electrically connected to the first node M, and the other end of the sixth bootstrap capacitor Cst6 is electrically connected to the sixth scan signal G(n+5) of this level.

[0084] It should be noted that, in the GOA circuit provided in the embodiment of the present application, the first scan signal G(n), the second scan signal G(n+1) and the third scan signal G(n+2) of the present level share the first pull-up control module 101, the first transmission module 102 and the first pull-down module 104. The fourth scan signal G(n+3), the fifth scan signal G(n+4) and the sixth scan signal G(n+5) of the present level share the second pull-up control module 105, the second transmission module 107 and the second pull-down module 108. The first scan signal G(n), the second scan signal G(n+1), the third scan signal G(n+2), the fourth scan signal G(n+3), the fifth scan signal G(n+4) and the sixth scan signal G(n+5) of the present level share the pull-down maintenance module 109, thereby reducing the number of modules of the GOA circuit, further reducing the design space of the GOA circuit, and thus facilitating the narrow frame design of the display panel.

[0085] In addition, since the GOA circuit design space is greatly reduced, the size of key thin film transistors can be increased, for example, the size of output thin film transistors can be increased, thereby ensuring the thrust of large-size high-definition narrow-frame LCD display panels.

[0086] See also Figure 3 , Figure 3 Schematic diagram of a first implementation of a GOA unit in a GOA circuit provided in an embodiment of the present application. Figure 3 As shown, the first pull-up control module 101 includes a first pull-up thin film transistor T11, the gate of the first pull-up thin film transistor T11 is connected to the first-stage transmission signal ST(n-4) of the previous stage, one of the source and the drain of the first pull-up thin film transistor T11 is connected to the reference high level signal VGH, and the other of the source and the drain of the first pull-up thin film transistor T11 is electrically connected to the first node P;

[0087] Among them, the second pull-up control module 105 includes a second pull-up thin film transistor T12, the gate of the second pull-up thin film transistor T12 is connected to the second-stage transmission signal ST(n-1) of the previous stage, one of the source and the drain of the second pull-up thin film transistor T12 is connected to the reference high level signal VGH, and the other of the source and the drain of the second pull-up thin film transistor T12 is electrically connected to the third node M.

[0088] Among them, the first output module 103 includes a first output thin film transistor T21, a second output thin film transistor T22 and a third output thin film transistor T23, the gate of the first output thin film transistor T21 is connected to the first node P, one of the source and the drain of the first output thin film transistor T21 is connected to the first clock signal Ck(n), the other of the source and the drain of the first output thin film transistor T21 is connected to the first scan signal G(n) of this level, the gate of the second output thin film transistor T22 is connected to the first node P, one of the source and the drain of the second output thin film transistor T22 is connected to the second clock signal Ck(n+1), the other of the source and the drain of the second output thin film transistor T22 is connected to the second scan signal G(n+1) of this level, the gate of the third output thin film transistor T23 is connected to the first node P, one of the source and the drain of the third output thin film transistor T23 is connected to the third clock signal Ck(n+2), and the other of the source and the drain of the third output thin film transistor T23 is connected to the third scan signal G(n+2) of this level.

[0089] The second output module 106 includes a fourth output thin film transistor T24, a fifth output thin film transistor T25, and a sixth output thin film transistor T26. The gate of the fourth output thin film transistor T24 is electrically connected to the third node M. One of the source and the drain of the fourth output thin film transistor T24 is connected to the fourth clock signal Ck(n+3). The other of the source and the drain of the fourth output thin film transistor T24 is connected to the fourth scan signal G(n+3) of the current stage. The gate of the fifth output thin film transistor T25 is electrically connected to the third node M. , one of the source and the drain of the fifth output thin film transistor T25 is connected to the fifth clock signal Ck(n+4), the other of the source and the drain of the fifth output thin film transistor T25 is connected to the fifth scan signal G(n+4) of this level, the gate of the sixth output thin film transistor T26 is electrically connected to the third node M, one of the source and the drain of the sixth output thin film transistor T26 is connected to the sixth clock signal Ck(n+5), and the other of the source and the drain of the sixth output thin film transistor T26 is connected to the sixth scan signal G(n+5) of this level.

[0090] Among them, the first-level transmission module 102 includes a first-level transmission thin film transistor T31, the gate of the first-level transmission thin film transistor T31 is electrically connected to the first node P, one of the source and the drain of the first-level transmission thin film transistor T31 is connected to the third clock signal Ck(n+2), and the other of the source and the drain of the first-level transmission thin film transistor T31 is connected to the first-level transmission signal ST(n+2) of this level.

[0091] Among them, the second-level transmission module 107 includes a second-level transmission thin film transistor T32, the gate of the second-level transmission thin film transistor T32 is electrically connected to the third node M, one of the source and the drain of the second-level transmission thin film transistor T32 is connected to the sixth clock signal Ck(n+5), and the other of the source and the drain of the second-level transmission thin film transistor T32 is connected to the second-level transmission signal ST(n+5) of this level.

[0092] Among them, the first pull-down module 104 includes a first pull-down thin film transistor T41, the gate of the first pull-down thin film transistor T41 is connected to the fourth scan signal G(n+9) of the next level, one of the source and the drain of the first pull-down thin film transistor T41 is connected to the first reference low level signal VSSQ, the other of the source and the drain of the first pull-down thin film transistor T41 is electrically connected to the first node P, and the other of the source and the drain of the first pull-down thin film transistor T41 is connected to the first-level transmission signal ST(n+2) of this level, the first scan signal G(n) of this level, the second scan signal G(n+1) of this level and the third scan signal G(n+2) of this level.

[0093] Among them, the second pull-down module 108 includes a second pull-down thin film transistor T42, the gate of the second pull-down thin film transistor T42 is connected to the first scanning signal G(n+12) of the next second level, one of the source and the drain of the second pull-down thin film transistor T42 is connected to the first reference low level signal VSSQ, the other of the source and the drain of the second pull-down thin film transistor T42 is electrically connected to the third node M, and the other of the source and the drain of the second pull-down thin film transistor T42 is connected to the second-level transmission signal ST(n+5) of this level, the fourth scanning signal G(n+3) of this level, the fifth scanning signal G(n+4) of this level and the sixth scanning signal G(n+5) of this level.

[0094] The pull-down maintenance module 109 includes a first pull-down maintenance thin film transistor T51, a second pull-down maintenance thin film transistor T52, a third pull-down maintenance thin film transistor T53 and a fourth pull-down maintenance thin film transistor T54; the gate of the first pull-down maintenance thin film transistor T51 is electrically connected to the second node Q, one of the source and the drain of the first pull-down maintenance thin film transistor T51 is connected to the first reference low level signal VSSQ, the other of the source and the drain of the first pull-down maintenance thin film transistor T51 is electrically connected to the first node P, and the other of the source and the drain of the first pull-down maintenance thin film transistor T51 is connected to the first level transmission signal ST(n+2) of the current level, the first scan signal of the current level, and the first level transmission signal ST(n+2) of the current level. signal G(n), the second scan signal G(n+1) of this level and the third scan signal G(n+2) of this level; the gate of the second pull-down maintaining thin film transistor T52 is electrically connected to the fourth node N, one of the source and the drain of the second pull-down maintaining thin film transistor T52 is connected to the first reference low level signal VSSQ, the other of the source and the drain of the second pull-down maintaining thin film transistor T52 is electrically connected to the first node P, and the other of the source and the drain of the second pull-down maintaining thin film transistor T52 is connected to the first level transmission signal ST(n+2), the first scan signal G(n) of this level, the second scan signal G(n+1) of this level and the third scan signal G(n+2) of this level. The gate of the third pull-down sustaining thin film transistor T53 is electrically connected to the second node Q, one of the source and the drain of the third pull-down sustaining thin film transistor T53 is connected to the first reference low level signal VSSQ, the other of the source and the drain of the third pull-down sustaining thin film transistor T53 is electrically connected to the third node M, and the other of the source and the drain of the third pull-down sustaining thin film transistor T53 is connected to the second-stage transmission signal ST(n+5) of the current stage, the fourth scan signal G(n+3) of the current stage, the fifth scan signal G(n+4) of the current stage, and the sixth scan signal G(n+5) of the current stage; The gate of the fourth pull-down maintaining thin film transistor T54 is electrically connected to the fourth node N, one of the source and the drain of the fourth pull-down maintaining thin film transistor T54 is connected to the first reference low level signal VSSQ, the other of the source and the drain of the fourth pull-down maintaining thin film transistor T54 is electrically connected to the third node M, and the other of the source and the drain of the fourth pull-down maintaining thin film transistor T54 is connected to the second-level transmission signal ST(n+5) of this level, the fourth scan signal G(n+3) of this level, the fifth scan signal G(n+4) of this level and the sixth scan signal G(n+5) of this level.

[0095] The first inverter module 110 includes a first inversion thin film transistor T61 , a second inversion thin film transistor T62 , a third inversion thin film transistor T63 , a fourth inversion thin film transistor T64 , a fifth inversion thin film transistor T65 and a sixth inversion thin film transistor T66 . The gate of the first inversion thin film transistor T61 is connected to the first low-frequency clock signal LC1, one of the source and the drain of the first inversion thin film transistor T61 is connected to the first low-frequency clock signal LC1, the other of the source and the drain of the first inversion thin film transistor T61 is electrically connected to the fifth node S, the gate of the second inversion thin film transistor T62 is electrically connected to the fifth node S, one of the source and the drain of the second inversion thin film transistor T62 is connected to the first low-frequency clock signal LC1, the other of the source and the drain of the second inversion thin film transistor T62 is electrically connected to the second node Q, the gate of the third inversion thin film transistor T63 is connected to the first scan signal G(n) of this stage, one of the source and the drain of the third inversion thin film transistor T63 is connected to the first reference low-level signal VSSQ, the other of the source and the drain of the third inversion thin film transistor T63 is electrically connected to the fifth node S, and the gate of the fourth inversion thin film transistor T62 is electrically connected to the fifth node S. The gate of the body transistor T64 is connected to the first scan signal G(n) of the current stage, one of the source and the drain of the fourth inverting thin film transistor T64 is electrically connected to the second node Q, the other of the source and the drain of the fourth inverting thin film transistor T64 is connected to the first reference low level signal VSSQ, the gate of the fifth inverting thin film transistor T65 is connected to the fourth scan signal G(n+3) of the current stage, one of the source and the drain of the fifth inverting thin film transistor T65 is connected to the first reference low level signal VSSQ, the other of the source and the drain of the fifth inverting thin film transistor T65 is electrically connected to the fifth node S, the gate of the sixth inverting thin film transistor T66 is connected to the first stage transfer signal ST(n-4) of the previous stage, one of the source and the drain of the sixth inverting thin film transistor T66 is connected to the first reference low level signal VSSQ, and the other of the source and the drain of the sixth inverting thin film transistor T66 is electrically connected to the second node Q.

[0096] The second inverter module 111 includes a seventh inverting thin film transistor T67, an eighth inverting thin film transistor T68, a ninth inverting thin film transistor T69, a tenth inverting thin film transistor T610, an eleventh inverting thin film transistor T611 and a twelfth inverting thin film transistor T612, the gate of the seventh inverting thin film transistor T67 is connected to the second low-frequency clock signal LC2, one of the source and the drain of the seventh inverting thin film transistor T67 is connected to the second low-frequency clock signal LC2, and the source and drain of the seventh inverting thin film transistor T67 are connected to the second low-frequency clock signal LC2. The other of the drains is electrically connected to the sixth node T, the gate of the eighth inverting thin film transistor T68 is electrically connected to the sixth node T, one of the source and the drain of the eighth inverting thin film transistor T68 is connected to the second low-frequency clock signal LC2, the other of the source and the drain of the eighth inverting thin film transistor T68 is electrically connected to the fourth node N, the gate of the ninth inverting thin film transistor T69 is connected to the first scan signal G(n) of the current stage, and one of the source and the drain of the ninth inverting thin film transistor T69 is connected to the first reference low-level signal VSSQ , the other of the source and the drain of the ninth inverting thin film transistor T69 is electrically connected to the sixth node T, the gate of the tenth inverting thin film transistor T610 is connected to the first scan signal G(n) of the current stage, one of the source and the drain of the tenth inverting thin film transistor T610 is electrically connected to the fourth node N, the other of the source and the drain of the tenth inverting thin film transistor T610 is connected to the first reference low level signal VSSQ, the gate of the eleventh inverting thin film transistor T611 is connected to the fourth scan signal G(n+3) of the current stage, One of the source and the drain of the transistor T611 is connected to the first reference low-level signal VSSQ, the other of the source and the drain of the eleventh inversion thin film transistor T611 is electrically connected to the sixth node T, the gate of the twelfth inversion thin film transistor T612 is connected to the previous level second-level transmission signal ST(n-1), one of the source and the drain of the twelfth inversion thin film transistor T612 is connected to the first reference low-level signal VSSQ, and the other of the source and the drain of the twelfth inversion thin film transistor T612 is electrically connected to the fourth node N.

[0097] Among them, the first reset module 112 includes a first reset thin film transistor T71, the gate of the first reset thin film transistor T71 is connected to the reset signal STV, one of the source and the drain of the first reset thin film transistor T71 is electrically connected to the first node P, and the other of the source and the drain of the first reset thin film transistor T71 is connected to the first reference low level signal VSSQ.

[0098] Among them, the second reset module 113 includes a second reset thin film transistor T72, the gate of the second reset thin film transistor T72 is connected to the reset signal STV, one of the source and the drain of the second reset thin film transistor T72 is electrically connected to the third node M, and the other of the source and the drain of the second reset thin film transistor T72 is connected to the first reference low level signal VSSQ.

[0099] For details, please refer to Figure 4 , Figure 4 This is a schematic diagram of a second implementation of a GOA unit in a GOA circuit provided in an embodiment of the present application. Figure 4 As shown, the first pull-down module 104 is also connected to the next-level second-level transmission signal ST(n+11), and the first pull-down module 104 is also used to connect the potential of the first node P, the first-level transmission signal ST(n+2) of this level, the first scan signal G(n) of this level, the second scan signal G(n+1) of this level, and the third scan signal G(n+2) of this level to the first reference low-level signal VSSQ under the control of the next-level second-level transmission signal ST(n+2).

[0100] The second pull-down module 108 is also connected to the first-level transmission signal ST(n+14) of the next two levels. The second pull-down module 108 is also used to pull down the third node M, the second-level transmission signal ST(n+5) of this level, the fourth scan signal G(n+3) of this level, the fifth scan signal G(n+4) of this level and the sixth scan signal G(n+5) of this level to the potential of the first reference low-level signal VSSQ under the control of the first-level transmission signal ST(n+14) of the next two levels.

[0101] For details, please refer to Figure 5 , Figure 5 Schematic diagram of a second implementation of a GOA unit in a GOA circuit provided in an embodiment of the present application. Figure 5 As shown, the first pull-down module 104 also includes a third pull-down thin film transistor T43, the gate of the third pull-down thin film transistor T43 is connected to the second-level transmission signal ST(n+11) of the next level, one of the source and the drain of the third pull-down thin film transistor T43 is connected to the first reference low-level signal VSSQ, the other of the source and the drain of the third pull-down thin film transistor T43 is electrically connected to the first node P, and the other of the source and the drain of the third pull-down thin film transistor T43 is connected to the first-level transmission signal ST(n+2), the first scan signal G(n), the second scan signal G(n+1) and the third scan signal G(n+2) of the current level.

[0102] The second pull-down module 108 includes a fourth pull-down thin film transistor T44, the gate of the fourth pull-down thin film transistor T44 is connected to the first-level transmission signal ST(n+14) of the next two levels, one of the source and the drain of the fourth pull-down thin film transistor T44 is connected to the first reference low-level signal VSSQ, the other of the source and the drain of the fourth pull-down thin film transistor T44 is electrically connected to the third node M, and the other of the source and the drain of the fourth pull-down thin film transistor T44 is connected to the second-level transmission signal ST(n+5) of this level, the fourth scan signal G(n+3) of this level, the fifth scan signal G(n+4) of this level and the sixth scan signal G(n+5) of this level.

[0103] The first pull-down module 104 provided in the embodiment of the present application uses an asymmetric first pull-down thin film transistor T41 and a third pull-down thin film transistor T43 to pull down the first node P, the first-stage transmission signal ST(n+2), the first scan signal G(n), the second scan signal G(n+1) and the third scan signal G(n+2) to the potential of the first reference low-level signal VSSQ. The second pull-down module 108 provided in the embodiment of the present application uses an asymmetric second pull-down thin film transistor T42 and a fourth pull-down thin film transistor T44 to pull down the third node M, the second-stage transmission signal ST(n+5), the fourth scan signal G(n+3), the fifth scan signal G(n+4) and the sixth scan signal G(n+5) to the potential of the first reference low-level signal VSSQ.

[0104] It should be noted that, since the GOA circuit provided in the embodiment of the present application is applied to a three-gate drive architecture product, and the three-gate drive architecture product is generally a large-size high-definition narrow-frame display panel, the load capacity required when pulling down is also large. First, the pull-down module provided in the embodiment of the present application uses two asymmetric pull-down thin-film transistors to perform the pull-down operation, thereby avoiding the technical problem of insufficient load. Second, when the pull-down module provided in the embodiment of the present application uses two asymmetric pull-down thin-film transistors to perform the pull-down, two pull-down processes are required, thereby avoiding the occurrence of certain nodes and signals that are not pulled down to the preset value. Third, the pull-down module provided in the embodiment of the present application uses two asymmetric pull-down thin-film transistors to perform the pull-down operation. Compared with the pull-down module using one pull-down thin-film transistor to perform the pull-down operation, the size of the pull-down thin-film transistor can be set smaller, which is conducive to the design of a narrow frame of the display panel.

[0105] For details, please refer to Figure 6 , Figure 6 This is a schematic diagram of the structure of a third implementation of a GOA unit in a GOA circuit provided in an embodiment of the present application. Figure 6As shown, the pull-down maintaining module 109 is also connected to the second reference low level signal VSSG. The pull-down maintaining module is used to maintain the potential of the first node P, the first-level transmission signal ST(n+2) of the current level, the third node M and the second-level transmission signal ST(n+5) of the current level under the potential control of the second node Q, and is used to maintain the first scanning signal G(n) of the current level, the second scanning signal G(n+1) of the current level, the third scanning signal G(n+2) of the current level, the fourth scanning signal G(n+3) of the current level, the fifth scanning signal G(n+4) of the current level and the sixth scanning signal G(n+5) of the current level under the potential control of the second node Q. The potential of the first reference low level signal VSSQ is used to maintain the potential of the first node P, the first-level transmission signal ST(n+2) of this level, the third node M and the second-level transmission signal ST(n+5) of this level at the second reference low level VSSG under the potential control of the fourth node N, and is used to maintain the potential of the first scanning signal G(n) of this level, the second scanning signal G(n+1) of this level, the third scanning signal G(n+2) of this level, the fourth scanning signal G(n+3) of this level, the fifth scanning signal G(n+4) of this level and the sixth scanning signal G(n+5) of this level at the first reference low level signal VSSQ under the potential control of the fourth node N.

[0106] It should be noted that the pull-down maintenance module provided in the embodiment of the present application is connected to the first reference low level signal VSSQ and the second reference low level signal VSSG, so as to reduce the load of the GOA circuit and further reduce the power consumption of the GOA circuit.

[0107] For details, please refer to Figure 7 , Figure 7 The first circuit diagram of the third implementation of a GOA unit in the GOA circuit provided in the embodiment of the present application. Figure 7 As shown, the pull-down maintaining module 109 includes a fifth pull-down maintaining thin film transistor T55, a sixth pull-down maintaining thin film transistor T56, a seventh pull-down maintaining thin film transistor T57, an eighth pull-down maintaining thin film transistor T58, a ninth pull-down maintaining thin film transistor T59, a tenth pull-down maintaining thin film transistor T510, an eleventh pull-down maintaining thin film transistor T511 and a twelfth pull-down maintaining thin film transistor T512.

[0108] Among them, the gate of the fifth pull-down maintenance thin film transistor T55 is electrically connected to the second node Q, one of the source and the drain of the fifth pull-down maintenance thin film transistor T55 is connected to the first reference low level signal VSSQ, the other of the source and the drain of the fifth pull-down maintenance thin film transistor T55 is electrically connected to the first node P, and the other of the source and the drain of the fifth pull-down maintenance thin film transistor T55 is connected to the first-level transmission signal ST(n+2) of this level, the gate of the sixth pull-down maintenance thin film transistor T56 is electrically connected to the second node Q, one of the source and the drain of the sixth pull-down maintenance thin film transistor T56 is connected to the second reference low level signal VSSG, and the other of the source and the drain of the sixth pull-down maintenance thin film transistor T56 is connected to the first scan signal G(n) of this level, the second scan signal G(n+1) of this level and the third scan signal G(n+2) of this level.

[0109] Among them, the gate of the seventh pull-down maintenance thin film transistor T57 is electrically connected to the fourth node N, one of the source and the drain of the seventh pull-down maintenance thin film transistor T57 is connected to the first reference low level signal VSSQ, the other of the source and the drain of the seventh pull-down maintenance thin film transistor T57 is electrically connected to the first node P, and the other of the source and the drain of the seventh pull-down maintenance thin film transistor T57 is connected to the first-level transmission signal ST(n+2) of this level, the gate of the eighth pull-down maintenance thin film transistor T58 is electrically connected to the fourth node N, one of the source and the drain of the eighth pull-down maintenance thin film transistor T58 is connected to the second reference low level signal VSSG, and the other of the source and the drain of the eighth pull-down maintenance thin film transistor T58 is connected to the first scan signal G(n) of this level, the second scan signal G(n+1) of this level and the third scan signal G(n+2) of this level.

[0110] Among them, the gate of the ninth pull-down maintenance thin film transistor T59 is electrically connected to the second node Q, one of the source and the drain of the ninth pull-down maintenance thin film transistor T59 is connected to the first reference low level signal VSSQ, the other of the source and the drain of the ninth pull-down maintenance thin film transistor T59 is electrically connected to the third node M, and the other of the source and the drain of the ninth pull-down maintenance thin film transistor T59 is connected to the second level transmission signal ST(n+5) of this level; the gate of the tenth pull-down maintenance thin film transistor T510 is electrically connected to the second node Q, one of the source and the drain of the tenth pull-down maintenance thin film transistor T510 is connected to the second reference low level signal VSSG, and the other of the source and the drain of the tenth pull-down maintenance thin film transistor T510 is connected to the fourth scan signal G(n+3) of this level, the fifth scan signal G(n+4) of this level and the sixth scan signal G(n+5) of this level.

[0111] Among them, the gate of the eleventh pull-down maintenance thin film transistor T511 is electrically connected to the fourth node N, one of the source and the drain of the eleventh pull-down maintenance thin film transistor T511 is connected to the first reference low level signal VSSQ, the other of the source and the drain of the eleventh pull-down maintenance thin film transistor T511 is electrically connected to the third node M, and the other of the source and the drain of the eleventh pull-down maintenance thin film transistor T511 is connected to the second level transmission signal ST(n+5) of this level; the gate of the twelfth pull-down maintenance thin film transistor T512 is electrically connected to the fourth node N, one of the source and the drain of the twelfth pull-down maintenance thin film transistor T512 is connected to the second reference low level signal VSSG, and the other of the source and the drain of the twelfth pull-down maintenance thin film transistor T512 is connected to the fourth scan signal G(n+3) of this level, the fifth scan signal G(n+4) of this level and the sixth scan signal G(n+5) of this level.

[0112] It should be noted that a pull-down sustaining thin film transistor provided in the embodiment of the present application can maintain the low potential of multiple signals or nodes, thereby reducing the number of pull-down sustaining thin film transistors, and further reducing the space occupied by the GOA circuit, which is beneficial to the design of a narrow frame of the display panel.

[0113] For details, please refer to Figure 8 , Figure 8 This is a second circuit diagram of a third implementation of a GOA unit in a GOA circuit provided in an embodiment of the present application. Figure 8 As shown, the pull-down maintaining module 109 includes a thirteenth pull-down maintaining thin film transistor T513, a fourteenth pull-down maintaining thin film transistor T514, a fifteenth pull-down maintaining thin film transistor T515, a sixteenth pull-down maintaining thin film transistor T516, a seventeenth pull-down maintaining thin film transistor T517, an eighteenth pull-down maintaining thin film transistor T518, a nineteenth pull-down maintaining thin film transistor T519, a twentieth pull-down maintaining thin film transistor T520, a twenty-first pull-down maintaining thin film transistor T521, and a twenty-second pull-down maintaining thin film transistor T523. 522, the twenty-third pull-down maintaining thin film transistor T523, the twenty-fourth pull-down maintaining thin film transistor T524, the twenty-fifth pull-down maintaining thin film transistor T525, the twenty-sixth pull-down maintaining thin film transistor T526, the twenty-seventh pull-down maintaining thin film transistor T527, the twenty-eighth pull-down maintaining thin film transistor T528, the twenty-ninth pull-down maintaining thin film transistor T529, the thirtieth pull-down maintaining thin film transistor T530, the thirty-first pull-down maintaining thin film transistor T531, and the thirty-second pull-down maintaining thin film transistor T532.

[0114] Among them, the gates of the thirteenth pull-down maintenance thin film transistor T513 and the fourteenth pull-down maintenance thin film transistor T514 are electrically connected to the second node Q, the source and the drain of the thirteenth pull-down maintenance thin film transistor T513 and the fourteenth pull-down maintenance thin film transistor T514 are both connected to the first reference low level signal VSSQ, the other of the source and the drain of the thirteenth pull-down maintenance thin film transistor T513 is electrically connected to the first node P, the other of the source and the drain of the fourteenth pull-down maintenance thin film transistor T514 is connected to the first stage transmission signal ST(n+2) of this stage, the fifteenth pull-down maintenance thin film transistor T515, the sixteenth pull-down maintenance thin film transistor T516 and the seventeenth pull-down maintenance thin film transistor T517 are connected to the first stage transmission signal ST(n+2) of this stage, The gates of the pull-down sustaining thin film transistors T517 are electrically connected to the second node Q, one of the source and the drain of the fifteenth pull-down sustaining thin film transistor T515, the sixteenth pull-down sustaining thin film transistor T516 and the seventeenth pull-down sustaining thin film transistor T517 are all connected to the second reference low level signal VSSG, the other of the source and the drain of the fifteenth pull-down sustaining thin film transistor T515 is connected to the first scan signal G(n) of the current stage, the other of the source and the drain of the sixteenth pull-down sustaining thin film transistor T516 is connected to the second scan signal G(n+1) of the current stage, and the other of the source and the drain of the seventeenth pull-down sustaining thin film transistor T517 is connected to the third scan signal G(n+2) of the current stage;

[0115] Among them, the gates of the eighteenth pull-down maintenance thin film transistor T518 and the nineteenth pull-down maintenance thin film transistor T519 are electrically connected to the fourth node N, the source and the drain of the eighteenth pull-down maintenance thin film transistor T518 and the nineteenth pull-down maintenance thin film transistor T519 are both connected to the first reference low level signal VSSQ, the other of the source and the drain of the eighteenth pull-down maintenance thin film transistor T518 is electrically connected to the first node P, the other of the source and the drain of the nineteenth pull-down maintenance thin film transistor T519 is connected to the first stage transmission signal ST(n+2) of this stage, the twentieth pull-down maintenance thin film transistor T520, the twenty-first pull-down maintenance thin film transistor T521 and the twenty-second pull-down maintenance thin film transistor T521 are connected to the first stage transmission signal ST(n+2) of this stage, The gates of the maintaining thin film transistors T522 are electrically connected to the fourth node N, one of the source and the drain of the twentieth pull-down maintaining thin film transistor T520, the twenty-first pull-down maintaining thin film transistor T521 and the twenty-second pull-down maintaining thin film transistor T522 are connected to the second reference low-level signal VSSG, the other of the source and the drain of the twentieth pull-down maintaining thin film transistor T520 is connected to the first scan signal G(n) of this level, the other of the source and the drain of the twenty-first pull-down maintaining thin film transistor T521 is connected to the second scan signal G(n+1) of this level, and the other of the source and the drain of the twenty-second pull-down maintaining thin film transistor T522 is connected to the third scan signal G(n+2) of this level.

[0116] Among them, the gates of the twenty-third pull-down maintenance thin film transistor T523 and the twenty-fourth pull-down maintenance thin film transistor T524 are electrically connected to the second node Q, the source and the drain of the twenty-third pull-down maintenance thin film transistor T523 and the twenty-fourth pull-down maintenance thin film transistor T524 are both connected to the first reference low level signal VSSQ, the other of the source and the drain of the twenty-third pull-down maintenance thin film transistor T523 is electrically connected to the third node M, the other of the source and the drain of the twenty-fourth pull-down maintenance thin film transistor T524 is connected to the second stage transmission signal ST(n+5) of this stage, the twenty-fifth pull-down maintenance thin film transistor T525, the twenty-sixth pull-down maintenance thin film transistor T526 and the twenty-seventh pull-down maintenance thin film transistor T527 are connected to the second stage transmission signal ST(n+5) of this stage, and the second stage transmission signal ST(n+5) of the twenty-fifth pull-down maintenance thin film transistor T525, the twenty-sixth pull-down maintenance thin film transistor T526 and the twenty-seventh pull-down maintenance thin film transistor T527 are connected to the second stage transmission signal ST(n+5) of this stage. The gates of the pull-down sustaining thin film transistors T527 are all electrically connected to the second node Q, one of the source and the drain of the twenty-fifth pull-down sustaining thin film transistor T525, the twenty-sixth pull-down sustaining thin film transistor T526, and the twenty-seventh pull-down sustaining thin film transistor T527 is connected to the second reference low level signal VSSG, the other of the source and the drain of the twenty-fifth pull-down sustaining thin film transistor T525 is connected to the fourth scan signal G(n+3) of the current stage, the other of the source and the drain of the twenty-sixth pull-down sustaining thin film transistor T526 is connected to the fifth scan signal G(n+4) of the current stage, and the other of the source and the drain of the twenty-seventh pull-down sustaining thin film transistor T527 is connected to the sixth scan signal G(n+5) of the current stage;

[0117] Among them, the gates of the twenty-eighth pull-down maintenance thin film transistor T528 and the twenty-ninth pull-down maintenance thin film transistor T529 are electrically connected to the fourth node N, one of the source and the drain of the twenty-eighth pull-down maintenance thin film transistor T528 and the twenty-ninth pull-down maintenance thin film transistor T529 is connected to the first reference low level signal VSSQ, the other of the source and the drain of the twenty-eighth pull-down maintenance thin film transistor T528 is electrically connected to the third node M, the other of the source and the drain of the twenty-ninth pull-down maintenance thin film transistor T529 is connected to the second-stage transmission signal ST(n+5) of the current stage, the thirtieth pull-down maintenance thin film transistor T530, the thirty-first pull-down maintenance thin film transistor T531 and the thirty-second pull-down maintenance thin film transistor T530 are connected to the third node M, the second-stage transmission signal ST(n+5) of the current stage is connected to the 30th pull-down maintenance thin film transistor T530, the thirty-first pull-down maintenance thin film transistor T531 and the thirty-second pull-down maintenance thin film transistor T531 are connected to the first reference low level signal VSSQ ... The gates of the pull-down maintaining thin film transistors T532 are electrically connected to the fourth node N, and one of the source and the drain of the 30th pull-down maintaining thin film transistor T530, the 31st pull-down maintaining thin film transistor T531 and the 32nd pull-down maintaining thin film transistor T532 is connected to the second reference low level signal VSSG, the other of the source and the drain of the 30th pull-down maintaining thin film transistor T530 is connected to the fourth scan signal G(n+3) of this level, the other of the source and the drain of the 31st pull-down maintaining thin film transistor T531 is connected to the fifth scan signal G(n+4) of this level, and the other of the source and the drain of the 32nd pull-down maintaining thin film transistor T532 is connected to the sixth scan signal G(n+5) of this level.

[0118] Among them, each pull-down maintenance thin film transistor provided in the embodiment of the present application is connected to a node or a signal, and is used to maintain a low potential of a node or a signal. It should be noted that through the above setting, it can be ensured that all nodes and signals maintain the required low potential, avoid the phenomenon of signal confusion, and help improve the stability of the GOA circuit.

[0119] For details, please refer to Fig. 9 , Fig. 9 This is a signal timing diagram of a GOA unit in the GOA circuit provided in an embodiment of the present application.

[0120] Among them, in the first clock cycle t1, the first pull-up control module 101 pulls up the potential of the first node P, and the second pull-up control module 105 pulls up the potential of the third node M, so that the first output module 103 and the second output module 106 are turned on. Because at this time the first clock signal Ck(n), the second clock signal Ck(n+1), the third clock signal Ck(n+2), the fourth clock signal Ck(n+3), the fifth clock signal Ck(n+4) and the sixth clock signal Ck(n+5) are all low potentials, so at this time the first scanning signal G(n) of this level, the second scanning signal G(n+1) of this level, the third scanning signal G(n+2) of this level, the fourth scanning signal G(n+3) of this level, the fifth scanning signal G(n+4) of this level and the sixth scanning signal G(n+5) of this level are also low potentials.

[0121] In the second clock cycle t2, the first pull-up control module 101 and the second pull-up control module 105 are turned off, the first node P and the third node M continue to maintain a high potential, and the first clock signal Ck(n) is at a high potential, so the first scan signal G(n) of this stage is at a high potential. In this stage, the first scan signal G(n) of this stage is at a high potential, so that the scan line corresponding to the first scan signal G(n) of this stage is charged, and a row of pixels corresponding to the scan line corresponding to the first scan signal G(n) of this stage is turned on to increase the scan signal, and the row of pixels is lit.

[0122] At the same time, in this stage, since the first scanning signal G(n) of this stage is at a high potential, under the action of the first bootstrap capacitor Cst1, the potential of the first node P is further increased to ensure that the output first scanning signal G(n) of this stage is at a high potential.

[0123] In the second clock cycle t2, the first pull-up control module 101 and the second pull-up control module 105 are turned off, the first node P and the third node M continue to maintain a high potential, and the first clock signal Ck(n) is at a high potential, so the first scan signal G(n) of this stage is at a high potential. In this stage, the first scan signal G(n) of this stage is at a high potential, so that the scan line corresponding to the first scan signal G(n) of this stage is charged, and a row of pixels corresponding to the scan line corresponding to the first scan signal G(n) of this stage is turned on to increase the scan signal, and the row of pixels is lit.

[0124] At the same time, in this stage, since the first scanning signal G(n) of this stage is at a high potential, under the action of the first bootstrap capacitor Cst1, the potential of the first node P is further increased to ensure that the output first scanning signal G(n) of this stage is at a high potential.

[0125] In the second clock cycle t2, the third clock cycle t3, the fourth clock cycle t4, the fifth clock cycle t5, the sixth clock cycle t6 and the seventh clock cycle t7, the first clock signal Ck(n), the second clock signal Ck(n+1), the third clock signal Ck(n+2), the fourth clock signal Ck(n+3), the fifth clock signal Ck(n+4) and the sixth clock signal Ck(n+5) sequentially output a high level signal of one cycle. Among them,

[0126] In the second clock cycle t2, the first pull-up control module 101 and the second pull-up control module 105 are turned off, the first node P and the third node M continue to maintain a high potential, and the first clock signal Ck(n) is at a high potential, so the first scanning signal G(n) of this stage is at a high potential. In this stage, the first scanning signal G(n) of this stage is at a high potential, so that the scanning line corresponding to the first scanning signal G(n) of this stage is charged, and a row of pixels that need the scanning line corresponding to the first scanning signal G(n) of this stage to provide a scanning signal is turned on, and the row of pixels is lit.

[0127] At the same time, in this stage, since the first scanning signal G(n) of this stage is at a high potential, under the action of the first bootstrap capacitor Cst1, the potential of the first node P is further increased to ensure that the output first scanning signal G(n) of this stage is at a high potential.

[0128] In the third clock cycle t3, the first pull-up control module 101 and the second pull-up control module 105 are turned off, the first node P and the third node M continue to maintain a high potential, and the second clock signal Ck(n+1) is at a high potential, so the second scanning signal G(n+1) of this stage is at a high potential. In this stage, the second scanning signal G(n+1) of this stage is at a high potential, so that the scanning line corresponding to the second scanning signal G(n+1) of this stage is charged, and a row of pixels that need the scanning line corresponding to the second scanning signal G(n+1) of this stage to provide a scanning signal is turned on, and the row of pixels is lit.

[0129] At the same time, in this stage, since the second scanning signal G(n+1) of this level is at a high potential, under the action of the second bootstrap capacitor Cst2, the potential of the first node P is further increased to ensure that the output second scanning signal G(n+1) of this level is at a high potential.

[0130] In the fourth clock cycle t4, the first pull-up control module 101 and the second pull-up control module 105 are turned off, the first node P and the third node M continue to maintain a high potential, and the third clock signal Ck(n+2) is at a high potential, so the third scan signal G(n+2) of this stage is at a high potential. In this stage, the third scan signal G(n+2) of this stage is at a high potential, so that the scan line corresponding to the third scan signal G(n+2) of this stage is charged, and a row of pixels that need the scan line corresponding to the third scan signal G(n+2) of this stage to provide a scan signal is turned on, and the row of pixels is lit.

[0131] At the same time, in this stage, since the third scanning signal G(n+2) of this level is at a high potential, under the action of the third bootstrap capacitor Cst3, the potential of the first node P is further increased to ensure that the output third scanning signal G(n+2) of this level is at a high potential.

[0132] In the fifth clock cycle t5, the first pull-up control module 101 and the second pull-up control module 105 are turned off, the first node P and the third node M continue to maintain a high potential, and the fourth clock signal Ck(n+3) is at a high potential, so the fourth scanning signal G(n+3) of this stage is at a high potential. In this stage, the fourth scanning signal G(n+3) of this stage is at a high potential, so that the scanning line corresponding to the fourth scanning signal G(n+3) of this stage is charged, and a row of pixels that need the scanning line corresponding to the fourth scanning signal G(n+3) of this stage to provide a scanning signal is turned on, and the row of pixels is lit.

[0133] At the same time, in this stage, since the fourth scanning signal G(n+3) of this stage is at a high potential, under the action of the fourth bootstrap capacitor Cst4, the potential of the third node M is further pulled up to ensure that the output fourth scanning signal G(n+3) of this stage is at a high potential. Since the first scanning signal G(n) of this stage, the second scanning signal G(n+1) of this stage and the third scanning signal G(n+2) of this stage are all at low potentials, the potential of the first node P drops to a normal high potential and cannot be further pulled up.

[0134] In the sixth clock cycle t6, the first pull-up control module 101 and the second pull-up control module 105 are turned off, the first node P and the third node M continue to maintain a high potential, and at this time the fifth clock signal Ck(n+4) is at a high potential, so the fifth scanning signal G(n+4) of this stage is at a high potential. In this stage, the fifth scanning signal G(n+4) of this stage is at a high potential, so that the scanning line corresponding to the fifth scanning signal G(n+4) of this stage is charged, and a row of pixels that need the scanning line corresponding to the fifth scanning signal G(n+4) of this stage to provide a scanning signal is turned on, and the row of pixels is lit.

[0135] At the same time, in this stage, since the fifth scanning signal G(n+4) of this stage is at a high potential, under the action of the fifth bootstrap capacitor Cst5, the potential of the third node M is further pulled up to ensure that the output fifth scanning signal G(n+4) of this stage is at a high potential. Since the first scanning signal G(n) of this stage, the second scanning signal G(n+1) of this stage and the third scanning signal G(n+2) of this stage are all at low potentials, the potential of the first node P drops to a normal high potential and cannot be further pulled up.

[0136] In the seventh clock cycle t7, the first pull-up control module 101 and the second pull-up control module 105 are turned off, the first node P and the third node M continue to maintain a high potential, and at this time the sixth clock signal Ck(n+5) is at a high potential, so the sixth scanning signal G(n+5) of this stage is at a high potential. In this stage, the sixth scanning signal G(n+5) of this stage is at a high potential, so that the scanning line corresponding to the sixth scanning signal G(n+5) of this stage is charged, and a row of pixels that need the scanning line corresponding to the sixth scanning signal G(n+5) of this stage to provide a scanning signal is turned on, and the row of pixels is lit.

[0137] At the same time, in this stage, since the sixth scanning signal G(n+5) of this stage is at a high potential, under the action of the sixth bootstrap capacitor Cst6, the potential of the third node M is further pulled up to ensure that the output sixth scanning signal G(n+5) of this stage is at a high potential. Since the first scanning signal G(n) of this stage, the second scanning signal G(n+1) of this stage and the third scanning signal G(n+2) of this stage are all at low potentials, the potential of the first node P drops to a normal high potential and cannot be further pulled up.

[0138] In the eighth clock cycle t8, the first pull-down module 104 and the second pull-down module 108 successively pull down the potentials of the first node P and the third node M to a low potential, and when the potentials of the first node P and the third node M are at a low potential, due to the existence of the first inverter module 110 and the second inverter module 111, the potentials of the second node Q and the fourth node M become high potentials, so that the pull-down maintaining module 109 maintains the potentials of the first node P, the third node M, the first scan signal G(n) of this level, the second scan signal G(n+1) of this level, the third scan signal G(n+2) of this level, the fourth scan signal G(n+3) of this level, the fifth scan signal G(n+4) of this level and the sixth scan signal G(n+5) of this level at a low potential.

[0139] In the GOA circuit provided in the embodiment of the present application, a three-gate drive architecture is adopted, wherein the GOA circuit includes a multi-level GOA circuit sharing unit, in each level of the GOA sharing unit, the first scan signal of this level, the second scan signal of this level and the third scan signal of this level share a pull-up control module, a level transmission module and a pull-down module, the fourth scan signal of this level, the fifth scan signal of this level and the sixth scan signal of this level share a pull-up control module, a level transmission module and a pull-down module, the first scan signal of this level, the second scan signal of this level, the third scan signal of this level, the fourth scan signal of this level, the fifth scan signal of this level and the sixth scan signal of this level share a pull-down control module, thereby reducing the number of modules of the GOA circuit, further reducing the design space of the GOA circuit, thereby facilitating the narrow frame design of the display panel. In addition, since the design space of the GOA circuit is greatly reduced, the size of the key thin film transistor can be increased, such as the size of the output thin film transistor can be increased, thereby ensuring the thrust of the large-size high-definition narrow-frame liquid crystal display panel.

[0140] See also Fig.10 , Fig.10 This is a schematic diagram of the structure of the display panel provided in the embodiment of the present application. Fig.10 As shown, the display panel includes a display area and a GOA circuit 200 integrated on the edge of the display area 100; wherein the structure and principle of the GOA circuit 200 are similar to those of the above-mentioned GOA circuit, which will not be repeated here.

[0141] The above are only embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

[0142] See also Fig.10 , Fig.10The present invention also provides a display panel 100, which includes a display area 100a and a non-display area 100b arranged around the display area 100a, wherein the non-display area 100b is integrated with a GOA circuit 10, and the GOA circuit 10 can be specifically described in the above description, which will not be described in detail here.

[0143] A GOA circuit and a display panel provided in an embodiment of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application, and does not limit the patent scope of the present invention. All equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, or directly or indirectly used in other related technical fields, are similarly included in the patent protection scope of the present invention; for technical personnel in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A GOA circuit, characterized in that: include: A cascaded multi-stage GOA circuit sharing unit, each stage of the GOA circuit sharing unit includes: a first pull-up control module, a first stage transmission module, a first output module, a first pull-down module, a second pull-up control module, a second stage transmission module, a second output module, a second pull-down module and a pull-down maintaining module; The first pull-up control module is connected to the first-stage transmission signal of the previous stage and the reference high-level signal, and is electrically connected to the first node. The first pull-up control module is used to pull the potential of the first node to the potential of the reference high-level under the control of the first-stage transmission signal of the previous stage. The first output module receives the first clock signal, the second clock signal and the third clock signal and is electrically connected to the first node. The first output module is used to output the first scanning signal of the current level, the second scanning signal of the current level and the third scanning signal of the current level under the potential control of the first node. The first-stage transmission module is connected to the third clock signal and is electrically connected to the first node. The first-stage transmission module is used to output the first-stage transmission signal of the current stage under the potential control of the first node. The first pull-down module is connected to the fourth scan signal of the next level, the first reference low-level signal, the first-level transmission signal of the current level, the first scan signal of the current level, the second scan signal of the current level, and the third scan signal of the current level, and is electrically connected to the first node. The first pull-down module is used to pull down the potential of the first node, the first-level transmission signal of the current level, the first scan signal of the current level, the second scan signal of the current level, and the third scan signal of the current level to the first reference low-level signal under the control of the fourth scan signal of the next level. The second pull-up control module is connected to the second-stage transmission signal of the previous stage and the reference high-level signal, and is electrically connected to the third node. The second pull-up control module is used to pull the potential of the third node to the potential of the reference high-level under the control of the second-stage transmission signal of the previous stage. The second output module receives the fourth clock signal, the fifth clock signal and the sixth clock signal and is electrically connected to the third node. The second output module is used to output the fourth scanning signal of the current level, the fifth scanning signal of the current level and the sixth scanning signal of the current level under the potential control of the third node. The second-stage transmission module is connected to the sixth clock signal and is electrically connected to the third node. The second-stage transmission module is used to output the second-stage transmission signal of the current stage under the potential control of the third node. The second pull-down module is connected to the first scanning signal of the next second level, the first reference low-level signal, the second-level transmission signal of the current level, the fourth scanning signal of the current level, the fifth scanning signal of the current level, and the sixth scanning signal of the current level, and is electrically connected to the third node. The second pull-down module is used to pull down the potential of the third node, the second-level transmission signal of the current level, the fourth scanning signal of the current level, the fifth scanning signal of the current level, and the sixth scanning signal of the current level to the potential of the first reference low-level signal under the control of the first scanning signal of the next second level. The pull-down maintaining module is connected to the first reference low-level signal and is electrically connected to the first node, the second node, the third node and the fourth node. The pull-down maintaining module is used to maintain the potential of the first node, the third node, the first-level transmission signal of the current level, the second-level transmission signal of the current level, the first scan signal of the current level, the second scan signal of the current level, the third scan signal of the current level, the fourth scan signal of the current level, the fifth scan signal of the current level and the sixth scan signal of the current level at the potential of the first reference low-level signal under the potential control of the second node. The pull-down maintaining module is used to maintain the potential of the first node, the third node, the first-level transmission signal of the current level, the second-level transmission signal of the current level, the first scan signal of the current level, the second scan signal of the current level, the third scan signal of the current level, the fourth scan signal of the current level, the fifth scan signal of the current level and the sixth scan signal of the current level at the potential of the first reference low-level signal under the potential control of the fourth node; wherein, The pulse periods of the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are the same, and the falling edge of each clock signal is aligned with the rising edge of the next adjacent clock signal; The first pull-down module includes a first pull-down thin film transistor, a gate of the first pull-down thin film transistor is connected to the fourth scan signal of the next stage, one of the source and the drain of the first pull-down thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the first pull-down thin film transistor is electrically connected to the first node, and the other of the source and the drain of the first pull-down thin film transistor is connected to the first stage transmission signal of the current stage, the first scan signal of the current stage, the second scan signal of the current stage, and the third scan signal of the current stage; The second pull-down module comprises a second pull-down thin film transistor, a gate of the second pull-down thin film transistor is connected to the second-level first scan signal, one of the source and the drain of the second pull-down thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the second pull-down thin film transistor is electrically connected to the third node, and the other of the source and the drain of the second pull-down thin film transistor is connected to the second-level transmission signal of the current level, the fourth scan signal of the current level, the fifth scan signal of the current level and the sixth scan signal of the current level; The first pull-down module is also connected to the next-level second-level transmission signal, and the first pull-down module is also used to pull down the potential of the first node, the first-level transmission signal of the current level, the first scanning signal of the current level, the second scanning signal of the current level, and the third scanning signal of the current level to the first reference low-level signal under the control of the next-level second-level transmission signal; The second pull-down module is also connected to the next second level first level transmission signal, and the first pull-down module is also used to pull down the third node, the second level transmission signal of the current level, the fourth scanning signal of the current level, the fifth scanning signal of the current level, and the sixth scanning signal of the current level to the potential of the first reference low level signal under the control of the next second level first level transmission signal; The first pull-down module further includes a third pull-down thin film transistor, a gate of the third pull-down thin film transistor is connected to the second-level transmission signal of the next level, one of the source and the drain of the third pull-down thin film transistor is connected to the first reference low-level signal, the other of the source and the drain of the third pull-down thin film transistor is electrically connected to the first node, and the other of the source and the drain of the third pull-down thin film transistor is connected to the first-level transmission signal of the current level, the first scanning signal of the current level, the second scanning signal of the current level, and the third scanning signal of the current level; The second pull-down module includes a fourth pull-down thin film transistor, a gate of the fourth pull-down thin film transistor is connected to the first-level transmission signal of the next two levels, one of the source and the drain of the fourth pull-down thin film transistor is connected to the first reference low-level signal, the other of the source and the drain of the fourth pull-down thin film transistor is electrically connected to the third node, and the other of the source and the drain of the fourth pull-down thin film transistor is connected to the second-level transmission signal of the current level, the fourth scanning signal of the current level, the fifth scanning signal of the current level, and the sixth scanning signal of the current level.

2. The GOA circuit according to claim 1, characterized in that: Each level of the GOA circuit sharing unit further includes a first bootstrap capacitor, a second bootstrap capacitor, a third bootstrap capacitor, a fourth bootstrap capacitor, a fifth bootstrap capacitor and a sixth bootstrap capacitor, one end of the first bootstrap capacitor is electrically connected to the first node, and the other end of the first bootstrap capacitor is electrically connected to the first scan signal of the current level, one end of the second bootstrap capacitor is electrically connected to the first node, and the other end of the second bootstrap capacitor is electrically connected to the second scan signal of the current level, one end of the third bootstrap capacitor is electrically connected to the first node, and the other end of the third bootstrap capacitor is electrically connected to the third scan signal of the current level, one end of the fourth bootstrap capacitor is electrically connected to the third node, and the other end of the fourth bootstrap capacitor is electrically connected to the fourth scan signal of the current level, one end of the fifth bootstrap capacitor is electrically connected to the third node, and the other end of the fifth bootstrap capacitor is electrically connected to the fifth scan signal of the current level, one end of the sixth bootstrap capacitor is electrically connected to the first node, and the other end of the sixth bootstrap capacitor is electrically connected to the sixth scan signal of the current level.

3. The GOA circuit according to claim 1, characterized in that: The first pull-up control module comprises a first pull-up thin film transistor, a gate of the first pull-up thin film transistor is connected to the first-stage transmission signal of the previous stage, one of the source and the drain of the first pull-up thin film transistor is connected to the reference high-level signal, and the other of the source and the drain of the first pull-up thin film transistor is electrically connected to the first node; The second pull-up control module includes a second pull-up thin film transistor, a gate of the second pull-up thin film transistor is connected to the second-stage transmission signal of the previous stage, one of the source and the drain of the second pull-up thin film transistor is connected to the reference high-level signal, and the other of the source and the drain of the second pull-up thin film transistor is electrically connected to the third node.

4. The GOA circuit according to claim 1, characterized in that: The first output module includes a first output thin film transistor, a second output thin film transistor and a third output thin film transistor, the gate of the first output thin film transistor is connected to the first node, one of the source and the drain of the first output thin film transistor is connected to the first clock signal, the other of the source and the drain of the first output thin film transistor is connected to the first scan signal of the current stage, the gate of the second output thin film transistor is connected to the first node, one of the source and the drain of the second output thin film transistor is connected to the second clock signal, the other of the source and the drain of the second output thin film transistor is connected to the second scan signal of the current stage, the gate of the third output thin film transistor is connected to the first node, one of the source and the drain of the third output thin film transistor is connected to the third clock signal, and the other of the source and the drain of the third output thin film transistor is connected to the third scan signal of the current stage; The second output module includes a fourth output thin film transistor, a fifth output thin film transistor and a sixth output thin film transistor, the gate of the fourth output thin film transistor is electrically connected to the third node, one of the source and the drain of the fourth output thin film transistor is connected to the fourth clock signal, and the other of the source and the drain of the fourth output thin film transistor is connected to the fourth scan signal of this level, the gate of the fifth output thin film transistor is electrically connected to the third node, one of the source and the drain of the fifth output thin film transistor is connected to the fifth clock signal, and the other of the source and the drain of the fifth output thin film transistor is connected to the fifth scan signal of this level, the gate of the sixth output thin film transistor is electrically connected to the third node, one of the source and the drain of the sixth output thin film transistor is connected to the sixth clock signal, and the other of the source and the drain of the sixth output thin film transistor is connected to the sixth scan signal of this level.

5. The GOA circuit according to claim 1, characterized in that: The first-stage transmission module includes a first-stage transmission thin film transistor, the gate of the first-stage transmission thin film transistor is electrically connected to the first node, one of the source and the drain of the first-stage transmission thin film transistor is connected to the third clock signal, and the other of the source and the drain of the first-stage transmission thin film transistor is connected to the first-stage transmission signal of the current stage; The second-level transmission module includes a second-level transmission thin film transistor, the gate of the second-level transmission thin film transistor is electrically connected to the third node, one of the source and the drain of the second-level transmission thin film transistor is connected to the sixth clock signal, and the other of the source and the drain of the second-level transmission thin film transistor is connected to the second-level transmission signal of this level.

6. The GOA circuit according to claim 1, characterized in that: The pull-down maintenance module includes a first pull-down maintenance thin film transistor, a second pull-down maintenance thin film transistor, a third pull-down maintenance thin film transistor and a fourth pull-down maintenance thin film transistor; wherein, The gate of the first pull-down sustaining thin film transistor is electrically connected to the second node, one of the source and the drain of the first pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the first pull-down sustaining thin film transistor is electrically connected to the first node, and the other of the source and the drain of the first pull-down sustaining thin film transistor is connected to the first level transmission signal of the current stage, the first scan signal of the current stage, the second scan signal of the current stage, and the third scan signal of the current stage; the gate of the second pull-down sustaining thin film transistor is electrically connected to the fourth node, one of the source and the drain of the second pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the second pull-down sustaining thin film transistor is electrically connected to the first node, and the other of the source and the drain of the second pull-down sustaining thin film transistor is connected to the first level transmission signal of the current stage, the first scan signal of the current stage, the second scan signal of the current stage, and the third scan signal of the current stage; The gate of the third pull-down sustaining thin film transistor is electrically connected to the second node, one of the source and the drain of the third pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the third pull-down sustaining thin film transistor is electrically connected to the third node, and the other of the source and the drain of the third pull-down sustaining thin film transistor is connected to the second level transmission signal of this level, the fourth scan signal of this level, the fifth scan signal of this level and the sixth scan signal of this level; the gate of the fourth pull-down sustaining thin film transistor is electrically connected to the fourth node, one of the source and the drain of the fourth pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the fourth pull-down sustaining thin film transistor is electrically connected to the third node, and the other of the source and the drain of the fourth pull-down sustaining thin film transistor is connected to the second level transmission signal of this level, the fourth scan signal of this level, the fifth scan signal of this level and the sixth scan signal of this level.

7. The GOA circuit according to claim 1, characterized in that: The pull-down maintaining module is also connected to a second reference low-level signal. The pull-down maintaining module is used to maintain the potential of the first node, the first-level transmission signal of the current level, the third node and the second-level transmission signal of the current level at the second reference low level under the potential control of the second node, and is used to maintain the potential of the first scan signal of the current level, the second scan signal of the current level, the third scan signal of the current level, the fourth scan signal of the current level, the fifth scan signal of the current level and the sixth scan signal of the current level at the first reference low-level signal under the potential control of the second node, and is used to maintain the potential of the first node, the first-level transmission signal of the current level, the third node and the second-level transmission signal of the current level at the second reference low level under the potential control of the fourth node, and is used to maintain the potential of the first scan signal of the current level, the second scan signal of the current level, the third scan signal of the current level, the fourth scan signal of the current level, the fifth scan signal of the current level and the sixth scan signal of the current level at the first reference low-level signal under the potential control of the fourth node.

8. The GOA circuit according to claim 7, characterized in that: The pull-down maintenance module includes a fifth pull-down maintenance thin film transistor, a sixth pull-down maintenance thin film transistor, a seventh pull-down maintenance thin film transistor, an eighth pull-down maintenance thin film transistor, a ninth pull-down maintenance thin film transistor, a tenth pull-down maintenance thin film transistor, an eleventh pull-down maintenance thin film transistor and a twelfth pull-down maintenance thin film transistor; wherein, The gate of the fifth pull-down sustaining thin film transistor is electrically connected to the second node, one of the source and the drain of the fifth pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the fifth pull-down sustaining thin film transistor is electrically connected to the first node, and the other of the source and the drain of the fifth pull-down sustaining thin film transistor is connected to the first stage transmission signal of the current level, the gate of the sixth pull-down sustaining thin film transistor is electrically connected to the second node, one of the source and the drain of the sixth pull-down sustaining thin film transistor is connected to the second reference low level signal, and the other of the source and the drain of the sixth pull-down sustaining thin film transistor is connected to the first scan signal of the current level, the second scan signal of the current level, and the third scan signal of the current level; The gate of the seventh pull-down sustaining thin film transistor is electrically connected to the fourth node, one of the source and the drain of the seventh pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the seventh pull-down sustaining thin film transistor is electrically connected to the first node, and the other of the source and the drain of the seventh pull-down sustaining thin film transistor is connected to the first level transmission signal of the current stage, the gate of the eighth pull-down sustaining thin film transistor is electrically connected to the fourth node, one of the source and the drain of the eighth pull-down sustaining thin film transistor is connected to the second reference low level signal, and the other of the source and the drain of the eighth pull-down sustaining thin film transistor is connected to the first scan signal of the current stage, the second scan signal of the current stage, and the third scan signal of the current stage; The gate of the ninth pull-down sustaining thin film transistor is electrically connected to the second node, one of the source and the drain of the ninth pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the ninth pull-down sustaining thin film transistor is electrically connected to the third node, and the other of the source and the drain of the ninth pull-down sustaining thin film transistor is connected to the second level transmission signal of the current stage; the gate of the tenth pull-down sustaining thin film transistor is electrically connected to the second node, one of the source and the drain of the tenth pull-down sustaining thin film transistor is connected to the second reference low level signal, and the other of the source and the drain of the tenth pull-down sustaining thin film transistor is connected to the fourth scan signal of the current stage, the fifth scan signal of the current stage, and the sixth scan signal of the current stage; The gate of the eleventh pull-down maintenance thin film transistor is electrically connected to the fourth node, one of the source and the drain of the eleventh pull-down maintenance thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the eleventh pull-down maintenance thin film transistor is electrically connected to the third node, and the other of the source and the drain of the eleventh pull-down maintenance thin film transistor is connected to the second level transmission signal of the current level; the gate of the twelfth pull-down maintenance thin film transistor is electrically connected to the fourth node, one of the source and the drain of the twelfth pull-down maintenance thin film transistor is connected to the second reference low level signal, and the other of the source and the drain of the twelfth pull-down maintenance thin film transistor is connected to the fourth scan signal of the current level, the fifth scan signal of the current level, and the sixth scan signal of the current level.

9. The GOA circuit according to claim 7, characterized in that: The pull-down maintaining module includes a thirteenth pull-down maintaining thin film transistor, a fourteenth pull-down maintaining thin film transistor, a fifteenth pull-down maintaining thin film transistor, a sixteenth pull-down maintaining thin film transistor, a seventeenth pull-down maintaining thin film transistor, an eighteenth pull-down maintaining thin film transistor, a nineteenth pull-down maintaining thin film transistor, a twentieth pull-down maintaining thin film transistor, a twenty-first pull-down maintaining thin film transistor, a twenty-second pull-down maintaining thin film transistor, a twenty-third pull-down maintaining thin film transistor, a twenty-fourth pull-down maintaining thin film transistor, a twenty-fifth pull-down maintaining thin film transistor, a twenty-sixth pull-down maintaining thin film transistor, a twenty-seventh pull-down maintaining thin film transistor, a twenty-eighth pull-down maintaining thin film transistor, a twenty-ninth pull-down maintaining thin film transistor, a thirtieth pull-down maintaining thin film transistor, a thirty-first pull-down maintaining thin film transistor, and a thirty-second pull-down maintaining thin film transistor; wherein, The gates of the thirteenth pull-down sustaining thin film transistor and the fourteenth pull-down sustaining thin film transistor are electrically connected to the second node, the source and the drain of the thirteenth pull-down sustaining thin film transistor and the fourteenth pull-down sustaining thin film transistor are both connected to the first reference low level signal, the other of the source and the drain of the thirteenth pull-down sustaining thin film transistor is electrically connected to the first node, the other of the source and the drain of the fourteenth pull-down sustaining thin film transistor is connected to the first stage transmission signal of the current stage, the fifteenth pull-down sustaining thin film transistor, the sixteenth pull-down sustaining thin film transistor and the The gates of the seventeenth pull-down sustaining thin film transistors are all electrically connected to the second node, the source and the drain of the fifteenth pull-down sustaining thin film transistor, the sixteenth pull-down sustaining thin film transistor and the seventeenth pull-down sustaining thin film transistor are all connected to the second reference low level signal, the other of the source and the drain of the fifteenth pull-down sustaining thin film transistor is connected to the first scan signal of the current stage, the other of the source and the drain of the sixteenth pull-down sustaining thin film transistor is connected to the second scan signal of the current stage, and the other of the source and the drain of the seventeenth pull-down sustaining thin film transistor is connected to the third scan signal of the current stage; The gates of the eighteenth pull-down sustaining thin film transistor and the nineteenth pull-down sustaining thin film transistor are electrically connected to the fourth node, one of the source and the drain of the eighteenth pull-down sustaining thin film transistor and the nineteenth pull-down sustaining thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the eighteenth pull-down sustaining thin film transistor is electrically connected to the first node, the other of the source and the drain of the nineteenth pull-down sustaining thin film transistor is connected to the first stage transmission signal of the current stage, the 20th pull-down sustaining thin film transistor, the 21st pull-down sustaining thin film transistor and the 20th The gates of the second pull-down sustaining thin film transistors are electrically connected to the fourth node, one of the source and the drain of the 20th pull-down sustaining thin film transistor, the 21st pull-down sustaining thin film transistor and the 22nd pull-down sustaining thin film transistor is connected to the second reference low level signal, the other of the source and the drain of the 20th pull-down sustaining thin film transistor is connected to the first scan signal of the current stage, the other of the source and the drain of the 21st pull-down sustaining thin film transistor is connected to the second scan signal of the current stage, and the other of the source and the drain of the 22nd pull-down sustaining thin film transistor is connected to the third scan signal of the current stage; The gates of the twenty-third pull-down sustaining thin film transistor and the twenty-fourth pull-down sustaining thin film transistor are both electrically connected to the second node, the source and the drain of the twenty-third pull-down sustaining thin film transistor and the twenty-fourth pull-down sustaining thin film transistor are both connected to the first reference low level signal, the other of the source and the drain of the twenty-third pull-down sustaining thin film transistor is electrically connected to the third node, the other of the source and the drain of the twenty-fourth pull-down sustaining thin film transistor is connected to the second stage transmission signal of the current stage, the twenty-fifth pull-down sustaining thin film transistor, the twenty-sixth pull-down sustaining thin film transistor and the The gates of the twenty-seventh pull-down sustaining thin film transistors are all electrically connected to the second node, the source and the drain of the twenty-fifth pull-down sustaining thin film transistor, the twenty-sixth pull-down sustaining thin film transistor, and the twenty-seventh pull-down sustaining thin film transistor are all connected to the second reference low level signal, the other of the source and the drain of the twenty-fifth pull-down sustaining thin film transistor is connected to the fourth scan signal of the current stage, the other of the source and the drain of the twenty-sixth pull-down sustaining thin film transistor is connected to the fifth scan signal of the current stage, and the other of the source and the drain of the twenty-seventh pull-down sustaining thin film transistor is connected to the sixth scan signal of the current stage; The gates of the twenty-eighth pull-down maintenance thin film transistor and the twenty-ninth pull-down maintenance thin film transistor are both electrically connected to the fourth node, the source and the drain of the twenty-eighth pull-down maintenance thin film transistor and the twenty-ninth pull-down maintenance thin film transistor are both connected to the first reference low level signal, the other of the source and the drain of the twenty-eighth pull-down maintenance thin film transistor is electrically connected to the third node, the other of the source and the drain of the twenty-ninth pull-down maintenance thin film transistor is connected to the second stage transmission signal of the current stage, the thirtieth pull-down maintenance thin film transistor, the thirty-first pull-down maintenance thin film transistor and the The gates of the thirty-second pull-down maintaining thin film transistor are all electrically connected to the fourth node, the source and the drain of the thirtieth pull-down maintaining thin film transistor, the thirty-first pull-down maintaining thin film transistor and the thirty-second pull-down maintaining thin film transistor are all connected to the second reference low level signal, the other of the source and the drain of the thirtieth pull-down maintaining thin film transistor is connected to the fourth scan signal of this level, the other of the source and the drain of the thirty-first pull-down maintaining thin film transistor is connected to the fifth scan signal of this level, and the other of the source and the drain of the thirty-second pull-down maintaining thin film transistor is connected to the sixth scan signal of this level.

10. The GOA circuit according to claim 1, characterized in that: Each level of the GOA circuit sharing unit further includes a first inverter module and a second inverter module; wherein, The first inverter module is electrically connected to the first node and the second node, the first inverter module is connected to the first-stage transmission signal of the previous stage, the first scanning signal of the current stage, the fourth scanning signal of the current stage and the first low-frequency clock signal, and the first inverter module is used to invert the potential of the second node and the first node; The second inverter module is electrically connected to the third node and the fourth node. The second inverter module is connected to the second-stage transmission signal of the previous level, the first scanning signal of the current level, the fourth scanning signal of the current level and the second low-frequency clock signal. The second inverter module is used to invert the potentials of the fourth node and the second node.

11. The GOA circuit according to claim 10, characterized in that: The first inverter module includes a first inverting thin film transistor, a second inverting thin film transistor, a third inverting thin film transistor, a fourth inverting thin film transistor, a fifth inverting thin film transistor and a sixth inverting thin film transistor, the gate of the first inverting thin film transistor is connected to the first low-frequency clock signal, one of the source and the drain of the first inverting thin film transistor is connected to the first low-frequency clock signal, the other of the source and the drain of the first inverting thin film transistor is electrically connected to a fifth node, the gate of the second inverting thin film transistor is electrically connected to the fifth node, one of the source and the drain of the second inverting thin film transistor is connected to the first low-frequency clock signal, the other of the source and the drain of the second inverting thin film transistor is electrically connected to the second node, the gate of the third inverting thin film transistor is connected to the first scanning signal of the current stage, and one of the source and the drain of the third inverting thin film transistor is connected to the first reference low level signal, The other of the source and the drain of the third inverting thin film transistor is electrically connected to the fifth node, the gate of the fourth inverting thin film transistor is connected to the first scanning signal of the current stage, one of the source and the drain of the fourth inverting thin film transistor is electrically connected to the second node, the other of the source and the drain of the fourth inverting thin film transistor is connected to the first reference low level signal, the gate of the fifth inverting thin film transistor is connected to the fourth scanning signal of the current stage, one of the source and the drain of the fifth inverting thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the fifth inverting thin film transistor is electrically connected to the fifth node, the gate of the sixth inverting thin film transistor is connected to the first stage transmission signal of the previous stage, one of the source and the drain of the sixth inverting thin film transistor is connected to the first reference low level signal, and the other of the source and the drain of the sixth inverting thin film transistor is electrically connected to the second node; The second inverter module includes a seventh inversion thin film transistor, an eighth inversion thin film transistor, a ninth inversion thin film transistor, a tenth inversion thin film transistor, an eleventh inversion thin film transistor and a twelfth inversion thin film transistor, the gate of the seventh inversion thin film transistor is connected to the second low-frequency clock signal, one of the source and the drain of the seventh inversion thin film transistor is connected to the second low-frequency clock signal, the other of the source and the drain of the seventh inversion thin film transistor is electrically connected to the sixth node, the gate of the eighth inversion thin film transistor is electrically connected to the sixth node, one of the source and the drain of the eighth inversion thin film transistor is connected to the second low-frequency clock signal, the other of the source and the drain of the eighth inversion thin film transistor is electrically connected to the fourth node, the gate of the ninth inversion thin film transistor is connected to the first scan signal of the current stage, one of the source and the drain of the ninth inversion thin film transistor is connected to the first reference low level signal, the The other of the source and the drain of the ninth inverted thin film transistor is electrically connected to the sixth node, the gate of the tenth inverted thin film transistor is connected to the first scan signal of the current stage, one of the source and the drain of the tenth inverted thin film transistor is electrically connected to the fourth node, the other of the source and the drain of the tenth inverted thin film transistor is connected to the first reference low level signal, the gate of the eleventh inverted thin film transistor is connected to the fourth scan signal of the current stage, one of the source and the drain of the eleventh inverted thin film transistor is connected to the first reference low level signal, the other of the source and the drain of the eleventh inverted thin film transistor is electrically connected to the sixth node, the gate of the twelfth inverted thin film transistor is connected to the second stage transmission signal of the previous stage, one of the source and the drain of the twelfth inverted thin film transistor is connected to the first reference low level signal, and the other of the source and the drain of the twelfth inverted thin film transistor is electrically connected to the fourth node.

12. The GOA circuit according to claim 1, characterized in that: Each level of the GOA circuit sharing unit also includes a first reset module and a second reset module, the first reset module is electrically connected to the first node, the first reset module is connected to the reset signal and the first reference low level signal, the first reset module is used to reset the potential of the first node to the potential of the first reference low level signal under the control of the reset signal, the second reset module is electrically connected to the third node, the second reset module is connected to the reset signal and the first reference low level signal, and the second reset module is used to reset the potential of the third node to the potential of the first reference low level signal under the control of the reset signal.

13. The GOA circuit according to claim 12, characterized in that: The first reset module comprises a first reset thin film transistor, a gate of the first reset thin film transistor is connected to the reset signal, one of a source and a drain of the first reset thin film transistor is electrically connected to the first node, and the other of a source and a drain of the first reset thin film transistor is connected to the first reference low level signal; The second reset module includes a second reset thin film transistor, a gate of the second reset thin film transistor is connected to the reset signal, one of the source and the drain of the second reset thin film transistor is electrically connected to the third node, and the other of the source and the drain of the second reset thin film transistor is connected to the first reference low level signal.

14. A display panel, characterized in that: The display panel comprises a display area and a non-display area arranged around the display area, wherein the non-display area is integrated with the GOA circuit according to any one of claims 1 to 13.

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