Display modules and electronic terminals

Abstract

The present invention provides a display module and an electronic terminal, comprising a panel having a display area and a non-display area and a gate control chip, wherein a gate driving circuit is provided in the non-display area, and a first output pin and a second output pin of the gate control chip are electrically connected to the gate driving circuit, wherein the gate control chip in the present invention is used to control the second output pin to output a second signal when a first signal output by the first output pin is abnormal, and to control the first output pin not to output the first signal, so as to improve the reliability of the gate driving circuit, thereby improving the yield of the display module.

Description

Technical Field

[0001] The present invention relates to the field of display technology, in particular to the field of display panel manufacturing technology, and specifically to a display module and an electronic terminal. Background Art

[0002] GOA (Gate Driver on Array) technology is conducive to the design of narrow bezels of display screens and has therefore been widely used.

[0003] Among them, the GOA circuit located on the array substrate needs to be electrically connected to multiple traces to load the GOA control signal. However, there are a large number of circuits and electronic devices on the array substrate, which causes the multiple traces transmitting the GOA control signal to be too close to each other. Due to reasons such as the process, short circuits may occur between the multiple traces transmitting the GOA control signal, causing the GOA circuit to work abnormally, resulting in the display panel being scrapped and reducing the yield of the display panel.

[0004] Therefore, it is necessary to provide a display panel and an electronic terminal that can reduce the risk of abnormal operation of the GOA circuit. Summary of the Invention

[0005] Embodiments of the present invention provide a display module and an electronic terminal to solve the existing technical problem of a high risk of abnormal operation of the GOA circuit caused by short circuits of multiple lines transmitting GOA control signals.

[0006] An embodiment of the present invention provides a display module, comprising:

[0007] A panel comprising a display area and a non-display area located at least on one side of the display area, wherein a gate drive circuit is provided in the non-display area;

[0008] A gate control chip, comprising a first output pin and a second output pin, wherein the first output pin and the second output pin are both electrically connected to the gate drive circuit;

[0009] The gate control chip is used to control the second output pin to output the second signal and control the first output pin not to output the first signal when the first signal output by the first output pin is abnormal.

[0010] In one embodiment, the panel comprises:

[0011] an array substrate layer, comprising the gate drive circuit;

[0012] a first circuit layer, located on the array substrate layer, comprising a first circuit, wherein the first circuit is electrically connected between the first output pin and the gate drive circuit;

[0013] The second circuit layer is located on the array substrate layer and includes a second circuit. The second circuit is electrically connected between the second output pin and the gate drive circuit. The first circuit layer and the second circuit layer are in different layers and are insulated.

[0014] In one embodiment, the gate control chip further includes:

[0015] First input pin;

[0016] An identification module, wherein the first input pin is electrically connected between the first output pin and the identification module, and the identification module is used to control the second output pin to output the second signal and control the first output pin not to output the first signal when identifying that the first signal is abnormal.

[0017] In one embodiment, the identification module includes:

[0018] an identification unit, wherein an input end of the identification unit is electrically connected to the first input pin to receive the first signal;

[0019] a first output unit, wherein a control end of the first output unit is electrically connected to an output end of the identification unit, and is configured to output a first enable signal through the first output end of the first output unit to control the second output pin to output the second signal when the first signal is abnormal;

[0020] A second output unit, wherein the control end of the second output unit is electrically connected to the output end of the identification unit, and is used to output a second disabling signal through the second output end of the second output unit to control the first output pin not to output the first signal when the first signal is abnormal.

[0021] In one embodiment, the first output unit is further configured to output a first disable signal through the first output terminal to control the second output pin to not output the second signal when the first signal is not abnormal;

[0022] The second output unit is further configured to output a second enable signal through the second output terminal to control the first output pin to output the first signal when the first signal is normal.

[0023] In one embodiment, the gate control chip includes a plurality of the identification modules, and the gate control chip further includes:

[0024] an OR circuit, wherein an input end of the OR circuit is electrically connected to the plurality of first output ends, and is configured to output a third enable signal through the output end of the OR circuit to control the second output pin to output the second signal when the first signal is abnormal;

[0025] An AND circuit, wherein the input end of the AND circuit is electrically connected to the plurality of second output ends, and is used to output a fourth enable signal through the output end of the AND circuit to control the first output pin to output the first signal when the first signal is not abnormal.

[0026] In one embodiment, the identification unit includes a voltage comparator, a first input terminal of the voltage comparator is configured as an input terminal of the identification unit, a second input terminal of the voltage comparator is loaded with a reference voltage, and an output terminal of the voltage comparator is configured as an output terminal of the identification unit;

[0027] The first output unit includes a first transistor, a gate of the first transistor is configured as a control terminal of the first output unit, a source of the first transistor is loaded with a first voltage, and a drain of the first transistor is configured as the first output terminal;

[0028] The second output unit includes a second transistor, a gate of the second transistor is configured as a control terminal of the second output unit, a source of the second transistor is loaded with a second voltage, and a drain of the second transistor is configured as the second output terminal.

[0029] In one embodiment, a power management chip is further included, and the gate control chip further includes:

[0030] a second input pin electrically connected to the power management chip to receive a third signal;

[0031] The gate control chip is configured to output the first signal or the second signal according to the third signal.

[0032] In one embodiment, the gate control chip further includes:

[0033] a first switch transistor, wherein a gate of the first switch transistor is electrically connected to the first output terminal, a source of the first switch transistor is electrically connected to the second input pin, and a drain of the first switch transistor is electrically connected to the second output pin;

[0034] a second switch transistor, wherein a gate of the second switch transistor is electrically connected to the second output terminal, a source of the second switch transistor is electrically connected to the second input pin, and a drain of the second switch transistor is electrically connected to the first output pin.

[0035] The present invention further provides an electronic terminal, comprising any one of the display modules described above.

[0036] The present invention provides a display module and an electronic terminal, comprising: a panel including a display area and a non-display area located on at least one side of the display area, wherein a gate drive circuit is provided in the non-display area; a gate control chip including a first output pin and a second output pin, wherein the first output pin and the second output pin are both electrically connected to the gate drive circuit; wherein the gate control chip is used to control the second output pin to output a second signal when a first signal output by the first output pin is abnormal, and to control the first output pin not to output the first signal. The present invention provides a gate control chip having a function of identifying a first signal and including a first output pin and a second output pin both electrically connected to the gate drive circuit. When the first signal is abnormal, the second signal can be loaded to the gate drive circuit to replace the first signal to avoid abnormal operation of the gate drive circuit, thereby improving the reliability of the gate drive circuit and the yield of the display module. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings described below are only used to illustrate some embodiments of the present invention, and those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0038] Figure 1 A schematic top view of a display module provided by an embodiment of the present invention;

[0039] Figure 2 A schematic top view of a gate control chip provided in an embodiment of the present invention;

[0040] Figure 3 A schematic cross-sectional view of a display module provided by an embodiment of the present invention;

[0041] Figure 4 A schematic diagram of the internal structure of a gate control chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0043] The terms "first", "second", "third" and "fourth" in the present invention are used to distinguish different objects rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. Among them, "high potential signal" can be understood as a constant voltage signal with a higher voltage, and the specific voltage value is not limited. For example, a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or modules, but optionally includes steps or modules that are not listed, or optionally includes other steps or modules inherent to these processes, methods, products or devices.

[0044] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] Embodiments of the present invention provide a display module, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0046] In one embodiment, combining Figure 1 and Figure 2 As shown, the display module 100 includes: a panel 10, including a display area A and a non-display area B located on at least one side of the display area A, and a gate driving circuit 20 is provided in the non-display area B; a gate control chip 30, including a first output pin 301 and a second output pin 302, and the first output pin 301 and the second output pin 302 are both electrically connected to the gate driving circuit 20; wherein, the gate control chip 30 is used to control the second output pin 302 to output the second signal when the first signal output by the first output pin 301 is abnormal, and to control the first output pin 301 not to output the first signal.

[0047] In this embodiment, the specific distribution of the non-display area B and the gate drive circuit 20 is not limited. Here, the non-display area B is located on both sides of the display area A, and each non-display area B is provided with a gate drive circuit 20 as an example for description. Figure 1As shown, a plurality of gate lines 01 and a plurality of pixel driving circuits and a plurality of sub-pixels that correspond to and are electrically connected to each other may be provided in the display area A of the panel 10. Each gate line 01 may be electrically connected to the plurality of pixel driving circuits to drive the corresponding plurality of sub-pixels. For example, the plurality of gate lines 01 may extend in the horizontal direction and be arranged in the vertical direction. Each gate line 01 may be electrically connected to the plurality of pixel driving circuits arranged in the horizontal direction to drive the plurality of sub-pixels in the corresponding row. Furthermore, each gate line 01 may extend to the non-display area B to be electrically connected to at least one gate driving circuit 20 to receive a gate signal for driving the plurality of sub-pixels in the corresponding row.

[0048] Further, such as Figure 1 As shown, the display module 100 may also include a first circuit board 401, a second circuit board 402, a first connector 403 and a source driver chip 404, wherein the first circuit board 401 may be provided with an electrically connected timing control chip 4011 and a power management chip 4012, the first connector 403 is electrically connected between the first circuit board 401 and the second circuit board 402, the second circuit board 402 may be provided with a gate control chip 30, and the source driver chip 404 is electrically connected to the second circuit board 402 through COF (Chip OnFlex, also called flip chip film) technology, that is, the second circuit board 402 is electrically connected to the flip chip film 405 including the source driver chip 404. Furthermore, the first circuit board 401 and the second circuit board 402 can be flexible circuit boards or rigid circuit boards at the same time or at different times, and the first connector 403 can be but not limited to a flexible flat cable connector, wherein a second circuit board 402 can be electrically connected to the first circuit board 401 through the first connector 403, and two adjacent second circuit boards 402 can be electrically connected through but not limited to a second connector 406 made of a flexible circuit board, and each second circuit board 402 can be electrically connected to multiple cover films 405.

[0049] Specifically, in conjunction with the above discussion, the power management chip 4012 can receive and convert the initial gate control signal and the initial source control signal generated by the timing control chip 4011 into target gate control signals and target source control signals, respectively. The power management chip 4012 can transmit the target gate control signal to the gate control chip 30 via the wiring located on the first circuit board 401, the first connector 403, the second connector 406, and the wiring located on the second circuit board 402. Simultaneously, the power management chip 4012 can transmit the target source control signal to the active electrode driver chip 404 included in the chip-on-film 405 via the wiring located on the first circuit board 401, the first connector 403, the second connector 406, and the wiring located on the second circuit board 402. Furthermore, in conjunction with the above discussion, the gate control chip 30 and the gate driver circuit 20 control the gate signal on the gate line 01, and the active electrode driver chip 404 controls the data signal on the data line, thereby jointly driving multiple sub-pixels to emit light. In particular, multiple pixel driver circuits electrically connected to the same data line can be electrically connected to different gate lines.

[0050] It is understood that the display module 100 in this embodiment is provided with a gate control chip 30, and the gate control chip 30 includes a first output pin 301 and a second output pin 302, both of which are electrically connected to the gate drive circuit 20. When the first signal output by the first output pin 301 is abnormal, the gate control chip 30 can control the second output pin 302 to output the second signal, and control the first output pin 301 not to output the first signal. That is, when the first signal is abnormal, the second signal can replace the first signal and be applied to the gate drive circuit 20 to drive the gate drive circuit 20 to operate, thereby preventing the gate drive circuit 20 from operating abnormally due to the abnormal first signal. At the same time, the first output pin 301 can be controlled not to output the first signal to prevent the abnormal first signal from interfering with the operation of the gate drive circuit 20. Therefore, compared to providing only one set of pins that can apply signals to the gate drive circuit 20, the second output pin 302 in the gate control chip 30 in this embodiment can apply the second signal to the gate drive circuit 20 when the first signal is abnormal, thereby preventing the gate drive circuit 20 from operating abnormally, thereby improving the reliability of the gate drive circuit 20 and improving the yield of the display module 100.

[0051] In one embodiment, combining Figures 1 to 3As shown, the panel 10 includes: an array substrate layer, including the gate drive circuit 20; a first circuit layer, located on the array substrate layer, including a first circuit 601, the first circuit 601 is electrically connected between the first output pin 301 and the gate drive circuit 20; a second circuit layer, located on the array substrate layer, including a second circuit 602, the second circuit 602 is electrically connected between the second output pin 302 and the gate drive circuit 20, and the first circuit layer and the second circuit layer are different layers and are insulated.

[0052] Specifically, such as Figure 3 As shown, in the non-display area B, the gate drive circuit 20 may include a first access point 201 and a second access point 202 that are insulated. For example, the first circuit 601 may be arranged in contact with the array substrate layer to be electrically connected to the first access point 201, thereby electrically connecting the first output pin 301 to the gate drive circuit 20. The second circuit 602 located on the side of the first circuit layer away from the array substrate layer may be electrically connected to the second access point 202 through a via technology, thereby electrically connecting the second output pin 302 to the gate drive circuit 20. An insulating layer 603 may be provided between the first circuit 601 and the second circuit 602 to insulate the two. A color filter layer 604 may also be provided on the side of the second circuit layer away from the array substrate layer to combine the light emitted by multiple sub-pixels to achieve colored display.

[0053] It can be understood that the first circuit 601 and the second circuit 602 in this embodiment can be located in the non-display area B. Furthermore, the two can be arranged relative to the gate drive circuit 20 to facilitate electrical connection to the gate drive circuit 20. At the same time, the two are arranged in different layers to avoid increasing the width of the non-display area B, which is conducive to achieving a narrow frame. Combined with the above discussion, when the first output pin 301 outputs a first signal, the first signal can be transmitted to the gate drive circuit 20 through the first circuit 601. When the second output pin 302 outputs a second signal, the second signal can be transmitted to the gate drive circuit 20 through the second circuit 602, so as to realize real-time driving of the gate drive circuit 20.

[0054] In one embodiment, if Figure 2As shown, the gate control chip 30 further includes: a first input pin 303; and an identification module 304. The first input pin 303 is electrically connected between the first output pin 301 and the identification module 304. The identification module 304 is configured to control the second output pin 302 to output the second signal and control the first output pin 301 not to output the first signal when the first signal is identified as abnormal. On the periphery of the gate control chip 30, the first input pin 303 can be electrically connected to the first output pin 301 via a first conductive portion 501 to receive the first signal output by the first output pin 301. Inside the gate control chip 30, the identification module 304 can be electrically connected to the first input pin 303 via a second conductive portion 502 to receive the input first signal.

[0055] It should be noted that before the identification module 304 receives the first signal or identifies the first signal as abnormal, the first output pin 301 may output the first signal, while the second output pin 302, which has not received the instruction from the identification module 304, may not output the second signal. That is, at this time, the first output pin 301 still outputs and loads the first signal to the gate drive circuit 20 to drive the gate drive circuit 20. In combination with the above discussion, when the identification module 304 identifies the first signal as abnormal, it can control the second output pin 302 to output and load the second signal to the gate drive circuit 20, and at the same time control the first output pin 301 not to output the first signal, so as to prevent the abnormal first signal from interfering with the operation of the gate drive circuit 20. Therefore, based on the above, in this embodiment, the identification module 304 is provided to obtain and identify the first signal, and can load the second signal to the gate drive circuit 20 when the first signal is abnormal to avoid abnormal operation of the gate drive circuit 20, thereby improving the reliability of the operation of the gate drive circuit 20 and improving the yield of the display module 100.

[0056] In one embodiment, combining Figure 2 and Figure 4As shown, the identification module 304 includes: an identification unit 3041, the input terminal C1 of the identification unit 3041 is electrically connected to the first input pin 303 to receive the first signal; a first output unit 3042, the control terminal D1 of the first output unit 3042 is electrically connected to the output terminal C2 of the identification unit 3041, and is used to output a first enable signal through the first output terminal D2 of the first output unit 3042 to control the second output pin 302 to output the second signal when the first signal is abnormal; a second output unit 3043, the control terminal E1 of the second output unit 3043 is electrically connected to the output terminal C2 of the identification unit, and is used to output a second disable signal through the second output terminal E2 of the second output unit 3043 to control the first output pin 301 not to output the first signal when the first signal is abnormal.

[0057] Specifically, such as Figure 4 As shown, the input terminal C1 of the recognition unit 3041 can receive the first signal. Further, the recognition module 304 in this embodiment also includes a first output unit 3042 whose control terminal D1 is electrically connected to the output terminal C2 of the recognition unit 3041, and a second output unit 3043 whose control terminal E1 is electrically connected to the output terminal C2 of the recognition unit 3041. In combination with the recognition function of the recognition unit 3041, Figure 2 and Figure 4 As shown, when the first signal is abnormal, the first output unit 3042 can control its own first output terminal D2 to output the first enable signal to control the second output pin 302 to output the second signal, and the second output unit 3043 can control its own second output terminal E2 to output the second disable signal to control the first output pin 301 not to output the first signal, that is, the gate control chip 30 outputs the second signal to replace the first signal when the first signal is abnormal to maintain the normal operation of the gate drive circuit 20.

[0058] In one embodiment, combining Figure 2 and Figure 4As shown, the first output unit 3042 is further configured to output a first disable signal through the first output terminal D2 to control the second output pin 302 from outputting the second signal when the first signal is normal; the second output unit 3043 is further configured to output a second enable signal through the second output terminal E2 to control the first output pin 301 from outputting the first signal when the first signal is normal. Similarly, in combination with the above discussion, when the first signal is normal, the first output unit 3042 can control its own first output terminal D2 to output the first disable signal to control the second output pin 302 from outputting the second signal, and the second output unit 3043 can control its own second output terminal E2 to output the second enable signal to control the first output pin 301 to output the first signal. This ensures that the gate control chip 30 maintains the first signal and prevents the output of the second signal when the first signal is normal, thereby maintaining the normal operation of the gate drive circuit 20.

[0059] In one embodiment, combining Figure 2 and Figure 4 As shown, the gate control chip 30 includes a plurality of the identification modules 304, and the gate control chip 30 also includes: an OR circuit 305, the input end of the OR circuit 305 is electrically connected to the plurality of the first output ends D2, and is used to output a third enable signal through the output end of the OR circuit 305 to control the second output pin 302 to output the second signal when the first signal is abnormal; and an AND circuit 306, the input end of the AND circuit 306 is electrically connected to the plurality of the second output ends E2, and is used to output a fourth enable signal through the output end of the AND circuit 306 to control the first output pin to output the first signal when the first signal is not abnormal.

[0060] Among them, combined Figure 2 and Figure 4 As shown, the gate control chip 30 may also include a plurality of first output pins 301, a plurality of second output pins 302, and a plurality of first input pins 303 corresponding to a plurality of identification modules 304. Accordingly, each first output pin 301 can transmit a corresponding first signal to a corresponding first input pin 303, and each second output pin 302 can output a corresponding second signal. In other words, each identification module 304 can be electrically connected to a corresponding first input pin 303 to identify the corresponding first signal. The plurality of first signals may include, but are not limited to, a field period signal STV and clock signals CK1 to CK8.

[0061] Specifically, according to the characteristics of the OR circuit 305, if at least one first output terminal D2 outputs a high potential, the OR circuit 305 outputs a high potential. Based on the above-mentioned first enable signal being a high potential signal, that is, when at least one first signal is abnormal, the corresponding at least one first output terminal D2 can output a first enable signal as a high potential signal, which can control the output terminal of the OR circuit 305 to output a third enable signal as a high potential signal, and can realize the above-mentioned function, that is, "the first enable signal in the single identification module 304 scheme controls the second output pin 302 to output the second signal, and the third enable signal in the multiple identification modules 304 scheme controls the second output pin 302 to output the second signal", that is, the function of the first enable signal in the single identification module 304 scheme can be achieved to be the same as the function of the third enable signal in the multiple identification modules 304 scheme.

[0062] Specifically, according to the characteristics of the AND circuit 306, if each second output terminal E2 outputs a high potential, the AND circuit 306 outputs a high potential. Based on the above-mentioned second enable signal being a high potential signal, that is, when each first signal is not abnormal, the corresponding each second output terminal E2 can output a second enable signal as a high potential signal, which can control the output terminal of the AND circuit 306 to output a fourth enable signal as a high potential signal, and can realize the function mentioned above, that is, "the second enable signal in the single identification module 304 scheme controls the first output pin 301 to output the first signal, and the fourth enable signal in the multiple identification modules 304 scheme controls the first output pin 301 to output the first signal", that is, the role of the second enable signal in the single identification module 304 scheme can be achieved to be the same as the role of the fourth enable signal in the multiple identification modules 304 scheme.

[0063] In one embodiment, combining Figure 2 and Figure 4 As shown, the identification unit 3041 includes a voltage comparator 30411, the first input terminal of the voltage comparator 30411 is configured as the input terminal C1 of the identification unit 3041, and the second input terminal of the voltage comparator 30411 is loaded with a reference voltage V ref , the output end of the voltage comparator 30411 is configured as the output end C2 of the identification unit 3041; the first output unit 3042 includes a first transistor T1, the gate of the first transistor T1 is configured as the control end D1 of the first output unit 3042, the source of the first transistor T1 is loaded with the first voltage V1, and the drain of the first transistor T1 is configured as the first output end D2; the second output unit 3043 includes a second transistor T2, the gate of the second transistor T2 is configured as the control end E1 of the second output unit 3043, the source of the second transistor T2 is loaded with the second voltage V2, and the drain of the second transistor is configured as the second output end E2.

[0064] In combination with the above discussion, it can be seen that the voltage comparator 30411 in this embodiment can compare the voltage value corresponding to the first signal with the reference voltage V ref The magnitude relationship is used to control the turn-on status of the first transistor T1 and the second transistor T2, and the values ​​of the first enable signal, the first disable signal, the second enable signal and the second disable signal are determined in combination with the specific values ​​of the first voltage V1 and the second voltage V2.

[0065] Specifically, the first transistor T1 is an N-type transistor and the voltage value corresponding to the first signal is greater than the reference voltage V ref When the first signal is turned on, the second transistor T2 is a P-type transistor and the voltage value corresponding to the first signal is less than the reference voltage V ref For example, Figure 4 As shown, the gate control chip 30 further includes a first resistor R1, which is connected in series with a second resistor R2. The second resistor R2 can be understood as the resistance of a circuit in the gate control chip 30 that is electrically connected to the first output pin 301. The node where the first resistor R1 is not connected to the second resistor R2 is grounded, and the node F where the second resistor R2 is not connected to the first resistor R1 has a voltage V F , that is, the first resistor R1 and the second resistor R2 share the voltage V F Therefore, when the circuit electrically connected to the first output pin 301 in the gate control chip 30 is short-circuited, the second resistance R2 is reduced, and the voltage distributed on the first resistor R1 increases, that is, the voltage at the connection point G of the first resistor R1 and the second resistor R2 increases. Among them, the first signal is the signal output by the first output pin 301 and the signal input by the first input pin 303, that is, Figure 4 The voltage at the connection point G between the first resistor R1 and the second resistor R2.

[0066] It can be understood that the input terminal C1 of the identification unit 3041 in this embodiment can receive the voltage of the connection point G of the first resistor R1 and the second resistor R2, which is the same as the first signal. In combination with the above discussion, when the first signal is abnormal, that is, the line electrically connected to the first output pin 301 in the gate control chip 30 is short-circuited, the second resistor R2 is reduced, that is, the voltage received by the input terminal C1 of the identification unit 3041 increases. It can be considered that the voltage of the first input terminal of the voltage comparator 30411 is greater than the reference voltage V ref, that is, the first transistor T1 is turned on, and the first voltage V1 is transmitted to the first output terminal D2 through the first transistor T1, that is, the first voltage V1 serves as the first enable signal mentioned above to control the second output pin 302 to output the second signal. At the same time, the second transistor T2 is turned on, and the second output terminal E2 is suspended, that is, the voltage of the second output terminal E2 at this time can be used as the second disable signal mentioned above to control the first output pin 301 not to output the first signal.

[0067] Similarly, when the first signal is normal, that is, the circuit electrically connected to the first output pin 301 in the gate control chip 30 is not short-circuited, the second resistor R2 is large, that is, the voltage received by the input terminal C1 of the identification unit 3041 is small, and it can be considered that the voltage of the first input terminal of the voltage comparator 30411 is less than the reference voltage V ref , that is, the second transistor T2 is turned on, and the second voltage V2 is transmitted to the second output terminal E2 through the second transistor T2, that is, the second voltage V2 serves as the second enable signal mentioned above to control the first output pin 301 to output the first signal. At the same time, the first transistor T1 is turned on, and the first output terminal D2 is left floating, that is, the voltage of the first output terminal D2 at this time can be used as the first disable signal mentioned above to control the second output pin 302 not to output the second signal.

[0068] In one embodiment, combining Figures 1 to 4 As shown, the display module 100 also includes a power management chip 4012, and the gate control chip 30 also includes: a second input pin 307, electrically connected to the power management chip 4012 to receive a third signal; wherein, the gate control chip 30 is used to output the first signal or the second signal according to the third signal. Specifically, in combination with the above discussion, the power management chip 4012 can transmit the target gate control signal to the gate control chip 30 through the lines located on the first circuit board 401, the first connector 403, the second connector 406 and the lines located on the second circuit board 402. The third signal here is the target gate control signal. It should be noted that after power-on, the second input pin 307 needs to be electrically connected to the first output pin 301, so as to combine with the first input pin 303 for the gate control chip 30 to receive and identify the first signal, and the second output pin 302 that does not receive the indication of the gate control chip 30 can be electrically disconnected from the first output pin 301 to not output the second signal, that is, at this time, the first output pin 301 is still output and the first signal is loaded to the gate drive circuit 20 to drive the gate drive circuit 20; further, combined with whether the first signal generated according to the third signal is abnormal, the gate control chip 30 outputs the first signal or the second signal.

[0069] In one embodiment, combining Figures 1 to 4As shown, the gate control chip 30 further includes: a first switching transistor, wherein the gate of the first switching transistor is electrically connected to the first output terminal D2, the source of the first switching transistor is electrically connected to the second input pin 307, and the drain of the first switching transistor is electrically connected to the second output pin 302; and a second switching transistor, wherein the gate of the second switching transistor is electrically connected to the second output terminal E2, the source of the second switching transistor is electrically connected to the second input pin 307, and the drain of the second switching transistor is electrically connected to the first output pin 301. In this embodiment, the first switching transistor and the second switching transistor are both N-type transistors and are turned on when their gates are at a high voltage.

[0070] In combination with the above discussion, it can be seen that when the first signal is abnormal, the first output terminal D2 outputs a first enable signal which is a high-voltage signal to control the second output pin 302 to output the second signal, that is, it can be considered that the voltage value of the high-voltage signal is equal to the high voltage mentioned above. Furthermore, in this embodiment, by setting a first switching transistor, it can be turned on to electrically connect the second input pin 307 to the second output pin 302, that is, the second output pin 302 can output the second signal; at the same time, the second output terminal E2 outputs a second non-enable signal which is not a high-voltage signal to control the first output pin not to output the first signal. Furthermore, in this embodiment, by setting a second switching transistor, it can be turned off to electrically disconnect the second input pin 307 from the first output pin 301, that is, the first output pin 301 can not output the first signal.

[0071] In combination with the above discussion, it can be seen that when the first signal is not abnormal, the first output terminal D2 outputs a first disable signal that is not a high-voltage signal to control the second output pin not to output the second signal. Furthermore, in this embodiment, by setting a first switching transistor, it can be turned off to electrically disconnect the second input pin 307 from the second output pin 302, that is, the second output pin 302 can not output the second signal; at the same time, the second output terminal E2 outputs a second enable signal that is a high-voltage signal to control the first output pin to output the first signal. Further, in this embodiment, by setting a second switching transistor, it can be turned on to electrically connect the second input pin 307 to the first output pin 301, that is, the first output pin 301 can output the first signal.

[0072] Furthermore, when the gate control chip 30 includes multiple identification modules 304, multiple first output pins 301 corresponding to the multiple identification modules 304, multiple second output pins 302 and multiple first input pins 303, the output end of the OR circuit 305 instead of the first output end D2 can be electrically connected to the gate of the first switching transistor. Similarly, the output end of the AND circuit 306 instead of the second output end E2 can be electrically connected to the gate of the second switching transistor. The specific working principle can refer to the above description of the OR circuit 305, the AND circuit 306, the first switching transistor and the second switching transistor.

[0073] An embodiment of the present invention provides an electronic terminal, comprising the display module as described in any one of the above items.

[0074] The present invention provides a display module and an electronic terminal, comprising: a panel including a display area and a non-display area located on at least one side of the display area, wherein a gate drive circuit is provided in the non-display area; a gate control chip including a first output pin and a second output pin, wherein the first output pin and the second output pin are both electrically connected to the gate drive circuit; wherein the gate control chip is used to control the second output pin to output a second signal when a first signal output by the first output pin is abnormal, and to control the first output pin not to output the first signal. The present invention provides a gate control chip having a function of identifying a first signal and including a first output pin and a second output pin both electrically connected to the gate drive circuit. When the first signal is abnormal, the second signal can be loaded to the gate drive circuit to replace the first signal to avoid abnormal operation of the gate drive circuit, thereby improving the reliability of the gate drive circuit and the yield of the display module.

[0075] The display module and electronic terminal provided in the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display module, characterized in that: include: A panel, comprising a display area and a non-display area located at least on one side of the display area, wherein a gate driving circuit is disposed in the non-display area; A gate control chip, comprising a first output pin and a second output pin, wherein the first output pin and the second output pin are both electrically connected to the gate drive circuit; Wherein, the gate control chip is used to control the second output pin to output the second signal, and control the first output pin not to output the first signal when the first signal output by the first output pin is abnormal; Wherein, the gate control chip further includes: First input pin; an identification module, wherein the first input pin is electrically connected between the first output pin and the identification module, and the identification module is used to control the second output pin to output the second signal and control the first output pin not to output the first signal when identifying that the first signal is abnormal; Wherein, the display module further includes a power management chip, and the gate control chip further includes: A second input pin, electrically connected to the power management chip to receive a third signal; Wherein, the gate control chip is used to output the first signal or the second signal according to the third signal.

2. The display module according to claim 1, characterized in that: The panel comprises: An array substrate layer, including the gate driving circuit; A first circuit layer, located on the array substrate layer, comprising a first circuit, wherein the first circuit is electrically connected between the first output pin and the gate driving circuit; The second circuit layer is located on the array substrate layer and includes a second circuit. The second circuit is electrically connected between the second output pin and the gate drive circuit. The first circuit layer and the second circuit layer are in different layers and are insulated.

3. The display module according to claim 1, characterized in that: The identification module comprises: an identification unit, wherein an input end of the identification unit is electrically connected to the first input pin to receive the first signal; a first output unit, wherein a control end of the first output unit is electrically connected to an output end of the identification unit, and is used for outputting a first enable signal through the first output end of the first output unit to control the second output pin to output the second signal when the first signal is abnormal; A second output unit, wherein the control end of the second output unit is electrically connected to the output end of the identification unit, and is used to output a second disabling signal through the second output end of the second output unit to control the first output pin not to output the first signal when the first signal is abnormal.

4. The display module according to claim 3, characterized in that: The first output unit is further configured to output a first disabling signal through the first output terminal to control the second output pin not to output the second signal when the first signal is not abnormal; The second output unit is further configured to output a second enable signal through the second output terminal to control the first output pin to output the first signal when the first signal is normal.

5. The display module according to claim 4, characterized in that: The gate control chip includes a plurality of the identification modules, and the gate control chip further includes: An OR circuit, wherein the input end of the OR circuit is electrically connected to the plurality of the first output ends, and is used for outputting a third enable signal through the output end of the OR circuit to control the second output pin to output the second signal when the first signal is abnormal; An AND circuit, wherein the input end of the AND circuit is electrically connected to the plurality of second output ends, and is used to output a fourth enable signal through the output end of the AND circuit to control the first output pin to output the first signal when the first signal is normal.

6. The display module according to claim 3, characterized in that: The identification unit comprises a voltage comparator, a first input terminal of the voltage comparator is configured as an input terminal of the identification unit, a second input terminal of the voltage comparator is loaded with a reference voltage, and an output terminal of the voltage comparator is configured as an output terminal of the identification unit; The first output unit includes a first transistor, a gate of the first transistor is configured as a control terminal of the first output unit, a source of the first transistor is loaded with a first voltage, and a drain of the first transistor is configured as the first output terminal; The second output unit includes a second transistor, a gate of the second transistor is configured as a control terminal of the second output unit, a source of the second transistor is loaded with a second voltage, and a drain of the second transistor is configured as the second output terminal.

7. The display module according to claim 3, characterized in that: The gate control chip also includes: a first switch transistor, wherein a gate of the first switch transistor is electrically connected to the first output terminal, a source of the first switch transistor is electrically connected to the second input pin, and a drain of the first switch transistor is electrically connected to the second output pin; A second switch transistor, wherein a gate of the second switch transistor is electrically connected to the second output terminal, a source of the second switch transistor is electrically connected to the second input pin, and a drain of the second switch transistor is electrically connected to the first output pin.

8. An electronic terminal, characterized in that: The electronic terminal comprises the display module as claimed in any one of claims 1 to 7.

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