A method for testing the safety performance of SRAM chips

Abstract

The present invention relates to a method for testing the safety performance of an SRAM chip, which belongs to the field of chip detection technology and solves the problem that the evaluation variables of the prior art are too single and cannot accurately measure the aging imprint. The method comprises the steps of: powering on a plurality of SRAM chips to be tested, initializing the back gate voltage of their storage arrays, and obtaining a power-on initial value of each SRAM chip; writing uniform data to all SRAM chips, grouping the SRAM chips after writing the uniform data, setting different back gate voltages for each group, and maintaining them for a predetermined time in different irradiation environments; re-powering on all SRAM chips to obtain a secondary power-on initial value of each SRAM chip; respectively inputting the secondary power-on initial value and the corresponding primary power-on initial value of each SRAM chip in different groups under different irradiation environments into an aging imprint force model, obtaining the aging imprint force of each SRAM chip under different irradiation environments, and then obtaining the safety performance test results of the SRAM chip to be tested.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a method for testing the safety performance of a SRAM chip. Background Art

[0002] Before the SRAM chip is put into use, it needs to be tested for its security performance. In order to protect data security, once the existing security chip system detects unauthorized illegal access, it will cut off the power supply of the SRAM chip to prevent attackers from stealing data. However, SRAM chips have the problem of information residue, and will partially restore the information stored before power failure. That is, when a certain storage unit is used to store fixed data for a long time, the two symmetrical MOS tubes will have different degrees of BTI aging effects, resulting in permanent threshold voltage mismatch, resulting in a certain probability (about 10% to 20%) of reading the power-on initial value opposite to the original storage value after the unit is powered on.

[0003] The existing technology has the problem of a single variable when testing the aging of SRAM chips. Currently, only the effect of voltage on aging is considered. In addition, it is difficult to accurately evaluate the aging of SRAM chips by comparing the differences in pictures. Summary of the invention

[0004] In view of the above analysis, an embodiment of the present invention aims to provide a method for testing the safety performance of an SRAM chip, so as to solve the problem that the evaluation variables in the prior art are too single and cannot accurately measure the degree of aging.

[0005] On the one hand, an embodiment of the present invention provides a method for testing the safety performance of an SRAM chip, comprising the following steps:

[0006] Power on a plurality of SRAM chips to be tested, initialize the back gate voltage of the storage array thereof, and obtain a power-on initial value after each SRAM chip to be tested is initialized;

[0007] Writing unified data to all SRAM chips, grouping the SRAM chips after writing the unified data, setting different back gate voltages for each group, and keeping them in different irradiation environments for a predetermined time before powering off;

[0008] Re-power on all SRAM chips to obtain the secondary power-on initial value of each SRAM chip after powering on again;

[0009] The secondary power-on initial value and the corresponding primary power-on initial value of each SRAM chip in each group under different irradiation environments are respectively input into the aging imprint force model to obtain the aging imprint force of each SRAM chip in each group under different irradiation environments;

[0010] According to the aging imprint strength of each SRAM chip in each group under the above-mentioned different irradiation environments, the safety performance test result of the SRAM chip to be tested is obtained.

[0011] The beneficial effects of the above technical solution are as follows: a multivariable and easy-to-quantify SRAM aging imprint force test method is proposed. Considering the introduction of back gate voltage and radiation effect, the problem of single variable when testing SRAM chip aging in the prior art is solved. At the same time, through the experimental measurement data and the customized aging imprint force model, it is no longer necessary to judge the aging condition by comparing the blurriness of the picture with the naked eye, which solves the problem that the aging imprint force is difficult to quantitatively evaluate. By comparing the anti-aging imprint capabilities of a batch of SRAM chips, while taking into account the influencing factors of multiple variables such as back gate and radiation, the final evaluation results of the safety performance of the SRAM chip to be tested are more comprehensive and reliable. The above method can be directly applied to SRAM chips that have been put into use, quantitatively analyze whether their safety performance meets the standards, and evaluate whether the corresponding security system has security vulnerabilities. After a large number of experimental verifications, the results are credible.

[0012] Based on the further improvement of the above method, the power-on initial value is the ratio of the number of storage cells with a value of 1 to the number of storage cells with a value of 0 in the SRAM chip to be tested after power-on;

[0013] The step of powering on a plurality of SRAM chips to be tested and initializing the back gate voltage of their storage arrays to obtain a power-on initial value of each SRAM chip to be tested after initialization comprises:

[0014] Connect each SRAM chip to be tested to the test system respectively, and power on the SRAM chip through the test system;

[0015] The back gate voltages of all NMOS transistors and PMOS transistors in the storage array of the SRAM chip are set to 0V to complete initialization, and the number and ratio of 1s and 0s in the storage array after initialization are counted;

[0016] Repeat the above process n times, and calculate Rate1 according to the following formula as the initial value of each SRAM chip to be tested after initialization.

[0017]

[0018] Where N 1i is the number of storage array cells that are 1 in the i-th test, N 0i is the number of storage array cells that are 0 in the i-th test, and n is the number of repeated power-on initializations, which is also the number of tests.

[0019] The beneficial effects of the above further improved solution are: controlling the back gate voltage of all NMOS transistors and PMOS transistors in the storage array of the SRAM chip to eliminate the interference caused by voltage fluctuations, and repeatedly counting the initial power-on value to reduce the impact of strong jitter nodes.

[0020] Further, the test system includes a test board and an FPGA chip connected in sequence;

[0021] The test board is used to connect to the SRAM chip to be tested, adjust the back gate voltages of all NMOS transistors and PMOS transistors in its storage array according to the control of the FPGA chip; and output the information stored in the storage array of the SRAM chip to the FPGA chip;

[0022] The FPGA chip is used to send initialization instructions to the test board during testing, wherein the initialization instructions are used to set the back gate voltages of all NMOS transistors and PMOS transistors in the storage array of the SRAM chip to 0V; and, after the initialization is completed, send read and write instructions to the test board, and receive information stored in the storage array fed back by the test board; the information includes the number and ratio of 1s and 0s in the storage array.

[0023] The beneficial effect of the above further improved scheme is that the connection form of the SRAM chip to be tested-the test board-the FPGA chip is simple and convenient, and can realize rapid testing and obtain data (information stored in the storage array).

[0024] Furthermore, the grouping includes at least the following 5 groups:

[0025] The grouping of NMOS transistors is negatively biased and PMOS transistors is negatively biased;

[0026] The grouping of NMOS transistors is negatively biased and PMOS transistors is positively biased;

[0027] A grouping of NMOS transistors with zero bias and PMOS transistors with zero bias;

[0028] The grouping of NMOS transistors is forward biased and PMOS transistors is negative biased;

[0029] The grouping of NMOS transistors forward biased and PMOS transistors forward biased;

[0030] Furthermore, each group includes at least 15 SRAM chips.

[0031] The above further improved scheme has the beneficial effects of: considering various back gate bias conditions to determine the worst back gate bias condition of the aged imprint. Setting multiple groups of SRAM chips for testing to ensure the credibility of the data. Each group includes at least 15 SRAM chips to ensure the credibility of the safety performance test results.

[0032] Furthermore, the irradiation environments include at least three types, the span of radiation doses between any two irradiation environments is not less than 100 krad (Si), and the highest radiation dose is greater than 300 krad (Si).

[0033] The beneficial effect of the above further improvement scheme is that the radiation environment is taken into consideration, and the safety performance test results incorporate the influence of various radiation environments on the aging imprint.

[0034] Further, the unified data is all 0 or all 1;

[0035] When the radiation dose rate of the radiation environment is 50 rad / s, the predetermined time is greater than or equal to 2000 s.

[0036] The beneficial effect of the above further improved solution is: further ensuring that the span between the radiation doses of each two irradiation environments is not less than 100 krad (Si).

[0037] Furthermore, each SRAM chip is tested no less than 3 times.

[0038] The beneficial effect of the above further improved solution is: multiple tests are performed to ensure the credibility of the data.

[0039] Further, the aging imprint force model is

[0040]

[0041]

[0042] Where Φ() is the standard normal cumulative distribution function, Ratio1 is the ratio of 1 to 0 in the initial value of power-on, Ratio3 is the ratio of 1 to 0 in the initial value of power-on twice, σ noise is the noise impact factor, T is the scheduled time; F j represents the aging imprint strength F obtained in the jth test j , α is the radiation environment coefficient, dose is the radiation dose in the irradiation environment, V p 、V n They are the back gate voltages of the PMOS transistor and the NMOS transistor during the test.

[0043] The beneficial effect of the above further improvement scheme is: the aging imprint force is calculated by the above aging imprint force model, which comprehensively considers multiple variables such as back gate voltage, radiation dose, power-on initial value and noise, so that the obtained aging imprint force result is more complete and reliable.

[0044] Further, the step of obtaining the safety performance test result of the SRAM chip to be tested according to the aging imprint strength of each SRAM chip in each group under the above-mentioned different irradiation environments includes:

[0045] The aging stamping force F of all SRAM chips in each group is tested. j Take the average value as the aging imprint strength of the group of chips in the corresponding radiation environment;

[0046] According to the aging stamping strength of the M groups of SRAM chips, the final aging stamping strength evaluation index F of the SRAM chip to be tested is obtained. total ;

[0047] If the final aging stamping force F total If the test result is within the preset range, the test result indicating that the safety performance of the SRAM chip to be tested is qualified is output.

[0048] The beneficial effect of the above further improvement scheme is: selecting the aging imprint strength of M groups of SRAM chips as the final aging imprint strength evaluation index improves the credibility of the evaluation result and can eliminate the interference of accidental situations.

[0049] Furthermore, the F total Obtained by the following formula

[0050]

[0051] Where M is the number of SRAM chips.

[0052] The beneficial effect of the above further improvement scheme is: the final aging imprint strength evaluation index of the SRAM chip to be tested is calculated in an average manner, which simplifies the calculation process and saves computing resources while ensuring the credibility of the data.

[0053] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0055] Figure 1 Schematic diagram of the steps of the method for testing the safety performance of an SRAM chip according to Example 1 of the present invention. DETAILED DESCRIPTION

[0056] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0057] Example 1

[0058] A specific embodiment of the present invention discloses a method for testing the safety performance of an SRAM chip, such as Figure 1 As shown, the following steps are included:

[0059] S1. Power on multiple SRAM chips to be tested, and initialize the back gate voltage of the storage array, and obtain the initial power-on value of each SRAM chip to be tested after initialization by statistics;

[0060] S2. write uniform data to all SRAM chips, group the SRAM chips after writing the uniform data, set different back gate voltages for each group, and keep them in different irradiation environments for a predetermined time before powering off;

[0061] S3. Re-power on all SRAM chips, and obtain the secondary power-on initial value of each SRAM chip after re-powering on by statistics;

[0062] S4. respectively input the secondary power-on initial value and the corresponding primary power-on initial value of each SRAM chip in each group under different irradiation environments into the aging imprint force model to obtain the aging imprint force of each SRAM chip in each group under different irradiation environments;

[0063] S5. According to the aging imprint strength of each SRAM chip in each group under the above-mentioned different irradiation environments, the safety performance test result of the SRAM chip to be tested is obtained.

[0064] During implementation, the SRAM chip to be tested is first tested in different radiation environments and with different back gate voltages, and then the obtained test results are comprehensively analyzed through an aging imprint force model, and finally the safety performance test results of the SRAM chip to be tested are obtained.

[0065] Compared with the prior art, this embodiment proposes a multivariable and easy-to-quantify SRAM aging imprint force test method. Considering the introduction of back gate voltage and radiation effect, the problem of single variable when testing SRAM chip aging in the prior art is solved. At the same time, through the experimental measurement data and the customized aging imprint force model, it is no longer necessary to judge the aging condition by comparing the blurriness of the picture with the naked eye, which solves the problem that the aging imprint force is difficult to quantitatively evaluate. By comparing the anti-aging imprint capabilities of a batch of SRAM chips, while taking into account the influencing factors of multiple variables such as back gate and radiation, the final evaluation results of the safety performance of the SRAM chip to be tested are more comprehensive and reliable. The above method can be directly applied to SRAM chips that have been put into use, quantitatively analyze whether their safety performance meets the standards, and evaluate whether the corresponding security system has security vulnerabilities.

[0066] Example 2

[0067] Based on the optimization of Example 1, the power-on initial value is represented by the ratio of the number of storage cells with a value of 1 to the number of storage cells with a value of 0 in the SRAM chip after power-on.

[0068] Step S1 further comprises:

[0069] S11. Connect each SRAM chip to the test system and power on the SRAM chip through the test system;

[0070] S12. Set the back gate voltage V of all NMOS transistors and PMOS transistors in the storage array of the SRAM chip BN With V BP All are set to 0V to complete initialization, and the number and ratio of 1 and 0 in the storage array after initialization are counted;

[0071] S13. Repeat the above steps S11 to S12 to complete n tests, and obtain the number and ratio of 1 and 0 in the storage array after the SRAM chip is initialized in the n test results, and the number N of all 1 and 0 1i 、N 0i The average of the ratio is calculated to obtain the initial value Rate1 of each SRAM chip to be tested after initialization.

[0072]

[0073] Where N 1i 、N 0i The numbers of 1 and 0 in the storage array after the SRAM chip is initialized are tested for the i-th time respectively.

[0074] Preferably, the test system comprises a test board and an FPGA chip which are connected in sequence.

[0075] The test board is used to connect to the SRAM chip to be tested, adjust the back gate voltages of all NMOS transistors and PMOS transistors in its storage array according to the control of the FPGA chip; and output the information stored in the storage array of the SRAM chip to the FPGA chip.

[0076] The FPGA chip is used to send initialization instructions to the test board during testing, wherein the initialization instructions are used to set the back gate voltages of all NMOS transistors and PMOS transistors in the storage array of the SRAM chip to 0V; and, after the initialization is completed, send read and write instructions to the test board, and receive information stored in the storage array fed back by the test board; the information includes the number and ratio of 1s and 0s in the storage array.

[0077] Preferably, the grouping is at least 5 groups, including one group each of NMOS transistor negative bias / PMOS transistor negative bias, NMOS transistor negative bias / PMOS transistor positive bias, NMOS transistor zero bias / PMOS transistor zero bias, NMOS transistor positive bias / PMOS transistor negative bias, and NMOS transistor positive bias / PMOS transistor positive bias, see Table 1; each group includes at least 15 SRAM chips.

[0078] Table 1

[0079]

[0080] Preferably, the irradiation environment includes at least three types. It can be set to low / none / high. The span between the radiation doses of each two irradiation environments is not less than 100krad (Si), and the highest radiation dose is greater than 300krad (Si). The unified data is all 0 or all 1. When the radiation dose rate of the radiation environment is 50rad / s, the predetermined time is greater than or equal to 2000s. Each SRAM chip is tested no less than 3 times. Multiple power-on-average is taken to reduce interference factors in extreme special situations.

[0081] Preferably, after step S2, the power is turned off and a period of time is waited to eliminate residual interference of the data, and then the SRAM chip is powered on again.

[0082] Preferably, the aging imprint force model is

[0083]

[0084] Where Φ() is the standard normal cumulative distribution function, Ratio1 is the ratio of 1 to 0 in the initial value of the power-on after initialization, Ratio3 is the ratio of 1 to 0 in the initial value of the power-on after the second power-on, and σ noise is the noise impact factor, which depends on environmental factors and actual equipment conditions and is obtained through calibration, T is the scheduled time; F j represents the aging imprint strength F obtained in the jth testj , α is the radiation environment coefficient, dose is the radiation dose in the irradiation environment, V p 、V n They are the back gate voltages of the PMOS transistor and the NMOS transistor during the test.

[0085] Preferably, step S5 further comprises:

[0086] S51. The aging stamping force F of all SRAM chips in each group tested n times (each chip is tested the same number of times) j Take the average value as the aging imprint strength of the group of chips in the corresponding radiation environment;

[0087] S52. According to the aging stamping strength of the M group of SRAM chips, obtain the final aging stamping strength evaluation index F of the SRAM chip to be tested total ; said F total Obtained by the following formula

[0088]

[0089] Where M is the number of SRAM chips.

[0090] S53. According to the above F total Determine whether the final aging stamping force is within a preset range. If so, determine that the safety performance of the SRAM chip to be tested meets the standard, and output the test result that the safety performance of the SRAM chip to be tested is qualified; otherwise, determine that the safety performance of this type of SRAM chip to be tested cannot meet the use requirements.

[0091] Specifically, the preset range is determined according to the security level of the actual application scenario of the SRAM, which depends on the protection capability of the security system and the amount and confidentiality of the information stored in the SRAM.

[0092] Compared with Example 1, the method provided in this embodiment takes into account the time, back gate voltage and total dose effects at the same time, can more comprehensively test the aging imprint strength of the SRAM chip to be tested, and analyze from multiple angles which factors will affect the aging imprint strength; the method of writing all "0" or all "1" is used to count the changes in the data of the SRAM after aging imprinting, which can quantitatively analyze the aging imprint strength and facilitate subsequent data processing.

[0093] Example 3

[0094] The present invention also provides a SRAM chip safety performance evaluation system corresponding to embodiment 1 or 2, comprising a test board, an FPGA chip and a host computer connected in sequence. The FPGA chip and the host computer can communicate wirelessly.

[0095] The test board is used to connect to the SRAM chip to be tested, adjust the back gate voltages of all NMOS transistors and PMOS transistors in its storage array according to the control of the FPGA chip; and output the information stored in the storage array of the SRAM chip to be tested to the FPGA chip.

[0096] Through the above test board, each port of the SRAM chip to be tested is brought out.

[0097] The FPGA chip is used to send initialization instructions to the test board during testing, wherein the initialization instructions are used to set the back gate voltages of all NMOS transistors and PMOS transistors in the storage array of the SRAM chip to be tested to 0V; and, after the initialization is completed, send read and write instructions to the test board, and receive information stored in the storage array fed back by the test board; the information includes the number and ratio of 1s and 0s in the storage array.

[0098] The host computer is used to control the FPGA chip to power on the SRAM chip; and read the internal data information stored in the storage array of the SRAM chip to be tested through the FPGA chip, wherein the information includes the initial value of the first power-on after initialization and the initial value of the second power-on after re-powering on; and the initial value of the first power-on and the initial value of the second power-on are input into a user-defined aging imprint force model to obtain the aging imprint force of the SRAM chip under each irradiation environment, and obtain the evaluation result of whether the safety performance of the SRAM chip to be tested is good according to the aging imprint force of the SRAM chip to be tested under all the above irradiation environments.

[0099] It is worth noting that power-on is for each internal unit of the storage array of the SRAM chip. After power-on is completed, the storage array of the SRAM chip should complete the establishment of a steady state.

[0100] The SRAM chip includes a back-gate signal port, which is connected to the IO port of the FPGA chip. The back-gate voltage is controlled by controlling the level voltage of the IO port, thereby achieving a 0V setting of the back-gate voltage.

[0101] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0102] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for testing the safety performance of an SRAM chip, characterized in that: Includes steps: Power on a plurality of SRAM chips to be tested, initialize the back gate voltage of the storage array thereof, and obtain a power-on initial value after each SRAM chip to be tested is initialized; Writing unified data to all SRAM chips, grouping the SRAM chips after writing the unified data, setting different back gate voltages for each group, and keeping them in different irradiation environments for a predetermined time before powering off; Re-power on all SRAM chips to obtain the secondary power-on initial value of each SRAM chip after powering on again; The secondary power-on initial value and the corresponding primary power-on initial value of each SRAM chip in each group under different irradiation environments are respectively input into the aging imprint force model to obtain the aging imprint force of each SRAM chip in each group under different irradiation environments; According to the aging imprint strength of each SRAM chip in each group under the above-mentioned different irradiation environments, the safety performance test result of the SRAM chip to be tested is obtained.

2. The method for testing the safety performance of an SRAM chip according to claim 1, characterized in that: The power-on initial value is the ratio of the number of storage cells with a value of 1 to the number of storage cells with a value of 0 in the SRAM chip to be tested after power-on; The step of powering on a plurality of SRAM chips to be tested and initializing the back gate voltage of their storage arrays to obtain a power-on initial value of each SRAM chip to be tested after initialization comprises: Connect each SRAM chip to be tested to the test system respectively, and power on the SRAM chip through the test system; The back gate voltages of all NMOS transistors and PMOS transistors in the memory array of the SRAM chip are set to 0V, and the number and ratio of 1s and 0s in the memory array after initialization are counted; Repeat the above process n times, and calculate Rate1 according to the following formula as the initial value of each SRAM chip to be tested after initialization: Where N 1i is the number of storage array cells that are 1 in the i-th test, N 0i is the number of storage array cells that are 0 in the i-th test, and n is the number of repeated power-on initialization times.

3. The method for testing the safety performance of an SRAM chip according to claim 2, characterized in that: The test system includes a test board and an FPGA chip connected in sequence; The test board is used to connect to the SRAM chip to be tested and adjust the back gate voltages of all NMOS transistors and PMOS transistors in its storage array according to the control of the FPGA chip; And, outputting the information stored in the storage array of the SRAM chip to the FPGA chip; The FPGA chip is used to send initialization instructions to the test board during testing, wherein the initialization instructions are used to set the back gate voltages of all NMOS transistors and PMOS transistors in the storage array of the SRAM chip to 0V; and, after the initialization is completed, send read and write instructions to the test board, and receive information stored in the storage array fed back by the test board; the information includes the number and ratio of 1s and 0s in the storage array.

4. The method for testing the safety performance of an SRAM chip according to any one of claims 1 to 3, characterized in that: The grouping includes at least the following 5 groups: The grouping of NMOS transistors with negative bias and PMOS transistors with negative bias; The grouping of NMOS transistors is negatively biased and PMOS transistors is positively biased; A grouping of NMOS transistors with zero bias and PMOS transistors with zero bias; The grouping of NMOS transistors is forward biased and PMOS transistors is negative biased; The grouping of NMOS transistors forward biased and PMOS transistors forward biased; Furthermore, each group includes at least 15 SRAM chips.

5. The method for testing the safety performance of an SRAM chip according to claim 4, characterized in that: The irradiation environments include at least three types, the span of radiation doses between any two irradiation environments is not less than 100 krad, and the highest radiation dose is greater than 300 krad.

6. The method for testing the safety performance of an SRAM chip according to claim 5, characterized in that: The unified data is all 0 or all 1; When the radiation dose rate of the radiation environment is 50 rad / s, the predetermined time is greater than or equal to 2000 s.

7. The method for testing the safety performance of an SRAM chip according to claim 5 or 6, characterized in that: Each SRAM chip is tested no less than 3 times.

8. The method for testing the safety performance of an SRAM chip according to claim 7, characterized in that: The aging imprint force model is: Where Φ() is the standard normal cumulative distribution function, Ratio1 is the ratio of 1 to 0 in the initial value of power-on, Ratio3 is the ratio of 1 to 0 in the initial value of power-on twice, σ noise is the noise impact factor, T is the scheduled time; F j represents the aging imprint strength F obtained in the jth test j , α is the radiation environment coefficient, dose is the radiation dose in the irradiation environment, V p 、V n They are the back gate voltages of the PMOS transistor and the NMOS transistor during the test.

9. The method for testing the safety performance of an SRAM chip according to claim 1, characterized in that: The step of obtaining the safety performance test result of the SRAM chip to be tested according to the aging imprint strength of each SRAM chip in each group under the above-mentioned different irradiation environments comprises: The aging stamping force F of all SRAM chips tested in each group j Take the average value as the aging imprint strength of the group of chips in the corresponding radiation environment; According to the aging stamping force of the M group of SRAM chips, the final aging stamping force F of the SRAM chip to be tested is obtained. total ; If the final aging stamping force F total If the test result is within the preset range, the test result indicating that the safety performance of the SRAM chip to be tested is qualified is output.

10. The method for testing the safety performance of an SRAM chip according to claim 9, characterized in that: The F total Obtained by the following formula Where M is the number of SRAM chips.

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