Changing the inverter layout of the gate-level truncation design

Abstract

The present invention provides an inverter layout with a modified gate-level cutoff design, comprising a parallel pMOS pattern and an nMOS pattern; a first and a second dummy gate pattern, both located on either side of the pMOS pattern and the nMOS pattern; a main gate pattern located on the pMOS pattern and the nMOS pattern and between the first and the second dummy gate patterns; a first and a second pad pattern, one end of each located on the pMOS pattern and the nMOS pattern and between the first dummy gate pattern and the main gate pattern; a third pad pattern with two ends located on the pMOS pattern and the nMOS pattern and between the main gate pattern and the nMOS pattern; and a shear pattern located on the first and the second dummy gate patterns and the main gate pattern. The present invention improves device speed and steady-state current testing by shearing the main gate on the NMOS and the dummy gate on the PMOS, as the stress of the interlayer dielectric layer on the FinFET device affects the gate shearing of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an inverter layout with a gate-level cutoff design changed. Background Art

[0002] An inverter reverses the phase of an input signal by 180 degrees. This circuit is used in analog circuits, such as audio amplifiers and clock oscillators. Inverters are frequently used in electronic circuit design. A CMOS (complementary metal oxide semiconductor) inverter circuit consists of two enhancement-mode MOS field-effect transistors. A typical TTL (transistor-transistor logic) NAND gate circuit consists of an input stage, an intermediate stage, and an output stage.

[0003] The existing CMOS inverter structure is as follows: Figure 1 As shown, its layout structure is as follows Figure 2 As shown in FIG, FinFET (Fin Field Effect Transistor) has strong stress due to the oxide generated by chemical vapor deposition, which affects the speed and steady-state current test (IDDQ) of the device.

[0004] To this end, a new cut-gate layout design on FinFET inverters is needed to improve device speed and steady-state current testing. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide an inverter layout with a changed gate-level cutoff design, so as to solve the problem in the prior art that FinFET, due to the strong stress of the oxide generated by chemical vapor deposition, will produce gate defects when the gate is sheared, which will affect the speed and steady-state current test of the device.

[0006] To achieve the above and other related objectives, the present invention provides an inverter layout with a modified gate-level truncation design, comprising:

[0007] Parallel pMOS and nMOS patterns;

[0008] a first dummy gate pattern and a second dummy gate pattern respectively located on both sides of the pMOS pattern and the nMOS pattern;

[0009] a main gate pattern located on the pMOS pattern and the nMOS pattern and between the first and second dummy gate patterns;

[0010] First and second pad patterns, one end of each of which is located on the pMOS pattern and the nMOS pattern, and is located between the first dummy gate pattern and the main gate pattern; and a third pad pattern, two ends of each of which is located on the pMOS pattern and the nMOS pattern, and is located between the main gate pattern and the nMOS pattern.

[0011] The cutout patterns are respectively located on the first and second dummy gate patterns and the main gate pattern.

[0012] Preferably, the pMOS pattern, the nMOS pattern, and the main gate pattern have the same shape.

[0013] Preferably, the pMOS pattern, the main gate pattern and the nMOS pattern are distributed in sequence at equal intervals.

[0014] Preferably, the first pad pattern is used to define the position of the power supply voltage in the inverter, the second pad pattern is used to define the position of the ground in the inverter, and the third pad pattern is used to connect the pMOS pattern and the nMOS pattern.

[0015] Preferably, the first, second and third pad patterns are all provided with contact hole patterns distributed at equal intervals.

[0016] Preferably, the first dummy gate pattern and the first pad pattern share a first cutout pattern.

[0017] Preferably, the main gate pattern and the second pad pattern share a second cutout pattern.

[0018] Preferably, a third shearing pattern is provided at one end of the second dummy gate pattern.

[0019] Preferably, the third shearing pattern is located at an end of the second dummy gate pattern away from the second shearing pattern.

[0020] Preferably, the graphic shape of the layout is a rectangle.

[0021] As described above, the inverter layout of the present invention with a changed gate-level truncation design has the following beneficial effects:

[0022] Since the stress of the interlayer dielectric layer on the FinFET device affects the gate cutting of the device, the present invention improves the device speed and steady-state current test by cutting the main gate on the NMOS and cutting the dummy gate on the PMOS. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Shown is a schematic diagram of an inverter circuit in the prior art;

[0024] Figure 2 Shown is a schematic diagram of an inverter layout in the prior art;

[0025] Figure 3 Shown is a schematic diagram of the inverter layout of the present invention;

[0026] Figure 4It is a schematic diagram showing the performance improvement of the present invention. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] See also Figure 3 The present invention provides an inverter layout with a gate-level truncation design changed, comprising:

[0029] The parallel pMOS pattern 10 and nMOS pattern 11 are used to define the positions of the pMOS and nMOS of the inverter. Usually, in the layout design, the pMOS pattern 10 and the nMOS pattern 11 are two parallel long strips, and the distance between the two patterns is not less than the minimum size in the layout design.

[0030] The first and second dummy gate patterns (12, 13) are respectively located on both sides of the pMOS pattern 10 and the nMOS pattern 11, and the first and second dummy gate patterns (12, 13) are used to define the positions of the first and second dummy gates of the inverter;

[0031] A main gate pattern 17 located on the pMOS pattern 10 and the nMOS pattern 11 and between the first and second dummy gate patterns (12, 13);

[0032] In an optional embodiment, the shapes of the pMOS pattern 10 , the nMOS pattern 11 , and the main gate pattern 17 are all the same.

[0033] In an optional embodiment, the pMOS pattern 10 , the main gate pattern 17 and the nMOS pattern 11 are distributed in sequence at equal intervals.

[0034] First and second bonding pad patterns, each having one end located on the pMOS pattern 10 and the nMOS pattern 11, and located between the first dummy gate pattern 12 and the main gate pattern 17; and third bonding pad pattern 16, each having two ends located on the pMOS pattern 10 and the nMOS pattern 11, and located between the main gate pattern 17 and the nMOS pattern 11;

[0035] In an optional embodiment, the first pad pattern 14 is used to define the position of the power supply voltage in the inverter, the second pad pattern 15 is used to define the ground position in the inverter, and the third pad pattern 16 is used to connect the pMOS pattern 10 and the nMOS pattern 11.

[0036] In an optional embodiment, the first, second and third pad patterns are all provided with equidistantly distributed contact hole patterns 21 .

[0037] Specifically, both ends of the first pad pattern 14 and the second pad pattern 15 are provided with contact hole patterns 21, and the third pad pattern 16 is provided with three contact hole patterns 21 distributed at equal intervals.

[0038] The shearing patterns are respectively located on the first and second dummy gate patterns (12, 13) and the main gate pattern 17. During the device forming process, an interlayer dielectric layer needs to be generated by chemical vapor deposition. The interlayer dielectric layer is usually an oxide such as silicon dioxide. Since the interlayer dielectric layer has stress, it will affect the performance of the device. Therefore, it is necessary to define the shearing position through the shearing pattern.

[0039] In an optional embodiment, the first dummy gate pattern 12 and the first pad pattern 14 share the first cutout pattern 18 .

[0040] In an optional embodiment, the main gate pattern 17 and the second pad pattern 15 share the second cutout pattern 19 .

[0041] In an optional embodiment, a third shearing pattern 20 is provided at one end of the second dummy gate pattern 13 .

[0042] In an optional embodiment, when the distance between the main gate pattern 17 and the second dummy gate pattern 13 is small, in order to avoid overlap between the second shearing pattern 19 and the third shearing pattern 20, the third shearing pattern 20 is located at an end of the second dummy gate pattern 13 away from the second shearing pattern 19.

[0043] In an optional embodiment, the graphic shape of the layout is a rectangle.

[0044] In an alternative embodiment, see Figure 4 , BSL (baseline) is the relationship between device speed and IDDQ in the prior art. The relationship between inverter speed and IDDQ obtained by the layout of this embodiment is shown in (Development), which increases the speed of the device and improves the performance of the device.

[0045] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0046] In summary, the present invention addresses the impact of interlayer dielectric stress on FinFET device gate cutting by cutting the main gate in NMOS and the dummy gate in PMOS, improving device speed and steady-state current testing. Therefore, the present invention effectively overcomes the shortcomings of existing technologies and has high industrial application value.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. An inverter layout with a gate-level truncation design changed, characterized in that: include: Parallel pMOS and nMOS patterns; a first dummy gate pattern and a second dummy gate pattern respectively located on both sides of the pMOS pattern and the nMOS pattern; a main gate pattern located on the pMOS pattern and the nMOS pattern and between the first and second dummy gate patterns; a first pad pattern located between the first dummy gate pattern and the main gate pattern and having one end located on the pMOS pattern; a second pad pattern located between the first dummy gate pattern and the main gate pattern and having one end located on the nMOS pattern; a third pad pattern located between the main gate pattern and the second dummy gate pattern, with two ends thereof respectively located on the pMOS pattern and the nMOS pattern; The shearing patterns are respectively located on the first and second dummy gate patterns and the main gate pattern, wherein the shearing patterns include: a first shearing pattern commonly used for the first dummy gate pattern and the first pad pattern; a second shearing pattern commonly used for the main gate pattern and the second pad pattern; and a third shearing pattern arranged at one end of the second dummy gate pattern.

2. The inverter layout with a gate-level truncation design modified according to claim 1, wherein: The pMOS pattern, the nMOS pattern, and the main gate pattern all have the same shape.

3. The inverter layout with a gate-level truncation design modified according to claim 1, wherein: The pMOS pattern, the main gate pattern and the nMOS pattern are distributed in sequence with equal intervals.

4. The inverter layout with a gate-level cutoff design modified according to claim 1, wherein: The first pad pattern is used to define a position of a power supply voltage in the inverter, the second pad pattern is used to define a position of a ground in the inverter, and the third pad pattern is used to connect the pMOS pattern and the nMOS pattern.

5. The inverter layout with a gate-level truncation design modified according to claim 1, wherein: The first, second and third pad patterns are all provided with contact hole patterns distributed at equal intervals.

6. The inverter layout with a gate-level truncation design modified according to claim 1, wherein: The third shearing pattern is located at an end of the second dummy gate pattern away from the second shearing pattern.

7. The inverter layout with a gate-level cutoff design changed according to any one of claims 1 to 6, wherein: The graphic shape of the layout is a rectangle.

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