Integrated chip and method of forming the same

Abstract

An integrated chip includes a first transistor and a second transistor arranged above a substrate. The first transistor includes a plurality of first channel structures extending between a first source / drain region and a second source / drain region. A first gate electrode is arranged between the first channel structures, and a first protective layer is arranged above a topmost one of the first channel structures. The second transistor includes a plurality of second channel structures extending between the second source / drain region and a third source / drain region. A second gate electrode is arranged between the second channel structures, and a second protective layer is arranged above a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first channel structures and the second channel structures, and a contact plug structure coupled to the second source / drain region and arranged above the first gate electrode and the second gate electrode.

Description

Technical Field

[0001] This invention relates to an integrated chip and a method for forming the same. Background Technology

[0002] As technology rapidly advances, engineers strive to make devices smaller and more complex in order to improve and develop more efficient, reliable, and functional electronic devices. One way to achieve these goals is through improving transistor design, as electronic devices comprise a large number of transistors working together to perform their functions. Overall electronic device performance can benefit from transistors that are smaller, consume less power, and have faster switching speeds, for example, in both the horizontal and vertical directions. Summary of the Invention

[0003] This invention provides an integrated chip, including: a first transistor, a second transistor, a first interconnect structure, and a contact plug structure. The first transistor is disposed above a substrate and includes: a plurality of first channel structures extending between a first source / drain region and a second source / drain region; a first gate electrode disposed between the first channel structures; and a first protective layer disposed above the topmost first channel structure. The second transistor is disposed above the substrate and next to the first transistor and includes: a plurality of second channel structures extending between a second source / drain region and a third source / drain region; a second gate electrode disposed between the second channel structures; and a second protective layer disposed above the topmost second channel structure. The first interconnect structure is coupled to the first gate electrode and the second gate electrode and is disposed between the substrate and the first and second channel structures. The contact plug structure is coupled to the second source / drain region and is disposed above the first gate electrode and the second gate electrode.

[0004] This invention provides an integrated chip, comprising: a first interconnect structure located above a substrate; a first channel structure disposed above and coupled to the first interconnect structure; a second channel structure disposed above and coupled to the first interconnect structure; a source / drain region disposed between the first channel structure and the second channel structure; a first protective layer and a second protective layer disposed above the first channel structure and the second channel structure, respectively; a contact plug structure disposed above and coupled to the source / drain region; and a memory structure disposed above and coupled to the contact plug structure.

[0005] This invention provides a method for forming an integrated chip, comprising: forming a first protective layer over a first substrate and forming a second protective layer over the first substrate; forming a first nanosheet field-effect transistor (NSFET) disposed over the first protective layer, wherein the first nanosheet field-effect transistor includes a first nanosheet channel structure, a first source / drain region, a second source / drain region, and a first gate electrode; forming a second nanosheet field-effect transistor over the second protective layer, wherein the second nanosheet field-effect transistor includes a second nanosheet channel structure, a second source / drain region, a third source / drain region, and a second gate electrode; forming a first interconnect structure over the first nanosheet field-effect transistor and the second nanosheet field-effect transistor, wherein the first interconnect structure includes interconnect wires and interconnect vias embedded in the interconnect dielectric structure; and forming a... A bonding layer; bonding a carrier substrate to the bonding layer; flipping the first substrate to pattern the back side of the first substrate; completely removing the first substrate to expose the first source / drain region, the second source / drain region, and the third source / drain region, as well as the first protective layer and the second protective layer; forming a dielectric layer over the first source / drain region, the second source / drain region, and the third source / drain region, as well as the first protective layer and the second protective layer; forming a contact plug structure to extend through the dielectric layer and couple to the second source / drain region disposed between the first nanosheet field-effect transistor and the second nanosheet field-effect transistor; forming a memory structure over the contact plug structure, and the memory structure being coupled to the contact plug structure; and forming a second interconnect structure over the memory structure, and the second interconnect structure being coupled to the memory structure. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, the various aspects of this disclosure are best understood in the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 Cross-sectional views of some embodiments of an integrated chip are shown, the integrated chip having a first interconnect structure disposed below a nanosheet field effect transistor (NSFET) and a memory structure disposed above the NSFET and coupled to the NSFET using a contact plug structure.

[0008] Figure 2ACross-sectional views of some other embodiments of an integrated chip are shown, the integrated chip having a first interconnect structure disposed below the NSFET, a memory structure disposed above the NSFET, a second interconnect structure disposed above the memory structure, and contact vias coupling the first interconnect structure to the second interconnect structure.

[0009] Figure 2B Show Figure 2A Cross-sectional views of some alternative embodiments, wherein a fin field-effect transistor (finFET) instead of an NSFET is arranged between the memory structure and the first interconnect structure.

[0010] Figures 3 to 23 Cross-sectional views of some embodiments of a method for forming a first interconnect structure on a first side of an NSFET and a memory structure on a second side of an NSFET are shown.

[0011] Figure 24 Show Figures 3 to 23 The flowcharts show some embodiments of the method illustrated. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not, in itself, define a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature relative to another element(s) shown in the diagrams. In addition to the orientations depicted in the diagrams, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0014] In some embodiments, the integrated circuit may include a plurality of transistor devices disposed above the same substrate. In some configurations, an interconnect structure may be disposed above one or more transistor devices on the front side of the same substrate. The interconnect structure may include a network of interconnect wires and interconnect vias embedded in an interconnect dielectric structure. The interconnect wires and interconnect vias may be electrically coupled to one or more of the plurality of transistor devices.

[0015] In integrated circuits including memory devices, memory structures (e.g., magnetoresistive random access memory cells, metal-insulator-metal memory cells, ferroelectric random access memory cells, phase-change random access memory cells, resistive random access memory cells, etc.) can be arranged within interconnect structures and coupled to at least one of a plurality of transistor devices. However, due to physical and / or electrical limitations to prevent signal interference, for example, the memory structures can conventionally be arranged between interconnect conductors 5 and 6. Because so many interconnect conductors and interconnect vias are arranged between the memory structures and one or more transistors, the height of the integrated circuit increases, which reduces device density and makes the distance of signals traveling between the memory structures and one or more transistors potentially inefficient.

[0016] Various embodiments of this disclosure are directed to an integrated chip including a first transistor and a second transistor, the first transistor and the second transistor being spaced apart by a second source / drain region and disposed above a carrier substrate. In some embodiments, the first transistor and the second transistor may be nanosheet field-effect transistors (NSFETs), fin field-effect transistors (FFETs), or some other type of transistor. A first interconnect structure is disposed between the carrier substrate and the first transistor and the second transistor. A contact plug structure is disposed directly above and electrically coupled to the second source / drain region, and a memory structure is disposed directly above and electrically coupled to the contact plug structure. In some embodiments, a second interconnect structure may be disposed directly above and coupled to the memory structure.

[0017] Therefore, in various embodiments of this disclosure, the front and back sides of the first and second transistors are utilized to reduce the size of the first interconnect structure and / or the second interconnect structure in the vertical direction to increase device density. Furthermore, contact plug structures are directly disposed between the first and / or second transistors and the memory structure, thereby reducing the distance of signals traveling between the first and / or second transistors and the memory structure to increase the reliability of the integrated chip.

[0018] Figure 1A cross-sectional view 100 shows some embodiments of an integrated chip, which includes a memory structure disposed above a nanosheet field-effect transistor (NSFET) and a first interconnect structure disposed below the NSFET.

[0019] The integrated chip in cross-sectional view 100 includes a first interconnect structure 107 disposed above a carrier substrate 102. In some embodiments, the first interconnect structure 107 is bonded to the carrier substrate 102 via a first bonding layer 104 and a second bonding layer 106. The first interconnect structure 107 may include interconnect conductors 110 and interconnect vias 108 disposed within an interconnect dielectric layer 112 and an interconnect etch stop layer 114. In some embodiments, from Figure 1 Viewed from the angle of the cross-sectional view 100, the first interconnect structure 107 is arranged above the carrier substrate 102, and the interconnect vias 108 of the first interconnect structure 107 may each have an upper surface that is narrower than its bottom surface.

[0020] In some embodiments, a first nanosheet field-effect transistor (NSFET) 118 is disposed above a first interconnect structure 107, and a second NSFET 120 is disposed above the first interconnect structure 107 and adjacent to the first NSFET 118. In some embodiments, the first NSFET and the second NSFET each include a channel structure 121 having a nanosheet channel structure 122 and a gate electrode 124 disposed between the nanosheet channel structures 122. The gate electrode 124 includes a plurality of portions disposed directly between the nanosheet channel structures 122 and a portion disposed below the bottommost nanosheet channel structure 122 and coupled to one of the interconnect vias 108 of the first interconnect structure 107. In some embodiments, an internal spacer structure 128 surrounds the outer sidewalls of the plurality of portions of the gate electrode 124 disposed directly between the nanosheet channel structures 122. Furthermore, in some embodiments, the first gate sidewall structure 132 is disposed on the outer sidewall of a portion of the gate electrode 124 directly disposed between the bottommost nanosheet channel structure 122 and the first interconnect structure 107 in the nanosheet channel structure 122, and the second gate sidewall structure 130 is disposed directly on the outer sidewall of the first gate sidewall structure 132. In addition, in some embodiments, the first gate sidewall structure 132 and the second gate sidewall structure 130 are disposed within and laterally surrounded by the gate dielectric layer 116.

[0021] In some embodiments, the first NSFET 118 includes a first source / drain region 126a and a second source / drain region 126b, wherein a nanosheet channel structure 122 of the first NSFET 118 extends between the first source / drain region 126a and the second source / drain region 126b. In some embodiments, the second NSFET 120 includes a second source / drain region 126b and a third source / drain region 126c, wherein a nanosheet channel structure 122 of the second NSFET 120 extends between the second source / drain region 126b and the third source / drain region 126c. Therefore, in some embodiments, the first NSFET 118 and the second NSFET 120 share the second source / drain region 126b. Furthermore, in some embodiments, the first source / drain region 126a, the second source / drain region 126b, and the third source / drain region 126c are spaced apart from the first interconnect structure 107 by a gate dielectric layer 116.

[0022] In some embodiments, the first NSFET 118 and the second NSFET 120 each include a protective layer 134 disposed above the topmost nanosheet channel structure 122 in the nanosheet channel structure 122. In such embodiments, the protective layer 134 may be centered above the topmost nanosheet channel structure 122 in the nanosheet channel structure 122 and include a width substantially the same as the topmost nanosheet channel structure 122 in the nanosheet channel structure 122. In some embodiments, the protective layer 134 may include, for example, a dielectric material, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitrogen, or some other suitable dielectric material. Thus, in some embodiments, the topmost nanosheet channel structure 122 in the nanosheet channel structure 122 has a bottom surface that directly contacts the gate electrode 124 and a top surface that directly contacts the protective layer 134.

[0023] In some embodiments, Figure 1The integrated chip further includes a contact dielectric layer 140 disposed above the first NSFET 118 and the second NSFET 120, and a contact plug structure 138 extending through the contact dielectric layer 140 and directly contacting the second source / drain region 126b. Therefore, in some embodiments, the contact plug structure 138 is electrically coupled to the first NSFET 118 and the second NSFET 120. Furthermore, in some embodiments, the contact plug structure 138 directly overlies the protective layer 134 of the first NSFET 118 and the second NSFET 120, and also extends below the protective layer 134 of the first NSFET 118 and the second NSFET 120. In some embodiments, the contact plug structure 138 is also directly disposed between the topmost nanosheet channel structures 122 of the nanosheet channel structures 122 of the first NSFET 118 and the second NSFET 120. In some embodiments, a barrier structure 136 is disposed directly between the contact plug structure 138 and the topmost nanosheet channel structure 122 of the nanosheet channel structures 122 of the first NSFET 118 and the second NSFET 120 to provide protection for the topmost nanosheet channel structure 122 of the nanosheet channel structures 122 of the first NSFET 118 and the second NSFET 120 during the formation of the contact plug structure 138. Similarly, in some embodiments, a protective layer 134 provides protection for the nanosheet channel structure 122 during the formation of the contact plug structure 138. In some embodiments, the contact plug structure 138 comprises a conductive material, such as tungsten, ruthenium, cobalt, or some other conductive material having low resistivity. In some embodiments, the contact plug structure 138 has a first height h1 extending between the memory structure 142 and the second source / drain region 126b. In some embodiments, the first height h1 may be in the range of, for example, about 10 nanometers to about 300 nanometers.

[0024] In some embodiments, the memory structure 142 is disposed directly over the contact plug structure 138, such that the contact plug structure 138 electrically couples the memory structure 142 to the first NSFET 118 and the second NSFET 120. In some embodiments, the memory structure 142 may include a bottom electrode 144 disposed over the contact plug structure 138, a top electrode 148 disposed over the bottom electrode 144, and a memory storage structure 146 disposed between the bottom electrode 144 and the top electrode 148. In some embodiments, the memory structure 142 may include a magnetoresistive random access memory cell, a metal-insulator-metal memory cell, a ferroelectric random access memory cell, a phase-change random access memory cell, a resistive random access memory cell, or some other memory device. In some embodiments, the memory structure 142 is surrounded by a memory dielectric structure 143 disposed over the contact dielectric layer 140.

[0025] In some embodiments, the second interconnect structure 150 may be disposed above and coupled to the memory structure 142. In such embodiments, the second interconnect structure 150 may include interconnect wires 110 and interconnect vias 108 embedded in the interconnect dielectric layer 112 and the interconnect etch stop layer 114. In some embodiments, from Figure 1 Viewed from the angle of the cross-sectional view 100, the second interconnect structure 150 is arranged above the memory structure 142 and the carrier substrate 102, and the interconnect vias 108 of the second interconnect structure 150 may each have an upper surface that is wider than its bottom surface.

[0026] Therefore, in some embodiments, the memory structure 142 is arranged above the first NSFET 118 and the second NSFET 120, and the first interconnect structure 107 is arranged below the first NSFET 118 and the second NSFET 120, so that both sides of the first NSFET 118 and the second NSFET 120 are utilized, thereby reducing... Figure 1 The overall height of the integrated chip. Furthermore, in some embodiments, the contact plug structure 138 is directly disposed between the memory structure 1472 and the first NSFET 118 and the second NSFET 120 to reduce the distance for signals (e.g., current, voltage) traveling between the first NSFET 118 and / or the second NSFET 120 and the memory structure 142, thereby increasing the signal travel efficiency and overall reliability of the integrated chip.

[0027] Figure 2A Cross-sectional view 200A shows some embodiments of an integrated chip, which includes a memory structure disposed above an NSFET and a first interconnect structure disposed below the NSFET.

[0028] like Figure 2A As shown in the cross-sectional view 200A, in some embodiments, Figure 2AThe memory structure 142 may correspond to a magnetoresistive random-access memory (MRAM) cell or device. In such embodiments, a magnetic tunnel junction (MTJ) stack 202 may be disposed between a top electrode 148 and a bottom electrode 144. In some embodiments, the MTJ stack 202 may include a thin insulating layer 208 disposed between a bottom magnetic layer 204 and a top magnetic layer 206. Data can be stored in the MTJ stack 202 using its magnetic orientation. In some embodiments, a first MRAM sidewall structure 210 may be disposed on an outer sidewall of the memory structure 142, and a second MRAM sidewall structure 212 may be disposed on an outer sidewall of the first MRAM sidewall structure 210 and / or an outer sidewall of the memory structure 142.

[0029] In some embodiments, the silicide layer 216 is disposed directly between the contact plug structure 138 and the second source / drain region 126b. In some embodiments, the silicide layer 216 may comprise, for example, cobalt silicide, titanium silicide, nickel silicide, or some other suitable metal silicide material. In such embodiments, the silicide layer 216 may assist in coupling the second source / drain region 126b to the contact plug structure 138.

[0030] In some embodiments, the first bonding layer 104 is used instead of the second bonding layer. Figure 1 The first interconnect structure 106 is directly disposed between the carrier substrate 102 and the first interconnect structure 107. Furthermore, in some embodiments, the first interconnect structure 107 may be electrically coupled to the second interconnect structure 150. In such embodiments, an elongated via structure 214 may extend through a dielectric layer (e.g., interconnect dielectric layer 112, gate dielectric layer 116, contact dielectric layer 140, memory dielectric structure 143, etc.) to directly couple the first interconnect structure 107 to the second interconnect structure 150. It should be understood that in other embodiments, multiple wires and vias and / or some other structures may be used to directly couple the first interconnect structure 107 and the second interconnect structure 150.

[0031] Figure 2B Show Figure 2A Cross-sectional Figure 200B shows some alternative embodiments of cross-sectional Figure 200A, in which the integrated chip includes a FinFET instead of an NSFET.

[0032] like Figure 2BAs illustrated in cross-sectional view 200B, in some embodiments, the integrated chip includes a first finFET 218 and a second finFET 220 disposed above the first interconnect structure 107 and below the memory structure 142. In such embodiments, the first finFET 218 and the second finFET 220 may each include a fin channel structure 224 extending continuously between the gate electrode 124 and the guard layer 134. In some embodiments, the first finFET 218 and the second finFET 220 may be used instead of the first NSFET and the second NSFET (NSFET). Figure 1 118, 120) to reduce manufacturing complexity; however, in some embodiments, the first NSFET and the second NSFET ( Figure 1 FinFETs 218 and 220 can offer certain advantages over the first FinFET 218 and the second FinFET 220, such as faster switching speeds.

[0033] Figures 3 to 23 Cross-sectional views 300 to 2300 illustrate some embodiments of a method for forming a first interconnect structure below a nanosheet field-effect transistor (NSFET) and a memory structure above the NSFET. Although relative to the method description... Figures 3 to 23 However, it should be understood that Figures 3 to 23 The structures disclosed herein are not limited to this method, but rather can be used independently of the method as structures.

[0034] like Figure 3 As illustrated in cross-sectional view 300, a first substrate 302 is provided. In some embodiments, the first substrate 302 may be a silicon-on-insulator (SOI) substrate. In such embodiments, the first substrate 302 may include a base layer 304, an insulating layer 306 disposed over the base layer 304, and an active layer 308 disposed over the insulating layer 306. In some embodiments, the base layer 304 and the active layer 308 may include semiconductor materials, such as silicon, germanium, etc. In some other embodiments, the first substrate 302 may be a single semiconductor substrate or a wafer.

[0035] like Figure 4As illustrated in cross-sectional view 400, a semiconductor layer stack 402 may be formed over a first substrate 302. The semiconductor layer stack 402 may include spacer layers 406 and semiconductor layers 404 arranged in an alternating sequence. In other words, each of the semiconductor layers 404 may be disposed between a lower spacer layer and an upper spacer layer in the spacer layers 406. In some embodiments, the spacer layers 406 comprise a first material, and the semiconductor layers 404 comprise a second material different from the first material. In some embodiments, for example, the first material of the spacer layers 406 comprises germanium-silicon or germanium, while the second material of the semiconductor layers 404 comprises silicon. In some embodiments, the bottommost layer of the semiconductor layer stack 402 is a bottommost spacer layer 406b. In such embodiments, the bottommost spacer layer 406b directly contacts the active layer 308 of the first substrate 302. In some embodiments, the semiconductor layers 404 and spacer layers 406 are formed by an epitaxial growth process.

[0036] like Figure 5 As illustrated in cross-sectional view 500, in some embodiments, a first virtual gate structure 502 and a second virtual gate structure 504 are formed over a semiconductor layer stack 402. In some embodiments, the first virtual gate structure 502 and the second virtual gate structure 504 include a virtual interface layer 506 disposed over the semiconductor layer stack 402, a virtual gate electrode 510 disposed over the virtual interface layer 506, and a virtual masking structure 508 disposed over the virtual gate electrode 510. In some embodiments, a conformal first gate layer 512 is continuously formed over the first virtual gate structure 502, the second virtual gate structure 504, and the semiconductor layer stack 402. In some embodiments, the first virtual gate structure 502 and the second virtual gate structure 504 are spaced apart by a first distance d1. In some embodiments, the first distance d1 is in the range of, for example, about 2.5 nanometers to about 100 nanometers.

[0037] In some embodiments, the virtual interface layer 506 of the first virtual gate structure 502 and the second virtual gate structure 504 may include, for example, a dielectric material, such as a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), or some other suitable material. In some embodiments, the virtual gate electrode 510 may include, for example, polysilicon. In some embodiments, the virtual interface layer 506 and the virtual gate electrode 510 may be formed by means of thermal oxidation and / or deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), etc.), followed by a removal process according to the virtual mask structure 508. In some embodiments, the virtual mask structure 508 may be formed using photolithography and removal (e.g., etching) processes. In some embodiments, the virtual mask structure 508 may include a photoresist or a hard mask material. In some embodiments, a conformal first gate layer 512 is formed over a virtual masking structure 508 by means of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the conformal first gate layer 512 may include an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), or some other suitable dielectric material.

[0038] like Figure 6 As illustrated in cross-sectional view 600, in some embodiments, a removal process may be performed based on a first dummy gate structure 502 and a second dummy gate structure 504 to remove the semiconductor layer stack ( Figure 5 The upper portion of 402) thereby forms an upper patterned semiconductor layer stack 602 directly disposed beneath the first virtual gate structure 502 and the second virtual gate structure 504. In such embodiments, Figure 6 The removal process, for example, is time-controlled, making... Figure 6 The removal process does not completely remove the bottom semiconductor layer 404b. Therefore, in Figure 6 After the removal process, the bottom spacer layer 406b is not removed and is completely covered by the bottom semiconductor layer 404b.

[0039] In some embodiments, Figure 6 The removal process may be or include etching processes, such as dry etching. It can also be performed generally in the vertical direction. Figure 6 The removal process. Furthermore, in some embodiments, Figure 6The removal process can remove part of the conformal first gate layer ( Figure 5 512), to form a first gate sidewall structure 132 surrounding the outermost sidewalls of the first virtual gate structure 502 and the second virtual gate structure 504. Furthermore, in some embodiments, the virtual masking structure 508 can substantially resist penetration through... Figure 6 The removal process is used to remove [the pollutants].

[0040] like Figure 7 As illustrated in cross-sectional view 700, an internal spacer structure 128 is formed on the outermost sidewall of spacer layer 406. In some embodiments, a lateral removal process is performed on the outer portion of spacer layer 406 to reduce the width of spacer layer 406 before forming the internal spacer structure 128. In some embodiments, the lateral removal process may include an isotropic etching process. Furthermore, in some embodiments, semiconductor layer 404 is not affected by the lateral removal process. Next, in some embodiments, internal spacer material is formed over the bottommost semiconductor layer 404b and over and around the upper patterned semiconductor layer stack 602. In some embodiments, a vertical etching process may then be performed to remove portions of the internal spacer material not disposed on the outer sidewall of spacer layer 406, thereby forming the internal spacer structure 128.

[0041] like Figure 8 As illustrated in cross-sectional view 800, in some embodiments, a removal process is performed to remove a portion of the bottommost semiconductor layer that is not located directly beneath the first dummy gate structure 502 or the second dummy gate structure 504. Figure 7 404b) and part of the bottommost spacer layer ( Figure 7 (406b). In some embodiments, Figure 8 The removal process includes an etching process performed generally in the vertical direction. In some embodiments, Figure 8 The removal process can also remove part of the active layer 308 of the first substrate 302.

[0042] exist Figure 8 After the removal process, the channel structure 121 is formed directly beneath the first dummy gate structure 502 and the second dummy gate structure 504. In some embodiments, the channel structure 121 may include a semiconductor layer ( Figure 7 The nanosheet channel structure 122 is formed by the 404 nanosheet channel structure. It should be understood that in some embodiments, each channel structure 121 may include more than four or fewer than four nanosheet channel structures 122. In some embodiments, the bottommost nanosheet channel structure 122b may be spaced apart from the first substrate 302 by a bottommost spacer layer 406b. The bottommost spacer layer 406b does not include the inner spacer structure 128.

[0043] like Figure 9As illustrated in cross-sectional view 900, in some embodiments, the bottommost spacer layer can be selectively removed by a removal process. Figure 8 (406b), and the protective layer 134 can be directly formed between the bottommost nanosheet channel structure 122b and the first substrate 302. In some embodiments, Figure 9 The removal process includes isotropic etching processes (e.g., wet etching, dry etching) to completely remove the bottommost spacer layer. Figure 8 406b). Although the spacer layer 406 arranged above the bottommost nanosheet channel structure 122b includes the bottommost spacer layer ( Figure 8 The same material as 406b), but the internal spacer structure 128 protects the spacer layer 406 arranged above the bottommost nanosheet channel structure 122b from the passage of... Figure 9 The removal process removes the pollutants.

[0044] After removing the bottommost spacer layer ( Figure 8 Following step 406b), the protective layer 134 can be formed by first forming a protective material above the first substrate 302 and directly between the active layer 308 of the first substrate 302 and the bottommost nanosheet channel structure 122b. Next, in some embodiments, an etching process can be performed according to the first dummy gate structure 502 and the second dummy gate structure 504 to remove a portion of the protective material not located directly below the first dummy gate structure 502 and the second dummy gate structure 504, thereby forming the protective layer 134.

[0045] In some embodiments, the protective layer 134 may include the same material as the internal spacer structure 128. In other embodiments, the protective layer 134 may include a different material than the internal spacer structure 128. In some embodiments, the protective layer 134 may include, for example, a dielectric material, such as silicon nitride, silicon oxynitride, silicon nitride carbon, or some other suitable dielectric material.

[0046] like Figure 10As illustrated in cross-sectional view 1000, in some embodiments, a first source / drain region 126a, a second source / drain region 126b, and a third source / drain region 126c are formed on an exposed portion of the active layer 308 of the first substrate 302. In some embodiments, the first source / drain region 126a, the second source / drain region 126b, and the third source / drain region 126c extend from the first substrate 302 over the topmost nanosheet channel structure 122 in the nanosheet channel structure 122. Furthermore, the first source / drain region 126a, the second source / drain region 126b, and the third source / drain region 126c directly contact the nanosheet channel structure 122. In some embodiments, the first source / drain region 126a, the second source / drain region 126b, and the third source / drain region 126c are formed by an epitaxial growth process and comprise semiconductor material. For example, in some embodiments, the first source / drain region 126a, the second source / drain region 126b, and the third source / drain region 126c comprise silicon, germanium, or silicon-germanium.

[0047] like Figure 11 As illustrated in cross-sectional view 1100, in some embodiments, a gate dielectric layer 116 is formed on the first source / drain region 126a, the second source / drain region 126b, and the third source / drain region 126c; and a removal process is performed to remove the first dummy gate structure and the second dummy gate structure. Figure 10 502, 504) and spacer layer ( Figure 10 (406). In some embodiments, the gate dielectric layer 116 is formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). Furthermore, in some embodiments, the gate dielectric layer 116 comprises, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxides, SiCOH), or some other suitable dielectric material.

[0048] In some embodiments, Figure 11 The removal process includes one or more etching processes. For example, in some embodiments, a first etchant may be used to remove the virtual masking structure ( Figure 10 508), and the second etchant can be used to remove the dummy gate electrode ( Figure 10 510), Virtual Interface Layer ( Figure 10 506) and spacer layer ( Figure 10(406). In some embodiments, Figure 11 The removal process does not remove the first gate sidewall structure 132.

[0049] like Figure 12 As illustrated in cross-sectional view 1200, in some embodiments, a gate electrode 124 is formed above and between nanosheet channel structures 122, thereby forming a first nanosheet field-effect transistor (NSFET) 118 and a second NSFET 120 disposed above a first substrate 302. In such embodiments, a second source / drain region 126b is disposed between the first NSFET 118 and the second NSFET 120 and is shared by both the first NSFET 118 and the second NSFET 120.

[0050] It should be understood that modifications may be made in other embodiments. Figures 3 to 12 The steps of the method shown are used to form some other transistor types that are different from NSFETs (e.g., fin field-effect transistors).

[0051] In some embodiments, the gate electrodes 124 of the first NSFET 118 and the second NSFET 120 are formed by depositing gate electrode material over and between the nanosheet channel structures 122. In some embodiments, the gate electrode material may be formed by means of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). Furthermore, in some embodiments, a removal process (e.g., chemical mechanical planarization (CMP)) is performed to remove any excess gate electrode material disposed over the gate dielectric layer 116, thereby forming the gate electrode 124 of the first NSFET 118 and the gate electrode 124 of the second NSFET 120. In some embodiments, the gate electrodes 124 of the first NSFET 118 and the second NSFET 120 comprise a conductive material, such as titanium, tantalum, aluminum, or some other suitable conductive material.

[0052] like Figure 13As illustrated in cross-sectional view 1300, a first interconnect structure 107 is formed on the gate electrodes 124 of the first NSFET 118 and the second NSFET 120 and above the gate dielectric layer 116. In some embodiments, the first interconnect structure 107 includes interconnect vias 108 and interconnect conductors 110 embedded in the interconnect dielectric layer 112 and the interconnect etch stop layer 114. In some embodiments, the first interconnect structure 107 may be formed by means of deposition processes (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.), patterning processes (e.g., photolithography / etching), and removal processes (e.g., wet etching, dry etching, chemical mechanical planarization (CMP), etc.).

[0053] For example, in some embodiments, the bottom layer of the interconnect etch stop layer 114 is deposited over the gate dielectric layer 116, and the bottom layer of the interconnect dielectric layer 112 is deposited over the bottom layer of the interconnect etch stop layer 114. Next, in some embodiments, photolithography is performed to form cavities in the bottom layers of the interconnect dielectric layer 112 and the interconnect etch stop layer 114, thereby exposing the gate electrodes 124 of the first NSFET 118 and the second NSFET 120. Next, in some embodiments, conductive material may be deposited within the cavities, and a removal process is performed to remove excess conductive material disposed over the bottom layer of the interconnect dielectric layer 112, thereby forming interconnect vias 108 in the bottom layers of the interconnect dielectric layer 112 and the interconnect etch stop layer 114. In such embodiments, the interconnect vias 108 and / or the interconnect wires 110 may be formed by means of a damascene process or a dual damascene process. In some other embodiments, it should be understood that there may be a ratio Figure 13 The cross-sectional view of Figure 1300 shows the interconnect wires 110 and interconnect vias 108, with more or fewer interconnect wires 110 and interconnect vias 108.

[0054] In some embodiments, the interconnect dielectric layer 112 comprises, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxides, SiCOH), or some other suitable dielectric material. In some embodiments, the interconnect etch stop layer 114 further comprises a dielectric material, but includes a dielectric material different from that of the interconnect dielectric layer 112. In some embodiments, the interconnect conductors 110 and the interconnect vias 108 comprise conductive materials, such as tungsten, aluminum, copper, titanium, tantalum, or some other suitable conductive materials.

[0055] like Figure 14As illustrated in cross-sectional view 1400, in some embodiments, a second bonding layer 106 is formed on the first interconnect structure 107. In some embodiments, the second bonding layer 106 comprises, for example, an oxide, such as silicon dioxide. It should be understood that other materials used for the second bonding layer 106 are also within the scope of this disclosure. In some embodiments, the second bonding layer 106 is formed by means of a high-density plasma deposition process. In other embodiments, the second bonding layer 106 may be formed by means of another deposition process (e.g., CVD, PVD, PE-CVD, ALD, etc.). In some embodiments, to ensure a smooth upper surface, for example, the second bonding layer 106 may undergo a CMP process after its deposition on the first interconnect structure 107.

[0056] like Figure 15 As illustrated in cross-sectional Figure 1500, in some embodiments, a first bonding layer 104 disposed on a carrier substrate 102 is bonded to a second bonding layer 106. In such embodiments, the bonding process for bonding the first bonding layer 104 to the second bonding layer 106 may include, for example, a thermal bonding process. It should be understood that other bonding processes are also within the scope of this disclosure. In some embodiments, the first bonding layer 104 may also comprise an oxide, such as silicon dioxide.

[0057] like Figure 16 As shown in the cross-sectional view 1600, in some embodiments, the flipping Figure 15 The structure in the cross-sectional view 1500 is such that the back side 302b of the first substrate 302 is "upward" for patterning. It should be understood that in Figures 3 to 15 In this embodiment, the first NSFET 118 and the second NSFET 120 are formed on the front side 302f of the first substrate 302, and the front side 302f of the first substrate 302 is on the opposite side of the back side 302b of the first substrate 302. In an embodiment where the first substrate 302 is an SOI substrate, the first substrate 302 is flipped so that the substrate layer 304 is exposed for patterning. In such embodiments, the carrier substrate 102 may be... Figure 16 The structure protects the first interconnect structure 107 from damage during the flipping process.

[0058] like Figure 17 As illustrated in cross-sectional Figure 1700, in some embodiments, a removal process is performed to remove a portion of the first substrate ( Figure 17 302). In some embodiments, the removal process may include a CMP process to remove the first substrate ( Figure 17 (302) becomes thinner. Can be performed Figure 17 The removal process is used to remove the first substrate ( Figure 16 The basal layer of 302) Figure 16 304) and the first substrate ( Figure 16The insulating layer of 302) Figure 16 (306). In some embodiments, stopping is performed before the active layer 308 is completely removed. Figure 17 The removal process. Therefore, in Figure 17 After the removal process, in some embodiments, the active layer 308 may still completely cover the first source / drain region 126a, the second source / drain region 126b, and the third source / drain region 126c. In other embodiments, Figure 17 The removal process may include etching.

[0059] like Figure 18 As illustrated in cross-sectional view 1800, in some embodiments, a removal process is performed to completely remove the active layer from the first source / drain region 126a, the second source / drain region 126b, and the third source / drain region 126c. Figure 17 308) and / or the first substrate ( Figure 16 The remaining portion of 302). In some embodiments, Figure 18 The removal process includes etching processes (e.g., wet etching, dry etching). In some embodiments, Figure 17 and Figure 18 The removal process includes a single etchant, while in other embodiments, Figure 17 The removal process includes CMP process, followed by Figure 18 The etching process in [the context]. In some embodiments, Figure 18 The removal process also removes the upper portions of the first source / drain region 126a, the second source / drain region 126b, and the third source / drain region 126c. In some embodiments, the same etchant can be used to remove the first substrate ( Figure 16 The first substrate (302) and portions of the first source / drain region 126a, the second source / drain region 126b, and the third source / drain region 126c, while in other embodiments, different etchants can be used to remove portions of the first substrate ( Figure 16 The portion of 302) and the first source / drain region 126a, the second source / drain region 126b and the third source / drain region 126c.

[0060] However, in such embodiments, in Figure 18 After the removal process, one or more of the nanosheet channel structures 122 can be exposed. In such embodiments, after removing the first substrate ( Figure 16 During phase 302), the protective layer 134 of the first NSFET 118 and the second NSFET 120 provides protection for the nanosheet channel structure 122. Therefore, in some embodiments, Figure 18 The removal process includes one or more etchants to remove the first substrate ( Figure 16The protective layer 134 includes portions of the first source / drain region 126a, the second source / drain region 126b, and the third source / drain region 126c, and includes a protective layer 134 that resists... Figure 18 The material is removed by one or more etchants in the removal process. Furthermore, Figure 18 One or more etchants in the removal process can be applied in a generally vertical direction to prevent removal or damage to the nanosheet channel structure 122 in the lateral direction.

[0061] like Figure 19 As illustrated in cross-sectional view 1900, in some embodiments, a barrier layer 1936 may be continuously formed over the first NSFET 118 and the second NSFET 120, thereby covering the outer sidewalls of the nanosheet channel structure 122 disposed over the first source / drain region 126a, the second source / drain region 126b, and the third source / drain region 126c. In some embodiments, the barrier layer 1936 is formed by means of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.) and includes a carbide (e.g., silicon carbide), a nitride (e.g., silicon nitride, silicon nitride carbon), or some other suitable dielectric material.

[0062] Furthermore, in some embodiments, a contact dielectric layer 140 is formed over the barrier layer 1936. In some embodiments, the contact dielectric layer 140 is formed by deposition processes (e.g., PVD, CVD, PE-CVD, ALD, etc.) and / or removal processes (e.g., etching, CMP, etc.). In some embodiments, the contact dielectric layer 140 comprises, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxides, SiCOH), or some other suitable dielectric material. In some embodiments, the contact dielectric layer 140 extends over the first NSFET 118 and the second NSFET 120.

[0063] like Figure 20 As illustrated in cross-sectional view 2000, in some embodiments, a contact masking structure 2002 is formed over a contact dielectric layer 140, and a removal process is performed based on the contact masking structure 2002 to form a contact cavity in the contact dielectric layer 140. In some embodiments, the contact masking structure 2002 is formed by means of photolithography and removal (e.g., etching) processes to form an opening disposed over the second source / drain region 126b. In such embodiments, the contact masking structure 2002 may include a photoresist or a hard mask material. In some embodiments, after the contact masking structure 2002 is formed, a removal process is performed... Figure 20The removal process removes a portion of the contact dielectric layer 140 located directly beneath the opening in the contact masking structure 2002, thereby forming a contact cavity 2004. In some embodiments, Figure 20 The removal process includes etching processes (e.g., wet etching, dry etching). In some embodiments, the contact cavity 2004 exposes the entire upper surface of the second source / drain region 126b. Furthermore, in some embodiments, a partial protective layer 134 is exposed after the contact cavity 2004 is formed. In such embodiments, the protective layer 134 may include substantially resistant... Figure 20 The material to be removed by the removal process.

[0064] Furthermore, in some embodiments, it can be achieved through Figure 20 The removal process removes the barrier layer directly beneath the opening in the contact shielding structure 2002. Figure 19 The horizontal portion of (1936). Residual barrier layer ( Figure 19 (1936) A barrier structure 136 can be formed on the outer sidewall of the protective layer 134 and on the outer sidewall of the nanosheet channel structure 122 above the first source / drain region 126a, the second source / drain region 126b, and the third source / drain region 126c. The barrier structure 136 can protect the nanosheet channel structure 122 from... Figure 20 The removal process removes and / or damages the material.

[0065] like Figure 21 As shown in the cross-sectional view 2100, a silicide layer 216 can be formed above the second source / drain region 126b, and a contact plug structure 138 can be formed above the silicide layer 216 and in the contact cavity. Figure 20 Within 2004). In some embodiments, the silicide layer 216 can be formed by depositing a transition metal layer covering the second source / drain region 126b, and subsequently heating the transition metal layer to react with the semiconductor material of the second source / drain region 126b. Therefore, in some embodiments, the silicide layer 216 may include nickel silicide, titanium silicide, cobalt silicide, platinum silicide, tungsten silicide, or some other metal-semiconductor material.

[0066] In some embodiments, after forming the silicide layer 216, a contact conductive material is formed over the silicide layer 216 by means of a deposition process (e.g., CVD, PVD, PE-CVD, ALD, sputtering, etc.). In some embodiments, excess contact conductive material disposed over the contact dielectric layer 140 is then removed by means of a removal process (e.g., etching, CMP) to form a contact plug structure 138 embedded in the contact dielectric layer 140. In some embodiments, the contact plug structure 138 may include, for example, tungsten, ruthenium, cobalt, or some other conductive material with low resistivity. Furthermore, in some embodiments, the contact plug structure 138 includes a lower portion 138L disposed directly between the protective layers 134, the lower portion 138L having a width equal to a first distance d1 and a second height h2. In some embodiments, the first distance d1 may be in the range of, for example, about 2.5 nanometers to about 100 nanometers, and the second height h2 may be in the range of, for example, about 5 nanometers to about 150 nanometers. Furthermore, in some embodiments, the contact plug structure 138 includes an upper portion 138U disposed above the protective layer 134, the upper portion 138U having a width equal to a second distance d2 and a third height h3. In some embodiments, the second distance d2 and the third height h3 may each be in the range of, for example, about 5 nanometers to about 150 nanometers.

[0067] like Figure 22 As illustrated in cross-sectional view 2200, in some embodiments, the memory structure 142 is formed directly over the contact plug structure 138. In some embodiments, the memory structure 142 is a magnetoresistive random access memory (MRAM) cell that includes a magnetic tunnel junction (MTJ) stack 202 disposed between a top electrode 148 and a bottom electrode 144. The bottom electrode 144 is disposed directly over and coupled to the contact plug structure 138. In some embodiments, the MTJ stack 202 may include a thin insulating layer 208 disposed between a bottom magnetic layer 204 and a top magnetic layer 206. Furthermore, in some embodiments, the MTJ stack 202 has an outermost sidewall surrounded by a first MRAM sidewall structure 210 and a second MRAM sidewall structure 212. The memory structure 142 may be disposed within a memory dielectric structure 143 above the contact dielectric layer 140.

[0068] In some embodiments, the memory structure 142 is formed by various steps including deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.), removal processes (e.g., wet etching, dry etching, chemical mechanical planarization (CMP), etc.), and / or patterning processes (e.g., photolithography / etching). In other embodiments, the memory structure 142 may alternatively be or include metal-insulator-metal memory cells, ferroelectric random access memory cells, phase-change random access memory cells, resistive random access memory cells, or some other memory device. In some embodiments, an interconnect etch stop layer 114 is formed over the memory structure 142 to protect the memory structure 142 and / or the memory dielectric structure 143 in future processing steps.

[0069] like Figure 23 As illustrated in cross-sectional view 2300, in some embodiments, a second interconnect structure 150 is arranged above and coupled to the memory structure 142. In some embodiments, the second interconnect structure 150 is similar to... Figure 13 The first interconnect structure 107 described herein is formed. The second interconnect structure 150 may include interconnect vias 108 and interconnect conductors 110 embedded in the interconnect dielectric layer 112 and / or the interconnect etch stop layer 114. In some embodiments, from the perspective of cross-sectional view 2300, the second interconnect structure 150 is disposed above the first NSFET 118 and the second NSFET 120, and the first interconnect structure 107 is disposed below the first NSFET 118 and the second NSFET 120, wherein the interconnect via 108 of the second interconnect structure 150 has an upper surface wider than its lower surface, and the interconnect via 108 of the first interconnect structure 107 has an upper surface narrower than its lower surface.

[0070] exist Figure 23 In the cross-sectional view 2300, the memory structure 142 is arranged above the first NSFET 118 and the second NSFET 120 and coupled to the first NSFET 118 and the second NSFET 120 via a contact plug structure 138, and the first interconnect structure 107 is arranged below the first NSFET 118 and the second NSFET 120 and coupled to the first NSFET 118 and the second NSFET 120. By utilizing the upper and lower sides of the first NSFET 118 and the second NSFET 120, the overall height of the integrated chip can be reduced to increase device density, while the signal travel efficiency between the first NSFET 118 and the second NSFET 120 and the memory structure 142 is improved to increase device reliability.

[0071] Figure 24 Showing the corresponding Figures 3 to 23 The flowcharts show some embodiments of method 2400.

[0072] Although method 2400 is shown and described below as a series of actions or events, it should be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events, in addition to those shown and / or described herein. Furthermore, not all shown actions may be required to implement one or more aspects or embodiments described herein. Moreover, one or more of the actions depicted herein may be performed as one or more separate actions and / or phases.

[0073] At action 2402, a spacer layer disposed between semiconductor layers is formed on the front side of the substrate. Figure 4 Cross-sectional view 400 is shown for some embodiments corresponding to action 2402.

[0074] At action 2404, a first virtual gate structure and a second virtual gate structure are formed above the spacer layer and the semiconductor layer. Figure 5 Cross-sectional view 500 is shown for some embodiments corresponding to action 2404.

[0075] At action 2406, a portion of the spacer layer and a portion of the semiconductor layer that are not located directly below the first virtual gate structure and the second virtual gate structure are removed, wherein the bottommost spacer layer is not removed and is still completely covered by the bottommost semiconductor layer. Figure 6 A cross-sectional view 600 is shown, corresponding to some embodiments of action 2406.

[0076] At action 2408, the outer portion of the exposed spacer layer is removed, and the inner spacer structure is formed on the exposed spacer layer. Figure 7 A cross-sectional view 700 is shown, corresponding to some embodiments of action 2408.

[0077] At action 2410, a portion of the bottommost semiconductor layer and a portion of the bottommost spacer layer that are not located directly below the first virtual gate structure and the second virtual gate structure are removed. Figure 8 A cross-sectional view 800 is shown, corresponding to some embodiments of action 2410.

[0078] At action 2412, the bottommost semiconductor layer is selectively removed, and a first protective layer and a second protective layer are formed, respectively disposed directly below the first virtual gate structure and the second virtual gate structure. Figure 9 A cross-sectional view 900 is shown, corresponding to some embodiments of action 2412.

[0079] At action 2414, a source / drain region is formed above the front side of the substrate and next to the semiconductor layer; and the first virtual gate structure, the second virtual gate structure, and the spacer layer are replaced by gate electrodes to form a first nanosheet field-effect transistor (NSFET) and a second NSFET. Figure 10 , Figure 11 as well as Figure 12 Cross-sectional views 1000, 1100, and 1200 are shown respectively, corresponding to some embodiments of action 2414.

[0080] At action 2416, a first interconnect (IC) structure is formed that is coupled to the first NSFET and the second NSFET. Figure 13 Cross-sectional view 1300 is shown for some embodiments corresponding to action 2416.

[0081] At action 2418, the substrate is flipped to expose the back side of the substrate. Figure 16 Cross-sectional view 1600 shows some embodiments corresponding to action 2418.

[0082] At action 2420, the substrate is removed. Figure 17 and Figure 18 Cross-sectional views 1700 and 1800 are shown respectively, corresponding to some embodiments of action 2420.

[0083] At action 2422, a contact plug structure is formed between the first NSFET and the second NSFET and the contact plug structure is coupled to the source / drain region disposed between the first NSFET and the second NSFET. Figure 21 Cross-sectional view 2100 shows some embodiments corresponding to action 2422.

[0084] At action 2424, a memory structure is formed above and coupled to the contact plug structure, and a second IC structure is formed above and coupled to the memory structure. Figure 22 and Figure 23 Cross-sectional views 2200 and 2300 are shown respectively, corresponding to some embodiments of action 2424.

[0085] Therefore, this disclosure relates to a method for manufacturing a memory structure disposed above a first transistor and a second transistor, and a first interconnect structure disposed below the first transistor and the second transistor, to reduce the height of the integrated chip, thereby increasing device density and improving signal travel efficiency.

[0086] Therefore, in some embodiments, this disclosure relates to an integrated chip, comprising: a first transistor disposed above a substrate and including: a plurality of first channel structures extending between a first source / drain region and a second source / drain region, a first gate electrode disposed between the first channel structures, and a first protective layer disposed above the topmost first channel structure in the first channel structures; a second transistor disposed above the substrate and next to the first transistor, and including: a plurality of second channel structures extending between a second source / drain region and a third source / drain region, a second gate electrode disposed between the second channel structures, and a second protective layer disposed above the topmost second channel structure in the second channel structures; a first interconnect structure coupled to the first gate electrode and the second gate electrode and disposed between the substrate and the first channel structure and the second channel structure; and a contact plug structure coupled to the second source / drain region and disposed above the first gate electrode and the second gate electrode.

[0087] In some embodiments, the integrated chip further includes: a memory structure disposed directly above and coupled to the contact plug structure. In some embodiments, the integrated chip further includes: a second interconnect structure coupled to the memory structure. In some embodiments, the integrated chip further includes: a bonding layer disposed directly between the substrate and the first interconnect structure. In some embodiments, the first channel structure and the second channel structure are nanosheet channel structures. In some embodiments, the integrated chip further includes: an internal spacer structure disposed on portions of the first gate electrode and the second gate electrode and separating the portions of the first gate electrode and the second gate electrode from the first source / drain region, the second source / drain region, and the third source / drain region. In some embodiments, the internal spacer structure comprises the same material as the first protective layer and the second protective layer. In some embodiments, the contact plug structure includes a lower portion disposed directly between the first protective layer and the second protective layer, and an upper portion disposed directly above the first protective layer and the second protective layer. In some embodiments, the barrier structure is disposed directly between the lower portion of the contact plug structure and the first protective layer, and also directly between the lower portion of the contact plug structure and the second protective layer.

[0088] In other embodiments, this disclosure relates to an integrated chip, comprising: a first interconnect structure located above a substrate; a first channel structure disposed above and coupled to the first interconnect structure; a second channel structure disposed above and coupled to the first interconnect structure; a source / drain region disposed between the first channel structure and the second channel structure; a first protective layer and a second protective layer disposed above the first channel structure and the second channel structure, respectively; a contact plug structure disposed above and coupled to the source / drain region; and a memory structure disposed above and coupled to the contact plug structure.

[0089] In some embodiments, the integrated chip further includes: a second interconnect structure disposed above and coupled to the memory structure. In some embodiments, the integrated chip further includes: an elongated via structure extending from the second interconnect structure to the first interconnect structure. In some embodiments, the integrated chip further includes: a first gate electrode disposed directly between the first channel structure and the first interconnect structure; and a second gate electrode disposed directly between the second channel structure and the first interconnect structure. In some embodiments, the integrated chip further includes: a silicide layer disposed between the source / drain region and the contact plug structure. In some embodiments, the integrated chip further includes: a barrier structure disposed on the inner sidewalls of the first protective layer and the second protective layer. In some embodiments, the first channel structure includes a plurality of first nanosheet channel structures, and wherein the second channel structure includes a plurality of second nanosheet channel structures.

[0090] In other embodiments, this disclosure relates to a method comprising: forming a first protective layer over a first substrate and forming a second protective layer over the first substrate; forming a first nanosheet field-effect transistor (NSFET) disposed over the first protective layer, wherein the first nanosheet field-effect transistor includes a first nanosheet channel structure, a first source / drain region, a second source / drain region, and a first gate electrode; forming a second NSFET over the second protective layer, wherein the second NSFET includes a second nanosheet channel structure, a second source / drain region, a third source / drain region, and a second gate electrode; forming a first interconnect structure over the first NSFET and the second NSFET, wherein the first interconnect structure includes interconnect wires and interconnect vias embedded in the interconnect dielectric structure; and forming a first interconnect structure over the second NSFET. A bonding layer is formed over an interconnect structure; a carrier substrate is bonded to the bonding layer; a first substrate is flipped to pattern the back side of the first substrate; the first substrate is completely removed to expose a first source / drain region, a second source / drain region, and a third source / drain region, as well as a first protective layer and a second protective layer; a dielectric layer is formed over the first source / drain region, the second source / drain region, and the third source / drain region, as well as the first protective layer and the second protective layer; a contact plug structure is formed to extend through the dielectric layer and couple to a second source / drain region disposed between a first NSFET and a second NSFET; a memory structure is formed over the contact plug structure and the memory structure is coupled to the contact plug structure; and a second interconnect structure is formed over the memory structure and the second interconnect structure is coupled to the memory structure.

[0091] In some embodiments, forming the first protective layer, the second protective layer, the first nanosheet field-effect transistor, and the second nanosheet field-effect transistor includes: forming a plurality of spacer layers disposed between a plurality of semiconductor layers over the first substrate; forming a first dummy gate structure and a second dummy gate structure over the spacer layers; removing portions of the spacer layers and portions of the semiconductor layers not directly beneath the first dummy gate structure and the second dummy gate structure, wherein the bottommost spacer layer is not removed and is still completely covered by the bottommost semiconductor layer; removing the outer portion of the exposed spacer layer and forming an inner spacer structure on the exposed spacer layer; removing portions of the bottommost semiconductor layer and portions of the bottommost spacer layer not directly beneath the first dummy gate structure and the second dummy gate structure; and selectively removing the bottommost spacer layer. A first protective layer is formed directly between the first substrate and the bottommost semiconductor layer, and directly below the first dummy gate structure; a second protective layer is formed directly between the first substrate and the bottommost semiconductor layer, and directly below the second dummy gate structure; a first source / drain region, a second source / drain region, and a third source / drain region are formed above the first substrate; the remaining portions of the first dummy gate structure, the second dummy gate structure, and the spacer layer are removed; a first gate electrode is formed above and between the semiconductor layers disposed above the first protective layer to form the first nanosheet field-effect transistor; and a second gate electrode is formed above and between the semiconductor layers disposed above the second protective layer to form the second nanosheet field-effect transistor. In some embodiments, the first substrate is a silicon-on-insulator substrate. In some embodiments, removing the first substrate includes a first etchant, and wherein the first and second protective layers resist removal by the first etchant.

[0092] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated chip, comprising: A first transistor, disposed above a substrate, includes: Multiple first-channel structures extend between the first source / drain region and the second source / drain region. The first gate electrode is disposed between the first channel structures, and The first protective layer is arranged above the topmost first channel structure in the first channel structure and directly contacts the topmost first channel structure in the first channel structure. A second transistor, disposed above the substrate and next to the first transistor, includes: Multiple second-channel structures extend between the second source / drain region and the third source / drain region. The second gate electrode is disposed between the second channel structures, and The second protective layer is arranged above the topmost second channel structure in the second channel structure and directly contacts the topmost second channel structure in the second channel structure. A first interconnect structure is coupled to the first gate electrode and the second gate electrode and disposed between the substrate and the first channel structure and the second channel structure; and A contact plug structure is coupled to the second source / drain region and disposed above the first gate electrode and the second gate electrode.

2. The integrated chip according to claim 1, further comprising: The memory structure is disposed directly above and coupled to the contact plug structure.

3. The integrated chip according to claim 2, further comprising: The second interconnect structure is coupled to the memory structure.

4. The integrated chip according to claim 1, further comprising: The bonding layer is disposed directly between the substrate and the first interconnect structure.

5. The integrated chip according to claim 1, wherein the first channel structure and the second channel structure are nanosheet channel structures.

6. The integrated chip according to claim 1, further comprising: An internal spacer structure is arranged on portions of the first gate electrode and the second gate electrode and separates said portions of the first gate electrode and the second gate electrode from the first source / drain region, the second source / drain region and the third source / drain region.

7. The integrated chip of claim 6, wherein the internal spacer structure comprises the same material as the first protective layer and the second protective layer.

8. The integrated chip of claim 1, wherein the contact plug structure includes a lower portion disposed directly between the first protective layer and the second protective layer, and includes an upper portion disposed directly above the first protective layer and the second protective layer.

9. The integrated chip of claim 8, wherein the barrier structure is disposed directly between the lower portion of the contact plug structure and the first protective layer, and also directly between the lower portion of the contact plug structure and the second protective layer.

10. An integrated chip, comprising: The first interconnect structure is located above the substrate; The first channel structure is arranged above the first interconnect structure and coupled to the first interconnect structure; The second channel structure is arranged above the first interconnect structure and coupled to the first interconnect structure; The source / drain regions are arranged between the first channel structure and the second channel structure; A first protective layer and a second protective layer are respectively arranged above the first channel structure and the second channel structure, wherein the first protective layer directly contacts the topmost first channel structure in the first channel structure and the second protective layer directly contacts the topmost second channel structure in the second channel structure. A contact plug structure is disposed above the source / drain region and coupled to the source / drain region; as well as A memory structure is disposed above and coupled to the contact plug structure.

11. The integrated chip according to claim 10, further comprising: A second interconnect structure is disposed above the memory structure and coupled to the memory structure.

12. The integrated chip according to claim 11, further comprising: A slender through-hole structure extends from the second interconnect structure to the first interconnect structure.

13. The integrated chip according to claim 10, further comprising: The first gate electrode is directly disposed between the first channel structure and the first interconnect structure. as well as The second gate electrode is directly disposed between the second channel structure and the first interconnect structure.

14. The integrated chip according to claim 10, further comprising: A silicide layer is disposed between the source / drain region and the contact plug structure.

15. The integrated chip according to claim 10, further comprising: A barrier structure is arranged on the inner sidewalls of the first protective layer and the second protective layer.

16. The integrated chip according to claim 10, wherein the first channel structure comprises a plurality of first nanosheet channel structures, and wherein the second channel structure comprises a plurality of second nanosheet channel structures.

17. A method for forming an integrated chip, comprising: A first protective layer is formed over a first substrate, and a second protective layer is formed over the first substrate; A first nanosheet field-effect transistor (NSFET) is formed on top of the first protective layer, and the first nanosheet field-effect transistor includes a first nanosheet channel structure, a first source / drain region, a second source / drain region, and a first gate electrode, wherein the first protective layer directly contacts the topmost first nanosheet channel structure in the first nanosheet channel structure. A second nanosheet field-effect transistor is formed above the second protective layer, and the second nanosheet field-effect transistor includes a second nanosheet channel structure, a second source / drain region, a third source / drain region, and a second gate electrode, wherein the second protective layer directly contacts the topmost second nanosheet channel structure in the second nanosheet channel structure. A first interconnect structure is formed above the first nanosheet field-effect transistor and the second nanosheet field-effect transistor, wherein the first interconnect structure includes an interconnect wire and an interconnect via embedded in the interconnect dielectric structure. A bonding layer is formed above the first interconnect structure; The carrier substrate is bonded to the bonding layer; Flip the first substrate to pattern the back side of the first substrate; Completely remove the first substrate to expose the first source / drain region, the second source / drain region, the third source / drain region, the first protective layer, and the second protective layer; A dielectric layer is formed over the first source / drain region, the second source / drain region, the third source / drain region, the first protective layer, and the second protective layer; A contact plug structure is formed to extend through the dielectric layer and couple to the second source / drain region disposed between the first nanosheet field-effect transistor and the second nanosheet field-effect transistor; A memory structure is formed above the contact plug structure, and the memory structure is coupled to the contact plug structure; as well as A second interconnect structure is formed above the memory structure, and the second interconnect structure is coupled to the memory structure.

18. The method of forming an integrated chip according to claim 17, wherein forming the first protective layer, the second protective layer, the first nanosheet field-effect transistor, and the second nanosheet field-effect transistor comprises: A plurality of spacer layers are formed above the first substrate, arranged between a plurality of semiconductor layers; A first virtual gate structure and a second virtual gate structure are formed above the spacer layer; Remove a portion of the spacer layer and a portion of the semiconductor layer that are not located directly below the first virtual gate structure and the second virtual gate structure, wherein the bottommost spacer layer is not removed and is still completely covered by the bottommost semiconductor layer; Remove the outer portion of the exposed spacer layer and form an internal spacer structure on the exposed spacer layer; Remove a portion of the bottommost semiconductor layer and a portion of the bottommost spacer layer that are not located directly below the first virtual gate structure and the second virtual gate structure; Selectively remove the bottommost spacer layer; A first protective layer is formed directly between the first substrate and the bottommost semiconductor layer, and directly below the first virtual gate structure; A second protective layer is formed directly between the first substrate and the bottommost semiconductor layer, and directly below the second virtual gate structure; A first source / drain region, a second source / drain region, and a third source / drain region are formed above the first substrate; Remove the first virtual gate structure, the second virtual gate structure, and the remaining portion of the spacer layer; A first gate electrode is formed above and between the semiconductor layer disposed above the first protective layer to form the first nanosheet field-effect transistor; as well as A second gate electrode is formed above and between the semiconductor layer disposed above the second protective layer to form the second nanosheet field-effect transistor.

19. The method for forming an integrated chip according to claim 17, wherein the first substrate is a silicon-on-insulator substrate.

20. The method of forming an integrated chip according to claim 17, wherein removing the first substrate includes a first etchant, and wherein the first protective layer and the second protective layer resist removal by the first etchant.

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