Junction Barrier Schottky Diode Devices and Their Fabrication Methods

Abstract

This application discloses a junction barrier Schottky diode and its fabrication method. The junction barrier Schottky diode includes: an epitaxial wafer having an epitaxial layer; the epitaxial layer having opposing first and second surfaces; the first surface having a functional region and trench regions located on both sides of the functional region; a deep trench located within the surface of the trench region; a first ion implantation region located within the surface of the sidewalls and bottom of the deep trench; and a Schottky region extension structure located within the surface of the functional region between two adjacent deep trenches, used to increase the area of ​​the Schottky region between the two adjacent deep trenches. In this application, the deep trench can increase the implantation depth of the first ion implantation region, and the Schottky region extension structure disposed between two deep trenches can increase the area of ​​the Schottky region between two adjacent deep trenches.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a junction barrier Schottky diode (JBS) and its fabrication method. Background Technology

[0002] SiC, a wide-bandgap semiconductor material that has developed rapidly in the last decade or so, possesses advantages over other semiconductor materials (such as Si, GaN, and GaAs), including a wide bandgap, high thermal conductivity, high carrier saturation mobility, and high power density. SiC can be thermally oxidized to form silicon dioxide, making it possible to realize power devices and circuits such as SiC MOSFETs and Schottky barrier diodes (SBDs). Since the 1990s, SiC MOSFETs and SBDs have been widely used in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.

[0003] like Figure 1 As shown, Figure 1 This is a schematic diagram of a conventional SiC Schottky diode device, including: a substrate 1; an epitaxial layer 2 disposed on the substrate 1; a functional region and ion implantation regions 3 on both sides of the functional region on the surface of the epitaxial layer 2 facing away from the substrate 1; an anode on the surface of the epitaxial layer 2 facing away from the substrate 1; and a cathode on the thin film of the substrate 1 facing away from the epitaxial layer 2. Generally, the epitaxial layer 2 is an N-type SiC epitaxial layer formed on an N+-type (heavily N-type doped) substrate 1, and the ion implantation regions 3 are P+ doped (heavily P-type doped).

[0004] In conventional SiC Schottky diode devices, the implantation depth of ion implantation region 3 and the area of ​​the Schottky region need to be further improved. Summary of the Invention

[0005] In view of this, this application provides a junction barrier Schottky diode and a method for fabricating the same, as follows:

[0006] A junction barrier Schottky diode device, comprising:

[0007] An epitaxial wafer has an epitaxial layer; the epitaxial layer has a first surface and a second surface opposite to each other; the first surface has a functional region and a trench region located on both sides of the functional region;

[0008] Deep trenches are located within the surface of the trench area;

[0009] The first ion implantation region is located within the surface of the sidewalls and bottom of the deep trench;

[0010] The Schottky region extension structure is located within the surface of the functional region between two adjacent deep trenches, and is used to increase the area of ​​the Schottky region between the two adjacent deep trenches.

[0011] Preferably, in the above-mentioned junction barrier Schottky diode device, the Schottky region extension structure includes: a second ion implantation region located within the surface of the functional region;

[0012] The implantation depth of the second ion implantation region is less than that of the first ion implantation region; the first ion implantation region and the second ion implantation region have the same doping type, but different from the doping type of the epitaxial wafer.

[0013] Preferably, in the above-mentioned junction barrier Schottky diode device, the deep trench is a multi-level trench, which includes a plurality of sub-trenches arranged sequentially in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; in the same deep trench, in two adjacent sub-trenches, the width of the sub-trench closer to the bottom of the deep trench is smaller than the width of the sub-trench farther from the bottom of the deep trench.

[0014] Preferably, in the above-mentioned junction barrier Schottky diode device, the functional region has a single-stage trench, and the depth of the single-stage trench is less than the depth of the deep trench;

[0015] The second ion implantation region is located within the surface of the sidewall and bottom of the single-stage trench.

[0016] Preferably, in the above-mentioned junction barrier Schottky diode device, the sub-trench adjacent to the first surface in the deep trench is the first-level sub-trench;

[0017] The single-level trench has the same depth as the first-level sub-trench.

[0018] Preferably, in the above-described junction barrier Schottky diode device, in the multi-level trenches, the width of the same sub-trench remains unchanged in the first direction;

[0019] The width of the single-stage trench remains unchanged.

[0020] Preferably, in the above-mentioned junction barrier Schottky diode device, the surface of the functional region has a first electric field buffer injection region, which surrounds the opening of the single-stage trench and is used to increase the thickness of the second ion implantation region near the opening position of the single-stage trench sidewall.

[0021] Preferably, in the above-mentioned junction barrier Schottky diode device, the second ion implantation region is a trenchless ion implantation region formed by direct ion implantation into the device region.

[0022] Preferably, in the above-described junction barrier Schottky diode device, the surface of the trench region has a second electric field buffer injection region, which surrounds the opening of the deep trench and is used to increase the thickness of the first ion implantation region near the opening position on the sidewall of the deep trench.

[0023] Preferably, in the above-described junction barrier Schottky diode device, the Schottky region extension structure is located between two adjacent deep trenches.

[0024] This application also provides a method for fabricating the above-mentioned junction barrier Schottky diode device, including:

[0025] An epitaxial wafer is provided, having an epitaxial layer; the epitaxial layer has opposing first and second surfaces; the first surface has functional regions and trench regions located on both sides of the functional regions;

[0026] A deep trench is formed within the surface of the trench region, and a Schottky region extension structure is formed within the surface of the functional region between two adjacent deep trenches; the Schottky region extension structure is used to increase the area of ​​the Schottky region between two adjacent deep trenches; the sidewalls and bottom of the trench have a first ion implantation region.

[0027] Preferably, in the above manufacturing method, the deep trench is a multi-level trench, which includes a plurality of sub-grooves arranged sequentially in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; in the same deep trench, in two adjacent sub-grooves, the width of the sub-grooves closer to the bottom of the deep trench is smaller than the width of the sub-grooves farther from the bottom of the deep trench.

[0028] The method for forming the first ion implantation region includes:

[0029] Ion implantation is performed based on the multi-level trenches, forming the first ion implantation region on the sidewalls and bottom of each sub-trench.

[0030] Preferably, in the above fabrication method, the Schottky region extension structure includes: a second ion implantation region located within the surface of the functional region; wherein the implantation depth of the second ion implantation region is less than the ion implantation depth of the first ion implantation region; the first ion implantation region and the second ion implantation region have the same doping type, but different from the doping type of the epitaxial wafer;

[0031] The method for forming the Schottky region extension structure includes:

[0032] While forming the sub-grooves adjacent to the first surface of the multi-level trenches, a single-level trench is formed within the surface of the functional area.

[0033] The second ion implantation region is formed simultaneously with the formation of the first ion implantation region.

[0034] Preferably, in the above manufacturing method, the method for forming the Schottky region extension structure includes:

[0035] Ion implantation is performed directly on the device region to form a trenchless ion implantation region as an extension structure of the Schottky region.

[0036] As described above, the junction barrier Schottky diode and its fabrication method provided in this application include: an epitaxial wafer having an epitaxial layer; the epitaxial layer having opposing first and second surfaces; the first surface having a functional region and trench regions located on both sides of the functional region; a deep trench located within the surface of the trench region; a first ion implantation region located within the surface of the sidewalls and bottom of the deep trench; and a Schottky region extension structure located within the surface of the functional region between two adjacent deep trenches, used to increase the area of ​​the Schottky region between two adjacent deep trenches. In this application, the deep trench can increase the implantation depth of the first ion implantation region, and the Schottky region extension structure disposed between two deep trenches can increase the area of ​​the Schottky region between two adjacent deep trenches. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0038] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0039] Figure 1 This is a schematic diagram of the structure of a conventional SiC Schottky diode device;

[0040] Figure 2 This is a schematic diagram of the structure of a JBS device provided in an embodiment of this application;

[0041] Figure 3 A surface electric field distribution diagram of the Schottky region in a JBS device provided in this application embodiment;

[0042] Figure 4 This is a schematic diagram of another JBS device provided in an embodiment of this application;

[0043] Figure 5 This is a schematic diagram of the structure of another JBS device provided in an embodiment of this application;

[0044] Figure 6 This is a schematic diagram of the structure of another JBS device provided in an embodiment of this application;

[0045] Figures 7-13 A process flow diagram of a JBS device fabrication method provided for an embodiment of this application;

[0046] Figure 14 This is a SEM image of the JBS device formed by the fabrication method described in the embodiments of this application. Detailed Implementation

[0047] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0048] Currently, SBD devices generally use, such as Figure 1 The JBS structure shown, especially the high-voltage SBD device, uses periodically distributed P+ type ion implantation regions 3 to mask and protect the Schottky region between two adjacent ion implantation regions 3. For Figure 1 The device structure shown presents a trade-off and contradiction in its design: a conflict exists between the device's current density per unit area and forward conduction impedance, and the surface electric field strength and reliability of the Schottky region. A wider Schottky region (m) results in a lower forward conduction impedance, but a larger m leads to a stronger surface electric field and lower reliability. Optimizing breakdown voltage and on-resistance is mutually influential and contradictory; achieving a high breakdown voltage generally makes it difficult to achieve a low on-resistance, especially for planar JBS devices. High breakdown voltage design is hampered by limitations in the implantation depth of the P+ type ion implantation region 13, which is limited by the process equipment, making it difficult to achieve a junction depth greater than 1µm. Using high-dose, MeV- or higher-energy ion implantation equipment, even at temperatures of 500-600 degrees Celsius, can still damage the SiC lattice structure, causing carrier trapping or continued expansion of lattice defects during subsequent device operation, thus leading to long-term device reliability issues.

[0049] Trench-type SBDs utilize deep trenches to create ion implantation regions of the desired depth, thereby increasing the ion implantation depth. Larger ion implantation depths can be achieved using smaller implantation doses and lower implantation energies, while simultaneously avoiding lattice damage to the SiC material. However, single-width trench SBD structures require trade-offs between trench depth and device forward conduction impedance, as well as between trench spacing and the breakdown voltage and surface electric field strength of the Schottky region between trenches. This presents a challenge for the design of high-voltage SBD devices.

[0050] In view of this, embodiments of this application propose a novel JBS device, which is a novel trench-type SBD device. The JBS device can further improve the performance of trench-type SBDs, further increasing the area of ​​the Schottky region between the two deep trenches, while maintaining a low Schottky surface electric field and low reverse leakage current, increasing the flexibility of device design. Moreover, the JBS device can avoid the contradiction between the forward conduction impedance and the breakdown voltage and surface electric field reliability of the Schottky region caused by a single-width deep trench structure in device design, further enhancing the breakdown voltage capability of the SBD device while maintaining a low forward conduction impedance. On the first surface, a Schottky region extension structure with a linewidth smaller than the opening area of ​​the deep trenches is introduced between the two deep trenches, which can enhance the flexibility of device design and process tolerance, while still maintaining a low planar Schottky region surface electric field and low leakage current, thereby enhancing the manufacturability and reliability of the device.

[0051] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] refer to Figure 2 As shown, Figure 2 This is a schematic diagram of a JBS device provided in an embodiment of this application. The JBS device includes:

[0053] The epitaxial wafer 10 has an epitaxial layer 101; the epitaxial layer 101 has a first surface B1 and a second surface B2 opposite to each other; the first surface B1 has a functional region A1 and a trench region A2 located on both sides of the functional region A1;

[0054] Deep trench 11 is located within the surface of the trench area A2;

[0055] The first ion implantation region 12 is located within the surface of the sidewall and bottom of the deep trench 11;

[0056] The Schottky region extension structure 13 is located within the surface of the functional region A1 between two adjacent deep trenches 11, and is used to increase the area of ​​the Schottky region between the two adjacent deep trenches 11.

[0057] The JBS device further includes a first electrode 14 located on the first surface B1 and a second electrode 15 located on the side of the epitaxial wafer opposite to the first electrode 14. The functional region A1 includes a first region for setting the Schottky region extension structure and a second region surrounding the first region. In the functional region A1, the contact area between the first electrode 14 and the second region is the Schottky region.

[0058] For a JBS device with deep trenches 11, when the design parameters of the deep trenches 11 and the first ion implantation region 12 formed based on the deep trenches 11 are fixed, the maximum area of ​​the Schottky region between two adjacent deep trenches 11 is fixed in order to ensure the reliability and stability of the device. Although increasing the number of deep trenches 11 can increase the area ratio of the Schottky region in the device, the opening area of ​​the deep trenches 11 on the first surface B1 is relatively large, so increasing the number of deep trenches has a limited effect on improving the area ratio of the Schottky region in the device. In the technical solution of this application, by setting a Schottky region extension structure 13 between two adjacent deep trenches 11, the width of the Schottky region extension structure 13 on the first surface B1 is smaller than the opening width of the deep trenches 11 on the first surface B1. Compared with a JBS device with a single linewidth deep trench 11, this can effectively increase the area of ​​the Schottky region in the device.

[0059] In this embodiment, the JBS device further improves the performance of the trench SBD, increasing the area of ​​the Schottky region between the two deep trenches 11 while maintaining a low Schottky surface electric field and low reverse leakage current, thus increasing the flexibility of device design. Furthermore, the JBS device avoids the contradiction between the forward conduction impedance and the breakdown voltage and surface electric field reliability of the Schottky region caused by a single-width deep trench structure in device design, further enhancing the breakdown voltage capability of the SBD device while maintaining a low forward conduction impedance. On the first surface B1, a Schottky region extension structure 13 with a linewidth smaller than the opening area of ​​the deep trenches 11 is introduced between the two deep trenches, enhancing the flexibility and process tolerance of device design while still maintaining a low planar Schottky surface electric field and low leakage current, thereby enhancing the manufacturability and reliability of the device.

[0060] Optionally, the epitaxial wafer 10 is a SiC epitaxial wafer, including a substrate 102 and an epitaxial layer 101 located on the surface of the substrate 102. The second surface B2 faces the substrate 102. Both the substrate 102 and the epitaxial layer 101 are made of SiC material. The second electrode 15 is located on the surface of the substrate 102 opposite to the epitaxial layer 101. Optionally, the epitaxial layer 11 can be an N-type (lightly doped N-type) SiC epitaxial layer; the substrate 102 can be an N+ type SiC substrate.

[0061] like Figure 2 As shown, the Schottky region extension structure 13 includes a second ion implantation region 131 located within the surface of the functional region; wherein the implantation depth of the second ion implantation region 131 is less than the ion implantation depth of the first ion implantation region 12; the first ion implantation region 12 and the second ion implantation region 131 have the same doping type, but different from the doping type of the epitaxial wafer. When the epitaxial layer 11 is N-type doped, both the first ion implantation region 12 and the second ion implantation region 131 can be P+ type doped.

[0062] In trench region A2, the first ion implantation region 12 can achieve P+ ion implantation to a greater depth based on the deep trench 11, weakening the surface electric field of the Schottky region, thereby achieving a Schottky region with a larger width between the two deep trenches 11. Furthermore, by setting a Schottky region extension structure 13 with a smaller linewidth between the two deep trenches 11, not only can the protection of the planar Schottky region and the shielding of the surface electric field be maintained, but the spacing between the two deep trenches 11 can also be further increased, thereby increasing the area of ​​the Schottky region between the two deep trenches 11.

[0063] The deep trench 11 contains a filling material, which can be any of an insulating medium, polycrystalline silicon, or metal. When filling with metal, a metal with good dense pore filling properties, such as titanium-tungsten, titanium, Mo, or aluminum, is used.

[0064] like Figure 2 As shown, the deep trench 11 is a multi-level trench, which includes a plurality of sub-trenches arranged sequentially in a first direction; the first direction is the direction in which the opening of the deep trench 11 points to the bottom; in the same deep trench 11, in two adjacent sub-trenches, the width of the sub-trench closer to the bottom of the deep trench is smaller than the width of the sub-trench farther from the bottom of the deep trench.

[0065] In this embodiment, the deep trench 11 is described as a two-stage trench. Figure 2 As shown, based on existing silicon carbide epitaxial wafers, a two-level trench can meet the required ion implantation depth. Clearly, the number of levels of the deep trench 11 can be selected based on device design requirements, and is not limited to the two-level trench structure in this embodiment; it can also be a three-level trench structure or other multi-level trench structures.

[0066] like Figure 2As shown, the functional area A1 has a single-level trench 16, the depth of which is less than the depth of the deep trench 11; wherein, the second ion implantation region is located within the surface of the sidewall and bottom of the single-level trench. In this embodiment, the second ion implantation region 131 is formed based on the single-level trench 16 with a smaller depth, which can effectively increase the area of ​​the Schottky region between the two deep trenches 11. The single-level trench 16 contains a filling material, which can be any of an insulating medium, polycrystalline silicon, or metal. When filling with metal, a metal with good dense pore filling properties, such as titanium-tungsten, titanium, molybdenum, or aluminum, is used.

[0067] refer to Figure 3 As shown, Figure 3 This application provides a surface electric field distribution diagram of the Schottky region in a JBS device. Figure 3 The upper figure shows the surface electric field distribution of the Schottky region in a conventional single-level trench JBS device, while the lower figure shows the surface electric field distribution of the Schottky region in the JBS device according to an embodiment of this application. Figure 3 A comparison of the surface electric field distribution of the Schottky region in the two figures shows that, when the deep trenches 11 are of the same multi-level trenches, the technical solution of this application can effectively increase the area of ​​the Schottky region between the two deep trenches 11, while maintaining the protection of the planar Schottky region and the shielding effect of the surface electric field. This is in contrast to... Figure 3 The area of ​​the Schottky region in the upper middle figure is S1. Using the technical solution of this application, the area of ​​the Schottky region can be increased to S2, which is twice the size of S1.

[0068] Optionally, in the deep trench 11, the sub-trench adjacent to the first surface B1 is a first-level sub-trench; the single-level trench 16 has the same depth as the first-level sub-trench. In this way, the single-level trench 16 is formed simultaneously with the first-level sub-trench of the deep trench 11, simplifying the manufacturing process, not adding process steps, and reducing manufacturing costs.

[0069] When the deep trench 11 is a multi-level trench, in the first direction, the width of the same sub-trench remains unchanged; the width of the single-level trench 16 also remains unchanged. The deep trench 11 employs a multi-level trench structure, where the widths of different sub-trenches decrease sequentially in the first direction, while the width of the same sub-trench remains constant. This allows for the formation of a deep trench 11 with a good morphology and enables the achievement of trench structures with greater depth.

[0070] When the second ion implantation region 131 is formed based on the single-level trench 16, the thickness of the second ion implantation region 131 gradually decreases along the direction from the bottom of the single-level trench 16 towards the opening due to the influence of the opening width and depth of the single-level trench 16. Especially near the opening of the single-level trench 16, where the thickness of the second ion implantation region 131 is the thinnest, leakage current and leakage or breakdown caused by electric field accumulation can occur at this location, affecting the manufacturability and reliability of the device. To solve these problems, such as Figure 2 As shown, in the Schottky diode device, the surface of the functional region A1 has a first electric field buffer injection region 17, which surrounds the opening of the single-stage trench 16 and is used to increase the thickness of the second ion implantation region 131 near the opening of the single-stage trench sidewall.

[0071] Similarly, near the opening of the deep trench 11, where the first ion implantation region 12 is the thinnest, leakage current and electric field accumulation leading to leakage or breakdown can occur, affecting the manufacturability and reliability of the device. To address these issues, such as... Figure 2 As shown, the surface of the trench region has a second electric field buffer injection region 18, which surrounds the opening of the deep trench and is used to increase the thickness of the first ion implantation region 12 near the opening of the deep trench sidewall.

[0072] To ensure the reliability and stability of the devices, such as Figure 2 As shown in the embodiment of this application, the Schottky region extension structure 13 is located in the middle of two adjacent deep trenches 11. That is, the deep trenches 11 on both sides of the Schottky region extension structure 13 are symmetrically arranged on both sides of the Schottky region extension structure 13.

[0073] refer to Figure 4 As shown, Figure 4 This is a schematic diagram of another JBS device provided in an embodiment of this application. Figure 4 The device structure shown is similar to Figure 2 The device structure shown employs different Schottky region extension structures 13. In this method, the second ion implantation region 131 is a trenchless ion implantation region formed by direct ion implantation into the device region A1. The JBS device shown in this method can also further increase the area of ​​the Schottky region between the two deep trenches 11 through the Schottky region extension structure 13, while maintaining a low Schottky surface electric field and a low reverse leakage current, increasing the flexibility of device design.

[0074] refer to Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of another JBS device provided in an embodiment of this application, based on Figure 2As shown, the first surface B1 further includes a termination region A3, with the functional region A1 and the trench region A2 located on the same side of the termination region A3. The surface of the termination region has a termination structure 19, which includes a junction termination extension (JTE) or a field limiting ring (FLR). An insulating dielectric layer 21, comprising silicon nitride and silicon dioxide, covers the surface of the termination region A3. The epitaxial wafer has a dicing region 20 for dicing and separating different devices.

[0075] refer to Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of another JBS device provided in an embodiment of this application, based on Figure 4 As shown, the first surface B1 further includes a terminal region A3, with the functional region A1 and the trench region A2 located on the same side of the terminal region A3. The surface of the terminal region has a terminal structure 19, and the surface of the terminal region A3 is covered with an insulating dielectric layer 21. The epitaxial wafer has a cutting area 20.

[0076] As can be seen from the above description, the technical solution described in this application embodiment combines the deep trench 11 and the first ion implantation region 12 connected to the deep trench 11 to construct a novel hybrid trench JBS device, which can further improve the performance of multi-level trench diode devices. By setting the Schottky region extension structure 13, the spacing between the two multi-level deep trenches can be further increased, while maintaining a low Schottky surface electric field and a low reverse leakage current, increasing the flexibility of device design. Furthermore, when the second ion implantation region 131 formed based on the single-level trench 16 serves as the Schottky region extension structure 13, it avoids the contradiction between the forward conduction impedance of the device and the breakdown voltage and surface electric field reliability of the Schottky region caused by the single-width trench structure during device design. This further enhances the breakdown voltage capability of the SBD device while maintaining a low forward conduction impedance. Introducing a Schottky region extension structure 13 with a linewidth smaller than the opening of the multi-level trench 11 between the two multi-level deep trenches 11 can enhance the flexibility and process tolerance of device design, save device area, and at the same time maintain a low surface electric field and low leakage current in the planar Schottky region, thereby enhancing the manufacturability and reliability of the device.

[0077] Based on the above embodiments, another embodiment of this application provides a manufacturing method for fabricating the JBS device described in the above embodiments, the manufacturing method being as follows: Figures 7-13 As shown.

[0078] refer to Figures 7-13 As shown, Figures 7-13 A process flow diagram of a JBS device fabrication method provided in this application embodiment, the fabrication method comprising:

[0079] Step S11: As Figure 7 As shown, an epitaxial wafer 10 is provided.

[0080] The epitaxial wafer 10 includes an epitaxial layer 101; the epitaxial layer 101 has a first surface B1 and a second surface B2 opposite to each other; the first surface B1 has a functional region A1 and trench regions A2 located on both sides of the functional region A1. The epitaxial wafer 10 also includes a substrate 102, on which the epitaxial layer 101 is formed. The first surface B1 is the surface of the epitaxial layer 101 facing away from the substrate 102.

[0081] Step S12: As Figures 8-10 As shown, deep trenches are formed within the surface of the trench region, and Schottky region extension structures are formed within the surface of the functional region between two adjacent deep trenches; the Schottky region extension structures are used to increase the area of ​​the Schottky region between two adjacent deep trenches; the sidewalls and bottom of the trenches have first ion implantation regions, ultimately forming as shown... Figure 2 The JBS device shown.

[0082] The trench structure can be fabricated using processes such as ICP, RIE, or laser ablation.

[0083] As described above, the deep trench 11 is a multi-level trench, which includes a plurality of sub-trenches arranged sequentially in a first direction; the first direction is the direction in which the opening of the deep trench 11 points to the bottom; in the same deep trench 11, among two adjacent sub-trenches, the width of the sub-trench closer to the bottom of the deep trench is smaller than the width of the sub-trench farther from the bottom of the deep trench. The fabrication method for forming the first ion implantation region 12 includes: performing ion implantation based on the multi-level trench to form the first ion implantation region 12 on the sidewalls and bottom of each level of sub-trench.

[0084] As described above, the Schottky region extension structure 13 includes a second ion implantation region 131 located within the surface of the functional region A1; wherein the implantation depth of the second ion implantation region 131 is less than the ion implantation depth of the first ion implantation region 12; the first ion implantation region 12 and the second ion implantation region 131 have the same doping type, but different from the doping type of the epitaxial wafer 10. The fabrication method for forming the Schottky region extension structure 13 includes: simultaneously forming the sub-trench adjacent to the first surface of the multi-level trench, forming a single-level trench 16 within the surface of the functional region A1; and simultaneously forming the second ion implantation region 131 while forming the first ion implantation region 12.

[0085] In other methods, the method of forming the Schottky region extension structure 13 includes: directly implanting an ion region into the device region A1 to form a trenchless ion implantation region as the Schottky region extension structure 13.

[0086] The manufacturing method is used to prepare Figure 2 Taking the JBS device shown as an example, the deep trench 11 is a two-stage trench, and the second ion implantation region 131 is formed based on the single-stage trench 16 in the surface of the functional region A1 as the Schottky region extension structure 13.

[0087] Specifically, step S12 includes:

[0088] First, such as Figure 8 As shown, a first-level sub-trench 111 and a single-level trench 16 are formed to create a multi-level trench. The first-level sub-trench 111 and the single-level trench 16 are simultaneously etched. The first surface B1 can be etched based on a mask layer to form the first-level sub-trench 111 and the single-level trench 16. The mask layer can be a stack of SiO layer and polysilicon layer.

[0089] The epitaxial wafer undergoes two or more photolithography and etching processes to form two-level trenches or multi-level trenches (more than two levels) as deep trenches. After the epitaxial wafer enters the production line, alignment marks are created for subsequent photolithography alignment. The technical solution of this application fabricates the first-level sub-trench 111 and the single-level trench 16 simultaneously with the creation of the alignment marks, eliminating the need for a separate etching process. The etching process for the alignment marks is reused to create the first-level sub-trench 111, reducing manufacturing costs.

[0090] Then, as Figure 9 As shown, other sub-trenches are formed to create multi-level trenches. Taking a two-level trench as an example, a second-level sub-trench 112 is formed based on the first-level sub-trench 111. In subsequent etching processes, the single-level trench 16 is blocked, and a mask with an etching window opening smaller than the opening width of the previous level sub-trench is used to sequentially form sub-trenches with gradually decreasing widths.

[0091] For the same deep trench 11, the sub-trenches in the direction from the first surface B1 to the second surface B2 are defined as the 1st to the nth level sub-trench, where n is a positive integer greater than 1. For two adjacent multi-level trenches, the distance between their i-th level sub-trenches is Li, where i is a positive integer not greater than n. Within the same multi-level trench, the depth of the i-th level sub-trench is ti. For example... Figure 9 As shown, taking deep trench 11 as a two-level trench as an example, the distance between two adjacent first-level sub-trenches is L1, and the distance between two adjacent second-level sub-trenches is L2; ​​in the same multi-level trench, the depth of the first-level sub-trench is t1, and the depth of the second-level sub-trench is t2.

[0092] For example Figure 10As shown, a mask 30 is used for ion implantation. A first ion implantation region 12 is formed based on a deep trench 11, and a second ion implantation region 131 is formed based on a single-level trench 16. The mask 30, which forms the desired pattern structure, is formed using a photolithography process. It has a first ion implantation window 31 and a second ion implantation window 32. Ion implantation is performed based on the first ion implantation window 31 to form the first ion implantation region 12, and ion implantation is performed based on the second ion implantation window 32 to form the second ion implantation region 131. During this process, a first electric field buffer implantation region 17 and a second electric field buffer implantation region 18 can be formed simultaneously.

[0093] Furthermore, a filling material is formed in the deep trench 11 and the single-stage trench 16. SiO2 or polycrystalline silicon can be used as the filling material via CVD. Alternatively, metal can be used as the filling material via PVD. It should be noted that when filling the trench structure with metal, it can be a single metal or a stack of multiple different metals. The metal filling material can form a Schottky base or ohmic contact with the trench sidewalls through an RTA (Regenerative Thermal Acrylation) process. Typical RTA annealing conditions for forming a Schottky contact are 400-550 degrees Celsius for 60 seconds to 3 minutes. If the metal in the trench forms an ohmic contact with the trench sidewalls, an MPS diode with better surge capability can be constructed. Typical RTA annealing conditions for ohmic contacts are 900-1100 degrees Celsius for 60 seconds to 5 minutes.

[0094] Furthermore, a first electrode 14 is formed on the first surface B1, and a second electrode 15 is formed on the lower surface of the substrate 102. The first electrode serves as the anode of the JBS device, and the second electrode 15 serves as the cathode of the JBS device. The first electrode 14 includes a Schottky contact metal (such as Ti or Mo) located on the first surface B1 and a metal electrode (such as Al) located on the surface of the Schottky metal. The Schottky contact metal can be formed using processes such as PVD. The Schottky contact metal forms a Schottky base with the first surface B1 through a rapid annealing (RTA) process at a specific temperature. The RTA conditions are 500°C and the annealing time is 60s-3min.

[0095] As described above, in this embodiment, multi-level trenches are used as deep trenches 11. In the trench region A2 of the epitaxial layer 101, sub-trenches of decreasing width from top to bottom are first etched, from the first level to the nth level. The widths between each level of sub-trench in two adjacent multi-level trenches are L1, L2, ..., Ln, where L1 < L2 < ... < Ln. Then, P+ ions are implanted at a certain angle in the deep trenches 11, and a ring of P+ doped regions is implanted around the sidewalls and bottom of the entire deep trenches 11 as the first ion implantation region 12. Simultaneously, a second electric field buffer implantation region 18 of a certain width is designed around the first-level sub-trench. The interval L0 < L1 between the second electric field buffer implantation regions 18 in two adjacent deep trenches. The second electric field buffer implantation region 18 can be formed using the same ion implantation process as the first ion implantation region 12, or it can be formed using different ion implantation methods. Subsequently, a filling material is formed in the deep trench 11. The filling material can be polycrystalline silicon or metal. The filling material is connected to the first electrode 14 to form a structure as shown in the image. Figure 2 The image shows a multi-stage trench diode device with a voltage buffer layer and a hybrid trench design.

[0096] Simultaneously, by combining deep trenches 11 with decreasing widths from top to bottom and a first ion implantation region 12 connected to the deep trenches 11, a novel hybrid trench JBS device is constructed, which can further improve the performance of multi-level trench diode devices. By setting the Schottky region extension structure 13, the spacing between the two multi-level deep trenches can be further increased, while maintaining a low Schottky surface electric field and a low reverse leakage current, increasing the flexibility of device design.

[0097] The above-described preparation method is used to prepare Figure 2 Or Figure 5 The Schottky region extension structure 13 shown in the illustration will be used as an example. When fabricating such a structure... Figure 4 Or Figure 6 The fabrication method for the Schottky region extension structure 13 shown is as follows: Figures 11-13 As shown:

[0098] First, such as Figure 11 As shown, a first-level sub-groove 111 is formed in the trench region A2.

[0099] Then, as Figure 12 As shown, a second-level sub-groove 112 is formed based on the first-level sub-groove 111.

[0100] For example Figure 13 As shown, ion implantation is performed based on a mask to form a first ion implantation region 12 and a Schottky region extension structure 13.

[0101] exist Figures 11-13In the illustrated method, it is not necessary to form a single-stage trench 16; other manufacturing processes are the same as described above, and will not be repeated in the embodiments of this application. Ultimately, a result as shown can be formed. Figure 4 Or Figure 6 The JBS device is shown.

[0102] In the manufacturing method described in this application embodiment, the structure in the terminal area A3 and the process of manufacturing the cutting area 20 are the same as the existing process, and the manufacturing method described in this application embodiment will not be repeated.

[0103] refer to Figure 14 As shown, Figure 14 This is a SEM image of the JBS device formed by the fabrication method described in the embodiments of this application. The method is illustrated using the second ion implantation region 131 formed based on a single-level trench 16 as an example of the Schottky region extension structure 13. According to... Figure 14 As shown in the SEM image, the JBS device formed using the fabrication method described in the embodiments of this application has a good trench etching effect.

[0104] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0105] It should be noted that, in the description of this application, the drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0106] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0107] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0108] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A junction barrier Schottky diode device, characterized in that, include: Epitaxial wafer, having an epitaxial layer; The epitaxial layer has a first surface and a second surface opposite to each other; the first surface has a functional region and a trench region located on both sides of the functional region; Deep trenches are located within the surface of the trench area; The first ion implantation region is located within the surface of the sidewalls and bottom of the deep trench; The Schottky region extension structure has a width on the first surface that is smaller than the opening width of the deep trench on the first surface. It is located within the functional area surface between two adjacent deep trenches and is used to increase the area of ​​the Schottky region between two adjacent deep trenches. The Schottky region extension structure includes: a second ion implantation region located within the surface of the functional region; wherein the implantation depth of the second ion implantation region is less than the ion implantation depth of the first ion implantation region; the first ion implantation region and the second ion implantation region have the same doping type, but different from the doping type of the epitaxial wafer; The deep trench is a multi-level trench, which includes a plurality of sub-trenches arranged sequentially in a first direction; the first direction is the direction in which the opening of the deep trench points to the bottom; in the same deep trench, in two adjacent sub-trenches, the width of the sub-trench closer to the bottom of the deep trench is smaller than the width of the sub-trench farther from the bottom of the deep trench. The functional area has a single-level trench, the depth of which is less than the depth of the deep trench; wherein, the second ion implantation area is located within the surface of the sidewall and bottom of the single-level trench; In the deep trench, the sub-trench adjacent to the first surface is the first-level sub-trench; The single-level trench has the same depth as the first-level sub-trench, and the single-level trench and the first-level sub-trench of the deep trench are formed simultaneously.

2. The junction barrier Schottky diode device according to claim 1, characterized in that, In the multi-level trenches, the width of the same sub-trench remains unchanged in the first direction; The width of the single-stage trench remains unchanged.

3. The junction barrier Schottky diode device according to claim 1, characterized in that, The surface of the functional area has a first electric field buffer injection region, which surrounds the opening of the single-stage trench and is used to increase the thickness of the second ion implantation region near the opening on the sidewall of the single-stage trench.

4. The junction barrier Schottky diode device according to claim 1, characterized in that, The surface of the trench region has a second electric field buffer injection region, which surrounds the opening of the deep trench and is used to increase the thickness of the first ion implantation region near the opening on the sidewall of the deep trench.

5. The junction barrier Schottky diode device according to claim 1, characterized in that, The Schottky region extension structure is located between two adjacent deep trenches.

6. A method for fabricating a junction barrier Schottky diode device as described in any one of claims 1-5, characterized in that, include: An epitaxial wafer is provided, having an epitaxial layer; The epitaxial layer has a first surface and a second surface opposite to each other; the first surface has a functional region and a trench region located on both sides of the functional region; A deep trench is formed in the surface of the trench area, and a Schottky region extension structure is formed in the surface of the functional area between two adjacent deep trenches. The width of the Schottky region extension structure on the first surface is smaller than the opening width of the deep trench on the first surface. The Schottky region extension structure is used to increase the area of ​​the Schottky region between two adjacent deep trenches; The trench has a first ion implantation region on its sidewalls and bottom; The deep trench is a multi-level trench, which includes a plurality of sub-trenches arranged sequentially in the first direction; The first direction is the direction in which the opening of the deep trench points to the bottom; in the same deep trench, in two adjacent sub-grooves, the width of the sub-grooves closer to the bottom of the deep trench is smaller than the width of the sub-grooves farther from the bottom of the deep trench; The method for forming the first ion implantation region includes: Ion implantation is performed based on the multi-level trenches, forming the first ion implantation region on the sidewalls and bottom of each sub-trench; The Schottky region extension structure includes: a second ion implantation region located within the surface of the functional region; wherein the implantation depth of the second ion implantation region is less than the ion implantation depth of the first ion implantation region; the first ion implantation region and the second ion implantation region have the same doping type, but different from the doping type of the epitaxial wafer; The method for forming the Schottky region extension structure includes: While forming the sub-grooves adjacent to the first surface of the multi-level trenches, a single-level trench is formed within the surface of the functional area. The second ion implantation region is formed simultaneously with the formation of the first ion implantation region.

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