Vertical Cavity Surface Emitting Laser

Abstract

Several VCSEL devices for long wavelength applications in the wavelength range of 1200 nm to 1600 nm are described. These devices include an active region between a semiconductor DBR on a GaAs wafer and a dielectric DBR regrown on the active region. The active region includes a multi-quantum layer (MQL) confined between active n‑InP and p‑InAlAs layers and a tunnel junction layer above the MQL. The semiconductor DBR is fused to the bottom of the active region by a wafer bonding process. The design simplifies the integrated reflector and active region stack by bonding only one wafer and then regrowing the other layers including the dielectric DBR. An air gap is fabricated in an air gap spacer layer on top of the n‑InP layer of the active region or the semiconductor DBR. The air gap enhances the optical confinement of the VCSEL. The air gap may also contain a grating.

Description

Technical Field

[0001] Embodiments described herein relate to lasers for fiber optic data and analog transmission, and more particularly, to the design and fabrication of long wavelength VCSELs with optical confinement. Background Art

[0002] The use of vertical cavity surface emitting lasers (VCSELs) for light transmission in fiber optic systems provides multiple advantages over commonly used edge emitting lasers. For example, VCSELs require less power consumption and can be manufactured more efficiently than edge emitting lasers. One aspect of this efficiency is provided by the on-wafer testing capability of VCSELs. The ability to perform on-wafer testing creates a considerable cost advantage compared to conventional testing techniques for edge emitting lasers. In addition, VCSELs provide reliable operation over time, which is critical for applications in fiber optic systems.

[0003] While the design and fabrication of reliable short-wavelength VCSELs by processing epitaxial structures grown on gallium arsenide (GaAs) substrates is well developed and accepted by the mass production industry, the design and fabrication of long-wavelength (LW) VCSELs in the wavelength range of 1200nm to 1650nm has not yet reached the same level of maturity, both from a performance and reliability perspective, and from a cost-per-chip perspective.

[0004] The state-of-the-art designs for the long-wave active region include indium phosphide (InP)-based multi-quantum layer (MQL) structures, buried tunnel junctions (TJs) for lateral current and optical confinement, and intracavity contact schemes. Among all the known designs and fabrication approaches for LW VCSELs, only those VCSEL designs with wafer-fused GaAs-based distributed Bragg reflectors (DBRs) and InP-based active regions have been reported to show credible reliable operation.

[0005] The advantage of the wafer-fused design and manufacturing approach is to provide the best possible heat sink from the MQL in the active area, and this thermal management is critical for reliable operation. The manufacturing process for long-wavelength VCSELs using a double-fused structure is very similar to that for short-wavelength VCSELs.

[0006] However, among the several disadvantages of the wafer fusion design, the most important ones are: (i) one InP and one GaAs substrate are sacrificed; (ii) the epitaxial growth of semiconductor distributed Bragg reflector DBR layers is more expensive than DBRs formed from dielectric materials; and (iii) the bonding process is highly sensitive to the surface morphology of the epitaxially grown wafer. The main difficulty in obtaining an acceptable bonding morphology is the regrowth of InP on the patterned TJ, which forms a non-planar wafer surface.

[0007] Last but not least, after the InP wafer is bonded to GaAs, the wafer fusion at high temperature can cause the size scaling of the pattern on the InP wafer because the different wafer materials may have mismatched thermal expansion coefficients. If the pattern on the InP wafer portion will match the pattern on the GaAs wafer after bonding, the size scaling problem can be avoided.

[0008] Dielectric DBRs have been used in alternative design and manufacturing methods. In their most advanced applications, VCSELs made with dielectric DBRs contain very small amounts of semiconductor material sandwiched between two dielectric DBRs on two thick metal layers. This potentially low-cost design and manufacturing process for VCSELs has the advantage of using dielectric DBRs with high refractive index contrast. However, the manufacturing process for this design is less mature and less reliable for both short- and long-wavelength VCSELs using a dual-fused wafer structure. So far, this type of heterogeneous integration of semiconductors with dielectric and metallic materials has not been widely accepted by the industry for large-scale VCSEL manufacturing.

[0009] To fabricate a VCSEL with dielectric DBRs on both sides, the main design limitation is the inherently high thermal resistance, since the MQL located in the optical and current confinement region is sandwiched from both sides by dielectric DBRs of low thermal conductivity. Further optimization of the VCSEL structure using double-sided DBRs usually involves integrating a metal matrix material (usually gold). This results in increased manufacturing costs and reduced reliability of the VCSEL after subassembly system-level packaging.

[0010] In today's market, there is a huge demand for numerous applications of LW VCSELs with design and manufacturing process solutions that are comparable to standard short-wavelength VCSEL technology in terms of performance, reliability and cost.

[0011] Therefore, it is necessary to find innovative LW VCSEL designs and feasible manufacturing processes to improve the performance and reliability of single-mode and multi-mode LW VCSEL devices at an affordable cost. Summary of the invention

[0012] An exemplary embodiment of a vertical cavity surface emitting laser (VCSEL) includes the following elements: a first substrate; a first reflector disposed on the first substrate, wherein the first reflector includes a distributed Bragg reflector (DBR), the distributed Bragg reflector including multiple layers of alternating semiconductor materials; a second reflector, wherein the second reflector includes a distributed Bragg reflector (DBR), the distributed Bragg reflector including multiple alternating dielectric layers; and an active region structure, the active region structure disposed between the first reflector and the second reflector.

[0013] The bottom of the active area and the top of the first reflector form a fusion interface layer through a wafer bonding process.

[0014] The active region structure comprises: a multi-quantum well and / or quantum dot layer of a VCSEL gain medium (MQL), wherein the MQL is disposed between a first group of active semiconductor layers at a bottom side facing the first reflector and a second group of active semiconductor layers at a top side facing the second reflector; wherein the first group of active semiconductor layers comprises a first semiconductor layer disposed in direct contact with the MQL and a second semiconductor layer disposed away from the MQL; wherein a first etch stop layer is disposed between the first semiconductor layer and the second semiconductor layer to define a patterning process of the active region structure so as to provide a space for a cathode layer; and wherein the second group of active semiconductor layers at the top side of the MQL The layers include a third semiconductor layer arranged to be in direct contact with the MQL, a fourth semiconductor layer arranged above the third semiconductor layer away from the MQL; a tunnel junction layer, which is arranged above the fourth semiconductor layer and is patterned to overlap with a portion of the MQL, wherein a second etch stop layer is arranged between the fourth semiconductor layer and the tunnel junction layer to define a patterning process of the tunnel junction layer; and a fifth semiconductor layer, which is above the tunnel junction layer and the second etch stop layer; wherein the second reflector is fabricated on the fifth semiconductor layer, and wherein an anode layer is arranged on the fifth semiconductor layer close to the second reflector.

[0015] In some cases, the VCSEL is configured to emit laser light at a wavelength in a range of 1200 nanometers (nm) to 1650 nm.

[0016] In some cases, the multiple layers of alternating semiconductor material in the first reflector include undoped aluminum gallium arsenide (AlGaAs) and gallium arsenide (GaAs) layers.

[0017] In some cases, the plurality of alternating dielectric layers in the second reflector includes alternating pairs of silicon and silicon oxide layers arranged with a period of one quarter of the laser wavelength.

[0018] In some cases, the first semiconductor layer and the second semiconductor layer are both n-doped indium phosphide (n-InP) layers.

[0019] In some cases, the third semiconductor layer and the fifth semiconductor layer are both n-doped indium phosphide (n-InP) layers, and wherein the fourth semiconductor layer is a p-doped indium aluminum arsenate (p-InAlAs) layer.

[0020] In some cases, the tunnel junction layer includes n++ doped InGaAlAs and p++ doped InGaAlAs.

[0021] In some cases, the first substrate is a GaAs wafer.

[0022] In some cases, the VCSEL further includes: a cathode pad arranged on the first reflector, wherein the cathode pad includes a cathode dielectric DBR stack, a polymer layer on the cathode dielectric DBR stack, and a metal cathode electrode on the polymer layer, wherein the metal cathode electrode is connected to the cathode layer; and an anode pad arranged on the first reflector, wherein the anode pad includes an anode dielectric DBR stack, a polymer layer on the anode dielectric DBR stack, and a metal anode electrode on the polymer layer, wherein the metal anode electrode is connected to the anode layer.

[0023] Another exemplary embodiment of a VCSEL includes: a first substrate; a first reflector disposed on the first substrate, wherein the first reflector includes a distributed Bragg reflector (DBR), which includes multiple layers of alternating first semiconductor material and second semiconductor material; a second reflector, wherein the second reflector includes a distributed Bragg reflector (DBR), which includes multiple alternating dielectric layers; and an active area structure, wherein the active area structure is disposed between the first reflector and the second reflector.

[0024] The VCSEL further includes an air-gap spacer layer including an air gap and an air-gap etch stop layer formed on the first reflector, wherein the air-gap spacer layer includes the first semiconductor material and the air-gap etch stop layer includes the second semiconductor material.

[0025] The bottom of the active area and the top of the air gap spacer layer form a fusion interface layer through a wafer bonding process.

[0026] Further, the active region structure comprises: an MQL, wherein the MQL is disposed between a first group of active semiconductor layers facing a bottom side of the first reflector and a second group of active semiconductor layers facing a top side of the second reflector.

[0027] The first group of active semiconductor layers includes a first semiconductor layer disposed in direct contact with the MQL and a second semiconductor layer disposed away from the MQL; wherein a first etch stop layer is disposed between the first semiconductor layer and the second semiconductor layer to define a patterning process of the active area structure so as to provide space for a cathode layer.

[0028] The second group of active semiconductor layers on the top side of the MQL includes a third semiconductor layer disposed in direct contact with the MQL, and a fourth semiconductor layer disposed above the third semiconductor layer away from the MQL.

[0029] A tunnel junction layer is disposed above the fourth semiconductor layer and patterned to overlap with a portion of the MQL, wherein a second etch stop layer is disposed between the fourth semiconductor layer and the tunnel junction layer to define a patterning process of the tunnel junction layer; and a fifth semiconductor layer, the fifth semiconductor layer being above the tunnel junction layer and the second etch stop layer; wherein the second reflector is fabricated on the fifth semiconductor layer, and wherein an anode layer is disposed on the fifth semiconductor layer adjacent to the second reflector.

[0030] Another exemplary embodiment of a VCSEL includes: a first substrate; a first reflector disposed on the first substrate, wherein the first reflector includes a distributed Bragg reflector (DBR), which includes multiple layers of alternating first semiconductor material and second semiconductor material; a second reflector, wherein the second reflector includes a distributed Bragg reflector (DBR), which includes multiple alternating dielectric layers; and an active area structure, wherein the active area structure is disposed between the first reflector and the second reflector.

[0031] The bottom of the active region and the top of the first reflector form a fusion interface layer through a wafer bonding process.

[0032] Further, the active area structure includes: a MQL, wherein the MQL is arranged between a first group of active semiconductor layers at the bottom side facing the first reflector and a second group of active semiconductor layers at the top side facing the second reflector; wherein the first group of active semiconductor layers includes a first semiconductor layer arranged in direct contact with the MQL and a second semiconductor layer arranged away from the MQL.

[0033] An air gap is formed in the second semiconductor layer above the fusion interface layer; a first etch stop layer is arranged between the first semiconductor layer and the second semiconductor layer to define the patterning process of the active area structure so as to provide a space for a cathode layer; and the second group of active semiconductor layers on the top side of the MQL includes a third semiconductor layer arranged in direct contact with the MQL and a fourth semiconductor layer arranged above the third semiconductor layer away from the MQL.

[0034] A tunnel junction layer is disposed above the fourth semiconductor layer and patterned to overlap with a portion of the MQL, wherein a second etch stop layer is disposed between the fourth semiconductor layer and the tunnel junction layer to define a patterning process of the tunnel junction layer; and a fifth semiconductor layer, the fifth semiconductor layer being above the tunnel junction layer and the second etch stop layer.

[0035] The second reflector is fabricated on the fifth semiconductor layer, and an anode layer is disposed on the fifth semiconductor layer adjacent to the second reflector.

[0036] Furthermore, the air gap comprises a grating structure, wherein the grating structure is aligned with the tunnel junction and is characterized by enhancing optical confinement of the VCSEL laser. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Having thus generally described the invention, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale.

[0038] Figure 1A and Figure 1B A schematic cross-sectional view showing the general design of a vertical cavity surface emitting laser (VCSEL) according to the present disclosure;

[0039] Figure 2A and Figure 2B illustrates a schematic cross-sectional view of a VCSEL device including an air gap in a GaAs portion of the structure according to an exemplary embodiment of the present disclosure;

[0040] Figure 3A and Figure 3B illustrates a schematic cross-sectional view of a VCSEL device including an air gap in the InP portion of the structure according to an exemplary embodiment of the present disclosure;

[0041] Figure 4 illustrates a schematic cross-sectional view of a VCSEL device including a dielectric layer as a part of a contact pad in a top DBR according to an exemplary embodiment of the present disclosure;

[0042] Figure 5 illustrates a schematic cross-sectional view of a VCSEL device having a grating formed on the bottom of an air gap on top of a bottom GaAs DBR according to an exemplary embodiment of the present disclosure;

[0043] Figure 6 illustrates a schematic cross-sectional view of a VCSEL device having a grating on the InP base side of an air gap according to an exemplary embodiment of the present disclosure; and

[0044] 7A and 7B illustrate schematic cross-sectional views of a VCSEL device having a grating disposed on a fusion interface according to other embodiments of the present disclosure. DETAILED DESCRIPTION

[0045] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which some but not all embodiments of the present invention are shown. In fact, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like numbers refer to like elements throughout the text.

[0046] In various embodiments, description is made with reference to the accompanying drawings. However, certain embodiments may be implemented without one or more of these specific details, or in combination with other known methods and configurations. In the following description, many specific details, such as specific configurations, dimensions, and processes, etc., are set forth in order to provide a thorough understanding of the embodiments. In other cases, well-known processes and manufacturing techniques are not particularly described in detail in order to avoid unnecessarily obscuring the embodiments. References to "one embodiment" throughout the specification mean that specific features, structures, configurations, or characteristics described in conjunction with the embodiments are included in at least one embodiment. Therefore, the appearance of the phrase "in one embodiment" in various places throughout the specification does not necessarily refer to the same embodiment. In addition, features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments. Similarly, unless otherwise stated, the term "exemplary" is used to describe exemplary embodiments and does not mean that the described embodiments are superior to other embodiments.

[0047] As used herein, the terms "over," "across," "to," "between," and "over" may refer to the relative position of one layer with respect to other layers. A layer that is "over," "across," or "on," or "bonded to," or "in contact with" another layer may be in direct contact with the other layer or may have one or more intervening layers. A layer "between" layers may be in direct contact with the layers or may have one or more intervening layers.

[0048] The present invention proposes ways and means to combine the best of existing technologies in LW VCSEL design and fabrication to improve the performance and reliability of single-mode and multi-mode LW VCSEL devices at an affordable cost.

[0049] The present invention proposes bonding an InP-based MQL with buried TJ active material to a GaAs-based DBR bottom specular reflector (which is typically a good heat sink), but for the top output DBR reflector, the proposed approach uses a dielectric-based material instead of GaAs, with the following benefits: (a) taking advantage of its potential low cost, (b) dual use of the dielectric as a contact pad, (c) the intrinsic potential will be deposited on a non-planar surface and with a non-perfect morphology compared to what is currently required in existing techniques for wafer bonding, and (d) increased vertical intra-cavity optical confinement of the VCSEL due to the high contrast of the refractive index of the dielectric to the semiconductor GaAs-based material (such as the DBR).

[0050] The present invention also proposes to perform regrowth of TJs for lateral current and optical confinement in sequence after the step of wafer bonding process which will eliminate dimensional scaling.

[0051] Furthermore, the present invention describes a way to implement an intracavity air gap at the interface of the InP-based MQL gain wafer and the bottom specular GaAs-based DBR reflector in order to further increase the intracavity vertical optical confinement. The introduction of an air gap layer with a low refractive index value of 1.0 has the benefit of further reducing the total number of bottom GaAs DBR layers without affecting the vertical optical confinement of the VCSEL device. Designing the lateral geometry of the air gap and the fabrication process allows control of the single-mode and / or multi-mode lateral optical confinement as well as the laser beam polarization of the VCSEL device.

[0052] In the manufacturing process sequence, the present invention proposes: (1) patterning and processing air gaps at the surface of the InP-based active area or GaAs bottom DBR wafer; (2) applying only a single bonding of two wafers after (1); (3) reversing the order of wafer bonding and TJ regrowth compared to the first bonding in the existing scheme, so that the process includes: first transferring the epitaxial structure onto the bottom DBR on the GaAs substrate, the epitaxial structure having the last layer (which is the TJ layer), and then continuing to pattern and further regrow the n-InP upper electrical contact layer.

[0053] In this way, having only one bonding process to combine the wafer with the dielectric material deposited as the second (output) DBR reflector has several advantages:

[0054] i. Forming the air gap body as part of strong vertical and lateral VCSEL optical confinement before the bonding process;

[0055] ii. Single bonding on wafers with good planar morphology and low surface defect density before TJ patterning and regrowth of n-InP electrical contacts which significantly improves the yield of the wafer bonding process;

[0056] iii. Due to the sequential patterning of TJs and regrowth after the bonding process, the size scaling issue is eliminated;

[0057] iv. The requirements for the regrowth morphology of the dielectric material DBR layer deposition are much more relaxed compared to the requirements for wafer bonding;

[0058] v. The regrowth process by metal oxide chemical vapor deposition (MOCVD) and / or molecular beam epitaxy (MBE) techniques has more engineering freedom because the requirements on the regrowth surface morphology and tolerance are relaxed;

[0059] vi. The dielectric layer in the top DBR introduces new degrees of freedom for optimizing device design: positioning the p-contact closer to the current hole to reduce series resistance, sharing the dielectric DBR layer as contact pad and surface passivation, all of which improve performance and reliability.

[0060] Several proposed embodiments of VCSEL devices are depicted in FIGS. 1 to 7 according to the present disclosure.

[0061] Figure 1A A schematic cross-sectional view of the overall design of a vertical cavity surface emitting laser (VCSEL) according to the present disclosure is shown. Figure 1B Shows Figure 1A Detailed structure of the core part of the VCSEL device.

[0062] Typically, a VCSEL device includes a lower wafer portion and an upper regrown portion. The lower wafer portion will be bonded to the upper regrown portion by a fusion process. The lower wafer portion includes a semiconductor wafer and a bottom GaAs DBR. The semiconductor wafer can be a GaAs wafer or a GaAs plate of a substrate. The upper regrown portion includes an active layer in the optical cavity and a dielectric-based top DBR reflector instead of a semiconductor-based top reflector. Additional features such as air gaps and gratings are introduced to enhance optical confinement in the active cavity. A dielectric DBR layer can also be added to the electrical interconnect structure. The specific design and structure will be disclosed in detail in the following figures Figures 1 to 7.

[0063] exist Figure 1A In the embodiment of the present invention, the VCSEL device 100 includes a bottom GaAs substrate 110, a bottom distributed Bragg reflector (DBR) including gallium arsenide, and an aluminum gallium arsenide layer (GaAs / AlGaAs) 120 fabricated on the bottom substrate 110. A stack of core layers 150 including an MQL 151 and a tunnel junction (TJ) 160 is attached to the top of the bottom DBR 120, and an attachment interface 157 is fused between the bottom DBR 120 and the bottom of the stack 150. A top dielectric distributed Bragg reflector (DBR) 140 is attached to the top of the stack 150.

[0064] Figure 1B The core stack 150 shown includes an MQL 151. There is an intermediate n-InP (n-doped InP) layer 153 below the MQL 151, and another thicker n-InP layer 156 above the fusion interface 157. The intermediate active n-InP layer 153 is patterned to provide space for a cathode layer 159 fabricated on the thicker n-InP layer 156. An etch stop layer 155 may be formed on the lower n-InP layer 156 for properly patterning the core stack 150.

[0065] Above the MQL 151, the stack 150 also includes an n-InP layer 154 formed on the MQL 151, a p-InAlAs layer 155, and a TJ layer 160 patterned on the p-InAlAs layer 155. In some cases, there may be an etch stop layer i-InP on the p-InAlAs to better define the patterning. A thicker n-InP layer 152 is deposited on the TJ layer 160, serving as an active InP base structure and an electrical n-InP contact re-growth layer on the p-InAlAs 155. A top dielectric DBR column 140 is deposited on top of the n-InP layer 152. A thin anode contact layer 158 is deposited on the n-InP layer 152 close to the top dielectric layer 140, and in some cases (as an option) is partially covered by the layer of the top dielectric DBR 140. This will allow the diameter of the top DBR column 140 to be much higher than the diameter of the TJ 160.

[0066] Figure 2A A schematic cross-sectional view of a VCSEL device including an air gap in the GaAs portion of the structure according to a second embodiment of the present disclosure is illustrated. Figure 2B Shows Figure 2A The second embodiment of the present invention describes a structure with a built-in air gap in the cavity.

[0067] exist Figure 2A In the embodiment, the VCSEL device 200 includes a bottom GaAs substrate 210, a bottom distributed Bragg reflector (DBR) containing gallium arsenide, and an aluminum gallium arsenide paired layer (GaAs / AlGaAs) 220 fabricated on the bottom substrate 210. Before bonding, there is a recess for the air gap 280 formed in the GaAs base portion. To this end, the bottom DBR 220 has an additional GaAs layer that will serve as an air gap spacer 281 and an AlGaAs etch stop layer 282 (with the conventional DBR structure 220) on top. Figure 1B compared to the structure depicted in ).

[0068] A stack of core layers 250 including MQL 251 and tunnel junction (TJ) 260 is attached on top of air gap spacer layer 281 above bottom DBR 220, and interface 257 is fused between air gap spacer layer 281 and the bottom of InP layer above bottom DBR 220. A top dielectric distributed Bragg reflector (DBR) 240 is attached to the top of stack 250.

[0069] Figure 2B The core stack 250 shown includes an MQL 251. There is an intermediate n-InP (n-doped InP) layer 253 below the MQL 251, and there is another thicker n-InP layer 256 above the fusion interface 257. The intermediate active n-InP layer 253 is patterned to provide space for a cathode layer 259 fabricated on the thicker n-InP layer 256. An etch stop layer 255 can be formed on the lower n-InP layer 256 for properly patterning the core stack 250.

[0070] On the MQL 251, the stack 250 also includes an active layer of n-InP 254 formed on the MQL 251, a p-InAlAs layer 255, a TJ layer 260 patterned on the p-InAlAs layer 255, and there may be an etch stop layer i-InP on the p-InAlAs layer 255 to better define the patterning. A thicker n-InP layer 252 is deposited on the TJ 260, serving as an active InP base structure and an electrical n-InP contact re-growth layer on the p-InAlAs 255. A top dielectric DBR column 240 is deposited on top of the n-InP layer 252. A thin anode contact layer 258 is deposited on the n-InP layer 252 close to the top dielectric layer 240, and in some cases (as an option) is partially covered by the layer of the top dielectric DBR 240. This will allow the diameter of the top DBR column 240 to remain much higher than the diameter of the TJ 260.

[0071] Figure 3A A schematic cross-sectional view of a VCSEL device including an air gap in the InP portion of the structure according to an exemplary embodiment of the present disclosure is illustrated. Figure 3B Shows Figure 3A The third embodiment of the present invention depicts a structure with a built-in air gap in the InP part of the cavity.

[0072] exist Figure 3AIn the embodiment, the VCSEL device 300 includes a bottom GaAs substrate 310 and a bottom distributed Bragg reflector (DBR) including gallium arsenide and aluminum gallium arsenide paired layers (GaAs / AlGaAs) 320 fabricated on the bottom substrate 310. Before the GaAs / AlGaAs DBR 320 is bonded to the substrate 310, there is a void for the air gap 380 formed in the n-InP base portion 356. The bottom DBR 320 does not have an additional GaAs layer (with Figure 2B compared to the structure depicted in ).

[0073] A stack of core layers 350 including MQL 351 and tunnel junction (TJ) 360 is attached on top of the bottom DBR 320, and an attachment interface 357 is fused between the InP layer 356 where the air gap is located and the top of the bottom DBR 320. A top dielectric distributed Bragg reflector (DBR) 240 is attached to the top of the stack 250.

[0074] Figure 3B The core stack 350 shown includes an MQL 351. Below the MQL 351 there is an intermediate active n-InP (n-doped InP) layer 353 and a thicker n-InP layer 356 with an air gap located at a fusion interface 357. The intermediate active n-InP layer 353 is patterned to provide space for a cathode layer 359 fabricated on the thicker n-InP layer 356. An etch stop layer may be formed on the lower n-InP layer 356 for properly patterning the core stack 350.

[0075] On the MQL 351, the stack 350 also includes an active layer of n-InP 354 formed on the MQL 351, a p-InAlAs layer 355, a TJ layer 360 patterned on the p-InAlAs layer 355, and in some cases, there may be an etch stop layer i-InP on the p-InAlAs layer 355 to better define the patterning. A thicker n-InP layer 352 is deposited on the TJ 360, serving as an active InP base structure and an electrical n-InP contact re-growth layer on the p-InAlAs 355. A top dielectric DBR column 340 is deposited on top of the n-InP layer 352. A thin anode contact layer 358 is deposited on the n-InP layer 352 close to the top dielectric layer 340, and in some cases (as an option) is partially covered by the layer of the top dielectric DBR 340. This will allow the diameter of the top DBR column 340 to remain much higher than the diameter of the TJ 360. Figure 3B Also shown is a picture of one possible arrangement in an embodiment that proposes making an air gap 380 in an InP based structure prior to bonding. For those skilled in the art, in view of this disclosure it will be appreciated that this is just one of several possible configurations.

[0076] Figure 4 A schematic cross-sectional view of a VCSEL device including a dielectric layer as a part of a contact pad in a top DBR according to an exemplary embodiment of the present disclosure is illustrated.

[0077] exist Figure 4 In FIG. 4 , the VCSEL device 400 includes a bottom GaAs substrate 410, a bottom distributed Bragg reflector (DBR) including gallium arsenide, and a pair of aluminum gallium arsenide layers (GaAs / AlGaAs) 420 fabricated on the bottom substrate 410. There is a recess formed in the GaAs base portion for the air gap 480. Similar to FIG. Figure 2A In the device in FIG. 4 , the bottom DBR 420 has an additional GaAs layer that will serve as an air gap spacer 481 on top of the conventional DBR structure 420. The MQL 451 is sandwiched between the n-InP layer 456 below the MQL and 453 above the MQL. A TJ layer 460 is fabricated above the MQL layer 451.

[0078] A top dielectric DBR 440 is fabricated on the n-InP layer above the TJ 460 as a top reflector for optical confinement. The other two dielectric DBRs 441 and 442 are fabricated as electrical contact pads. The top dielectric DBR 441 is built on the bottom GaAs / AlGaAs DBR 420 on one side of the active stack to serve as a contact pad for the cathode layer 459. DBR 442 is built on the bottom GaAs / AlGaAs DBR 420 on the other side of the active stack to serve as a contact pad for the anode layer 458. Both DBRs 441 and 442 are covered with a polymer layer (e.g., BCB, B-grade bisbenzocyclobutene). The cathode pad 441 is connected to the n-InP layer 456 below the MQL 451, and the anode pad 442 is connected to the n-InP layer 453 on the MQL 451. A metal electrode, typically gold (Au), serves as a lead connected to the contact pad 441 or 442 .

[0079] The dielectric layer of the top DBR can form part of the contact pad to reduce the contact pad capacitance. This possibility can be applied to all configurations of the air gap.

[0080] Figure 5 A schematic cross-sectional view of a VCSEL device having a grating formed on the bottom of an air gap on top of a bottom GaAs DBR according to an exemplary embodiment of the present disclosure is illustrated. Figure 5 In , a grating is used as an extra-cavity optical element for optical mode control at the bottom of an air gap formed on top of a bottom GaAs DBR.

[0081] exist Figure 5In the embodiment, the VCSEL device 500 includes a lower wafer portion and an upper regrown portion. The lower wafer portion will be bonded to the upper regrown portion by a fusion process. The lower wafer portion includes a semiconductor wafer, a bottom DBR, and a grating in an air gap. The semiconductor wafer can be a GaAs wafer or a GaAs plate of a substrate ( Figure 5 ), a bottom distributed Bragg reflector (DBR) comprising a gallium arsenide and aluminum gallium arsenide paired layer (GaAs / AlGaAs) 520 fabricated on a GaAs substrate. Before the lower portion is bonded to the active cavity, there is a recess for the air gap 580 formed in the GaAs layer on top of the DBR 520. For this purpose, the bottom DBR 520 has an additional GaAs layer that will serve as an air gap spacer 581 and an AlGaAs etch stop layer 586 (with the air gap spacer 581) on top of the conventional DBR structure 520 below the air gap spacer 581. Figure 1B 580). The grating 590 is patterned on the bottom surface of the air gap on top of the bottom GaAs DBR 520 by a photolithography / etching process as an extra-cavity optical element for optical mode control. Grating 590 fabrication requires high-resolution patterning compared to patterning the air gap. Typically, electron beam or photolithography can be applied to achieve the desired grating resolution. Two etch stop layers 585 and 586 are included to define two types of structures, as 586 is used to stop the etching of the air gap, and 585 is used to stop the etching of the grating features in the air gap 580.

[0082] The layer stack above the semiconductor substrate, DBR and air-gap grating structure includes an active optical cavity, a top reflector and electrical interconnects. The active optical cavity includes an MQL 551. Below the MQL 551 there is an n-InP (n-doped InP) layer 553 and another thicker n-InP layer 556.

[0083] When the lower portion is wafer bonded to the upper active cavity, a fusion layer 557 is formed between the air gap spacer layer 581 and the thick n-InP layer. The middle active n-InP layer 553 is patterned to provide space for the cathode layer 559 fabricated on the thicker n-InP layer 556.

[0084] The active cavity in the regrown layer also includes an n-InP 554 layer formed on the MQL 551, a p-InAlAs layer 555, a TJ layer 560 patterned on the p-InAlAs layer 555, and in some cases an etch stop layer ( Figure 5560) to better define the patterning of the TJ 560. The thicker n-InP layer 552 is regrown by deposition on the TJ 560, serving as the active InP base structure and the electrical n-InP contact regrown layer on the p-InAlAs 555. The top dielectric DBR pillar 540 is deposited on top of the n-InP layer 552. A thin anode contact layer 558 is deposited on the n-InP layer 552 close to the top dielectric DBR layer 540, and in some cases (as an option) is partially covered by the layers of the top dielectric DBR 540. This will allow the diameter of the top DBR pillar 540 to remain much higher than the diameter of the TJ 560.

[0085] The dielectric DBR layer 540 is formed of multiple pairs of Si and SiOx layers. The difference in refractive index of Si and SiOx arranged at a quarter period of the wavelength of the long-wave infrared light forms a highly reflective surface as a top reflector of the optical cavity.

[0086] Figure 6 A schematic cross-sectional view of a VCSEL device with a grating in an air gap in an InP layer according to an exemplary embodiment of the present disclosure is illustrated. The grating is used as an intracavity optical element for mode control on the InP-based side of the air gap.

[0087] exist Figure 6 In the embodiment, the VCSEL device 600 includes a lower wafer portion and an upper regrown portion. The lower wafer portion will be bonded to the upper regrown portion by a fusion process. The lower wafer portion includes a semiconductor wafer and a bottom DBR. The semiconductor wafer can be a GaAs wafer or a GaAs plate of a substrate ( Figure 6 ) and a bottom distributed Bragg reflector (DBR) comprising a gallium arsenide and aluminum gallium arsenide paired layers (GaAs / AlGaAs) 620 fabricated on a GaAs substrate.

[0088] The layer stack above the semiconductor substrate and DBR includes an active optical cavity, a top reflector, and electrical interconnects. The active optical cavity includes an MQL 651, an active n-InP (n-doped InP) layer 653 below the MQL 651, and another thicker n-InP layer 656. A fusion layer 657 is disposed between the lower GaAs DBR 620 and the thicker n-InP 656. A recess may be patterned and formed in the thicker n-InP layer 656 as an air gap 680 before bonding. The middle active n-InP layer 653 is patterned to provide space for a cathode layer 659 fabricated on the thicker n-InP layer 656.

[0089] The active cavity in the regrown layer also includes an n-InP 654 layer formed on the MQL 651, a p-InAlAs layer 655, a TJ layer 660 patterned on the p-InAlAs layer 655, and in some cases an etch stop layer ( Figure 6 660) to better define the patterning of the TJ 660. The thicker n-InP layer 552 is regrown by deposition on the TJ 660, serving as the active InP base structure and the electrical n-InP contact regrown layer on the p-InAlAs 655. The top dielectric DBR pillar 640 is deposited on top of the n-InP layer 652. A thin anode contact layer 658 is deposited on the n-InP layer 652 close to the top dielectric layer 640, and in some cases (as an option) is partially covered by the layer of the top dielectric DBR 640. This will allow the diameter of the top DBR pillar 640 to remain much higher than the diameter of the TJ 660.

[0090] The dielectric DBR layer 640 is formed of multiple pairs of Si and SiOx layers. The difference in refractive index of Si and SiOx arranged at a quarter period of the wavelength of the long-wave infrared light forms a highly reflective surface as the top reflector of the optical cavity.

[0091] Grating 690 is patterned with a photolithography / etching process on the top surface of the air gap in layer n-InP 656 as an intracavity optical element for optical mode control. Fabrication of grating 690 requires high resolution patterning compared to patterning the air gap. Typically, electron beam or photolithography can be applied to achieve the grating resolution requirement. An etch stop layer for the air gap and grating may be required to define the structure, although the etch stop layer is not in the Figure 6 Shown in.

[0092] Figure 7A illustrates a schematic cross-sectional view of a VCSEL device having a grating disposed on a fusion interface according to other embodiments of the present disclosure. Figure 7B shows a detailed structure of a core portion of the VCSEL device in Figure 7A. In Figures 7A and 7B, a grating is formed on the fusion interface of the GaAs portion of the structure.

[0093] In FIG. 7A , a VCSEL device 700 includes a bottom GaAs substrate 710 , a bottom distributed Bragg reflector (DBR) comprising gallium arsenide and an aluminum gallium arsenide paired layer (GaAs / AlGaAs) 720 fabricated on the bottom substrate 710 , a grating layer 790 at a fusion interface, a core layer stack 750 , and a top dielectric DBR 740 .

[0094] The stack of core layers 750 includes MQL 751 and tunnel junction (TJ) 760 , a fused interface 757 between the bottom DBR 720 and the bottom of the InP layer 756 , and a top dielectric DBR 740 .

[0095] The patterning of the grating structure 790 is done before bonding the semiconductor wafer to the InP based active optical cavity. The grating process is done in the top GaAs layer. The next AlGaAs layer on the DBR 720 can be used as an etch stop layer to define the depth of the grating etch.

[0096] The core stack 750, as shown in FIG7B , includes an MQL 751, an intermediate n-InP (n-doped InP) layer 753 below the MQL 751, and a thicker n-InP layer 756 below the n-InP layer 753 and on a fusion interface 757 in which a grating 790 is fabricated. The intermediate active n-InP layer 753 is patterned to provide space for a cathode layer 759 fabricated on the thicker n-InP layer 756. An etch stop layer (not shown in FIG7B ) may be formed on the lower n-InP layer 756 for properly patterning the core stack 750.

[0097] On the MQL 751, the stack 750 also includes an n-InP 754 layer formed on the MQL 751, a p-InAlAs layer 755, a TJ layer 760 patterned on the p-InAlAs layer 755, and in some cases there may be an etch stop layer (not shown in FIG. 7B ) on the p-InAlAs layer 755 to better define the patterning. A thicker n-InP layer 752 is deposited on the TJ 760, serving as an active InP base structure and an electrical n-InP contact re-growth layer on the p-InAlAs 755. A top dielectric DBR column 740 is deposited on top of the n-InP layer 752. A thin anode contact layer 758 is deposited on the n-InP layer 752 close to the top dielectric layer 740, and in some cases (as an option) is partially covered by the layer of the top dielectric DBR 740. This will allow the diameter of the top DBR column 740 to remain much higher than the diameter of the TJ 760.

[0098] Replacing the grating 790 in the fusion layer 757 has the advantage of presenting low thermal resistance in a structure with an intracavity grating.

[0099] Many modifications and other embodiments of the invention set forth herein will occur to those skilled in the art with the benefit of the teachings presented in the foregoing description and the associated drawings. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, these specific terms are used only in a generic and descriptive sense and are not intended to be limiting.

[0100] In utilizing various aspects of the embodiments, it will be readily understood by those skilled in the art based on the present disclosure that combinations or variations of the above embodiments may be used to manufacture optical coupling structures. Although the embodiments have been described in language specific to structural features and / or method actions, it should be understood that the appended claims are not necessarily limited to the specific features or actions described. On the contrary, the specific features and actions disclosed should be understood as embodiments of the claims for illustration. Therefore, it should be understood that the present invention is not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, these specific terms are used only in a general and descriptive sense and are not intended to be limiting.

Claims

1. A vertical cavity surface emitting laser, comprising: a first substrate; a first reflector disposed on the first substrate, wherein the first reflector comprises a distributed Bragg reflector comprising multiple layers of alternating semiconductor materials; a second reflector, wherein the second reflector comprises a distributed Bragg reflector comprising a plurality of alternating dielectric layers; as well as an active area structure, the active area structure being disposed between the first reflector and the second reflector, wherein a bottom of the active area and a top of the first reflector form a fusion interface layer via a wafer bonding process; wherein the vertical cavity surface emitting laser is configured to emit laser light having a wavelength in the range of 1200 nm to 1650 nm; and Wherein the plurality of alternating dielectric layers in the second reflector comprises alternating pairs of silicon and silicon oxide layers arranged with a period of one quarter of a wavelength.

2. The vertical cavity surface emitting laser according to claim 1, wherein the active region structure comprises: a multi-quantum well layer, wherein the multi-quantum well layer is disposed between a first group of active semiconductor layers facing a bottom side of the first reflector and a second group of active semiconductor layers facing a top side of the second reflector; The first group of active semiconductor layers includes a first semiconductor layer directly contacting the multi-quantum well layer and a second semiconductor layer away from the multi-quantum well layer; wherein a first etch stop layer is disposed between the first semiconductor layer and the second semiconductor layer to define a space for a cathode layer; and wherein the second group of active semiconductor layers on the top side of the multi-quantum well layer comprises a third semiconductor layer disposed in direct contact with the multi-quantum well layer, and a fourth semiconductor layer disposed above the third semiconductor layer away from the multi-quantum well layer; a tunnel junction layer disposed over the fourth semiconductor layer and patterned to overlap a portion of the multi-quantum well layer, wherein a second etch stop layer is disposed between the fourth semiconductor layer and the tunnel junction layer to define the tunnel junction layer; as well as a fifth semiconductor layer, the fifth semiconductor layer being above the tunnel junction layer and the second etch stop layer; The second reflector is fabricated on the fifth semiconductor layer, and the anode layer is disposed on the fifth semiconductor layer close to the second reflector.

3. The vertical cavity surface emitting laser of claim 1 and wherein the multiple layers of alternating semiconductor material in the first reflector include undoped aluminum gallium arsenide (AlGaAs) and gallium arsenide (GaAs) layers. 4 . The vertical cavity surface emitting laser according to claim 2 , wherein the first semiconductor layer and the second semiconductor layer are both n-doped indium phosphide (n-InP) layers.

5. The vertical cavity surface emitting laser according to claim 2, wherein the third semiconductor layer and the fifth semiconductor layer are both n-doped indium phosphide (n-InP) layers, and wherein the fourth semiconductor layer is a p-doped indium aluminum arsenate (p-InAlAs) layer. 6 . The vertical cavity surface emitting laser of claim 2 , wherein the tunnel junction layer comprises n++ doped InGaAlAs and p++ doped InGaAlAs.

7. The vertical cavity surface emitting laser of claim 1, wherein the first substrate is a gallium arsenide (GaAs) wafer.

8. The vertical cavity surface emitting laser according to claim 2, further comprising: a cathode pad disposed on the first reflector, wherein the cathode pad comprises a cathode dielectric distributed Bragg reflector stack, a polymer layer on the cathode dielectric distributed Bragg reflector stack, and a metal cathode electrode on the polymer layer, wherein the metal cathode electrode is electrically connected to the cathode layer; as well as An anode pad is arranged on the first reflector, wherein the anode pad includes an anode dielectric distributed Bragg reflector stack, a polymer layer on the anode dielectric distributed Bragg reflector stack, and a metal anode electrode on the polymer layer, wherein the metal anode electrode is electrically connected to the anode layer.

9. A vertical cavity surface emitting laser, comprising: a first substrate; a first reflector disposed on the first substrate, wherein the first reflector comprises a distributed Bragg reflector comprising multiple layers of alternating first and second semiconductor materials; a second reflector, wherein the second reflector comprises a distributed Bragg reflector comprising a plurality of alternating dielectric layers; an active area structure, the active area structure being disposed between the first reflector and the second reflector; as well as an air-gap spacer layer including an air-gap and an air-gap etch stop layer formed on the first reflector, wherein the air-gap spacer layer includes the first semiconductor material and the air-gap etch stop layer includes the second semiconductor material; wherein the bottom of the active area and the top of the air gap spacer layer form a fusion interface layer through a wafer bonding process; wherein the vertical cavity surface emitting laser is configured to emit laser light having a wavelength in the range of 1200 nm to 1650 nm; and Wherein the plurality of alternating dielectric layers in the second reflector comprises alternating pairs of silicon and silicon oxide layers arranged with a period of one quarter of a wavelength.

10. The vertical cavity surface emitting laser according to claim 9, wherein the active region structure comprises: a multi-quantum well layer, wherein the multi-quantum well layer is disposed between a first group of active semiconductor layers facing a bottom side of the first reflector and a second group of active semiconductor layers facing a top side of the second reflector; The first group of active semiconductor layers includes a first semiconductor layer directly contacting the multi-quantum well layer and a second semiconductor layer away from the multi-quantum well layer; wherein a first etch stop layer is disposed between the first semiconductor layer and the second semiconductor layer to define a space for a cathode layer; and wherein the second group of active semiconductor layers on the top side of the multi-quantum well layer comprises a third semiconductor layer disposed in direct contact with the multi-quantum well layer, and a fourth semiconductor layer disposed above the third semiconductor layer away from the multi-quantum well layer; a tunnel junction layer disposed over the fourth semiconductor layer and patterned to overlap a portion of the multi-quantum well layer, wherein a second etch stop layer is disposed between the fourth semiconductor layer and the tunnel junction layer to define the tunnel junction layer; as well as a fifth semiconductor layer, the fifth semiconductor layer being above the tunnel junction layer and the second etch stop layer; The second reflector is fabricated on the fifth semiconductor layer, and the anode layer is disposed on the fifth semiconductor layer close to the second reflector.

11. The vertical cavity surface emitting laser of claim 9, and wherein the first semiconductor material in the first reflector comprises undoped gallium arsenide (GaAs), and the second semiconductor material in the first reflector comprises undoped aluminum gallium arsenide (AlGaAs).

12. The VCSEL of claim 10, wherein the air gap comprises a grating structure, wherein the grating structure is aligned with the tunnel junction layer and characterized to enhance optical confinement of the VCSEL. 13 . The vertical cavity surface emitting laser according to claim 10 , wherein the first semiconductor layer and the second semiconductor layer in the active region structure are both n-doped indium phosphide (n-InP) layers.

14. The vertical cavity surface emitting laser of claim 10, wherein the third semiconductor layer and the fifth semiconductor layer are both n-doped indium phosphide (n-InP) layers, and wherein the fourth semiconductor layer is a p-doped indium aluminum arsenate (p-InAlAs) layer.

15. The vertical cavity surface emitting laser of claim 10, wherein the tunnel junction layer comprises n++ doped InGaAlAs and p++ doped InGaAlAs.

16. The vertical cavity surface emitting laser of claim 9, wherein the first substrate is a gallium arsenide (GaAs) wafer.

17. The vertical cavity surface emitting laser according to claim 9, further comprising: a cathode pad disposed on the first reflector, wherein the cathode pad comprises a cathode dielectric distributed Bragg reflector stack, a polymer layer on the cathode dielectric distributed Bragg reflector stack, and a metal cathode electrode on the polymer layer, wherein the metal cathode electrode is electrically connected to the cathode layer; as well as An anode pad is arranged on the first reflector, wherein the anode pad comprises an anode dielectric distributed Bragg reflector stack, a polymer layer on the anode dielectric distributed Bragg reflector stack, and a metal anode electrode on the polymer layer, wherein the metal anode electrode is electrically connected to the anode layer.

18. A vertical cavity surface emitting laser, comprising: a first substrate; a first reflector disposed on the first substrate, wherein the first reflector comprises a distributed Bragg reflector comprising multiple layers of alternating first and second semiconductor materials; a second reflector, wherein the second reflector comprises a distributed Bragg reflector comprising a plurality of alternating dielectric layers; as well as an active area structure, the active area structure being disposed between the first reflector and the second reflector; wherein the bottom of the active area and the top of the first reflector form a fusion interface layer via a wafer bonding process; The active region structure comprises: a multi-quantum well layer, wherein the multi-quantum well layer is disposed between a first group of active semiconductor layers facing a bottom side of the first reflector and a second group of active semiconductor layers facing a top side of the second reflector; The first group of active semiconductor layers includes a first semiconductor layer directly contacting the multi-quantum well layer and a second semiconductor layer away from the multi-quantum well layer; wherein an air gap is formed in the second semiconductor layer above the fusion interface layer; wherein a first etch stop layer is disposed between the first semiconductor layer and the second semiconductor layer to define a patterning process of the active area structure so as to provide a space for a cathode layer; and The second group of active semiconductor layers on the top side of the multi-quantum well layer includes a third semiconductor layer directly contacting the multi-quantum well layer and a fourth semiconductor layer above the third semiconductor layer away from the multi-quantum well layer; a tunnel junction layer disposed over the fourth semiconductor layer and patterned to overlap a portion of the multi-quantum well layer, wherein a second etch stop layer is disposed between the fourth semiconductor layer and the tunnel junction layer to define a patterning process of the tunnel junction layer; and a fifth semiconductor layer, the fifth semiconductor layer being above the tunnel junction layer and the second etch stop layer; wherein the second reflector is fabricated on the fifth semiconductor layer, and wherein the anode layer is disposed on the fifth semiconductor layer adjacent to the second reflector; wherein the vertical cavity surface emitting laser is configured to emit laser light having a wavelength in the range of 1200 nm to 1650 nm; and Wherein the plurality of alternating dielectric layers in the second reflector comprises alternating pairs of silicon and silicon oxide layers arranged with a period of one quarter of a wavelength.

19. The vertical cavity surface emitting laser of claim 18, and wherein the first semiconductor material in the first reflector comprises undoped gallium arsenide (GaAs), and the second semiconductor material in the first reflector comprises undoped aluminum gallium arsenide (AlGaAs).

20. The VCSEL of claim 18, wherein the air gap comprises a grating structure, wherein the grating structure is aligned with the tunnel junction layer and characterized to enhance optical confinement of the VCSEL.

21. The vertical cavity surface emitting laser of claim 18, wherein the first semiconductor layer and the second semiconductor layer in the active region structure are both n-doped indium phosphide (n-InP) layers.

22. The vertical cavity surface emitting laser of claim 18, wherein the third semiconductor layer and the fifth semiconductor layer are both n-doped indium phosphide (n-InP) layers, and wherein the fourth semiconductor layer is a p-doped indium aluminum arsenate (p-InAlAs) layer.

23. The VCSEL of claim 18, wherein the tunnel junction layer comprises n++ doped InGaAlAs and p++ doped InGaAlAs.

24. The VCSEL of claim 18, wherein the first substrate is a gallium arsenide (GaAs) wafer.

25. The vertical cavity surface emitting laser of claim 18, further comprising: a cathode pad disposed on the first reflector, wherein the cathode pad comprises a cathode dielectric distributed Bragg reflector stack, a polymer layer on the cathode dielectric distributed Bragg reflector stack, and a metal cathode electrode on the polymer layer, wherein the metal cathode electrode is electrically connected to the cathode layer; as well as An anode pad is arranged on the first reflector, wherein the anode pad includes an anode dielectric distributed Bragg reflector stack, a polymer layer on the anode dielectric distributed Bragg reflector stack, and a metal anode electrode on the polymer layer, wherein the metal anode electrode is electrically connected to the anode layer.

Images