An intelligent destruction method for storage motherboard based on Xilinx platform and RAID technology

Abstract

The present invention provides an intelligent destruction method of a storage motherboard based on a Xilinx platform and RAID technology, which includes a Xilinx processor and a RAID module, wherein the RAID module includes a plurality of embedded storage chips attached to the Xilinx platform, the Xilinx processor includes a RAID algorithm, and the plurality of embedded storage chips store data according to the RAID algorithm. The intelligent destruction method includes the following steps: a plurality of embedded storage chips receive a destruction signal; a plurality of embedded storage chips monitor the duration of the destruction signal; a plurality of embedded storage chips determine whether the duration meets a preset time; if the duration meets the preset time, it is determined to enter an erase execution state, and an erase operation is performed on the stored data based on the erase execution state; it is determined whether the erase operation is completed by a preset judgment condition; if it is determined that the erase operation is completed, a standby state is entered. The present invention effectively ensures the data security of a large-capacity storage motherboard.

Description

[Technical field]

[0001] The present invention relates to the technical field of storage devices, and in particular to an intelligent destruction method of a storage mainboard based on a Xilinx platform and RAID technology. [Background technology]

[0002] With the development of information technology, the demand for big data storage in the information age has also increased. In the storage industry, the market demands are diverse.

[0003] ZYNQ (full name: Zynq-7000 All Programmable SoC) is a new generation of fully programmable system-on-chip launched by Xilinx. ZYNQ combines a dual-core ARM Cortex-A9 processor and a traditional field programmable gate array (FPGA) logic component.

[0004] FPGA (Field Programmable Gate Array) devices are a type of semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC). They are programmable logic arrays that not only solve the shortcomings of custom circuits, but also overcome the disadvantage of the limited number of gate circuits of existing programmable devices.

[0005] RAID (Redundant Array of Independent Disks) is a technology that combines multiple independent hard disks (physical hard disks) in different ways to form a hard disk group (logical hard disk), thereby providing higher storage performance and data redundancy than a single hard disk. Currently, RAID technology has been widely used in various occasions for data storage.

[0006] RAID technology is divided into two types: hard RAID and soft RAID. In hard RAID, the system CPU and north bridge (in some cases, the north bridge may not be included) are connected to several memories through a RAID controller, and the CPU in the RAID controller calculates the parity data of each stripe stored in the storage space of the several memories; in soft RAID, there is no RAID controller, but the system CPU and north bridge (in some cases, the north bridge may not be included) are directly connected to the memory, and the memory is divided into several storage spaces, and the system CPU calculates the parity data of each stripe in the several storage spaces divided in the memory.

[0007] In the related technologies of soft RAID, the hanging storage generally adopts standard solid-state hard disk, so an external connector is required to transfer with the standard solid-state hard disk, which leads to a larger layout space, poor heat dissipation and poor shock resistance, and cannot meet the needs of large-capacity and fast data storage in the information age. And as the storage capacity increases, when the Xilinx processor is attacked, it cannot guarantee the security of its own data, increasing the risk of data leakage.

[0008] Therefore, it is necessary to provide a new intelligent destruction method of a storage motherboard based on the Xilinx platform and RAID technology to solve the above technical problems. [Summary of the invention]

[0009] The purpose of the present invention is to provide an intelligent destruction method of a storage motherboard based on a Xilinx platform and RAID technology that can provide data security, so as to solve the problems in the related art.

[0010] In order to achieve the above-mentioned purpose, the present invention provides an intelligent destruction method for a storage motherboard based on a Xilinx platform and RAID technology, wherein the storage motherboard based on the Xilinx platform and RAID technology comprises a Xilinx processor and a RAID module, wherein the RAID module comprises a plurality of embedded storage chips attached to the Xilinx platform, the Xilinx processor comprises a RAID algorithm, and the plurality of embedded storage chips store data according to the RAID algorithm, and the intelligent destruction method comprises the following steps: a first step, wherein the plurality of embedded storage chips receive a destruction signal; a second step, wherein the plurality of embedded storage chips monitor the duration of the destruction signal; a third step, wherein the plurality of embedded storage chips judge whether the duration meets a preset time; a fourth step, wherein if the duration meets the preset time, it is determined to enter an erase execution state, and an erase operation is performed on the stored data based on the erase execution state; a fifth step, wherein whether the erase operation is completed is judged by a preset judgment condition; a sixth step, wherein if it is determined that the erase operation is completed, a standby state is entered.

[0011] More preferably, in the first step, the Xilinx processor sends the destruction signal to the embedded storage chip.

[0012] More preferably, the storage motherboard based on the Xilinx platform and RAID technology also includes an intelligent destruction socket connected to the embedded storage chip. In the first step, the destruction signal is sent to the embedded storage chip by short-circuiting the intelligent destruction socket.

[0013] More preferably, in the fourth step, when the embedded storage chip is in the erase execution state, if it receives any control signal of the Xilinx processor, it enters the fault handling state from the erase execution state; any one control signal is used to instruct the embedded storage chip to enter the corresponding task execution state; the embedded storage chip generates an error signal in response to any one control signal, and returns the error signal to the Xilinx processor, the error signal being used to indicate that the embedded storage chip fails to enter the corresponding task execution state; after sending the error signal, the embedded storage chip enters the erase execution state from the fault handling state to continue the erase operation.

[0014] More preferably, in the fourth step, when the embedded storage chip is in the erase execution state, if a power cycle signal is received, the embedded storage chip enters the erase suspension state from the erase execution state, and the power cycle signal is used to instruct the embedded storage chip to perform a power cycle operation; the embedded storage chip performs a power cycle operation according to the power cycle signal; and when the power cycle operation is completed, the embedded storage chip enters the erase execution state from the erase suspension state to continue the erase operation.

[0015] More preferably, the embedded storage chip includes a control module, a flash memory module, a cache module and an interface module which are packaged therein by BGA technology, the control module includes a bus controller, a microprocessor and a DMA controller, the flash memory module includes a flash memory controller and a flash memory chip, the cache module includes a DRAM controller and a DDR3 cache, and the interface module includes a SATA interface and a UART interface.

[0016] More preferably, the Xilinx processor includes 8 signal channels, and the number of the embedded memory chips is 2 or 4 or 6 or 8.

[0017] More preferably, the embedded storage chip includes a QE pin, and when the QE pin is at a low level, intelligent destruction is triggered.

[0018] More preferably, the storage mainboard based on the Xilinx platform and RAID technology further includes a power supply module for supplying power to the embedded storage chip.

[0019] More preferably, the power supply module includes a voltage timing control circuit, which can output a first voltage to the control module, a second voltage to the flash memory module, a third voltage to the cache module, and a fourth voltage to the interface module according to a preset power-on timing.

[0020] The technical effect of the present invention is: large-capacity expansion is achieved based on the Xilinx platform, and the embedded storage chip occupies a small space and has good shock resistance, and as the storage capacity increases, the security of the data can also be guaranteed.

Brief Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0022] Figure 1 It is a structural schematic diagram of a storage mainboard based on the Xilinx platform and RAID technology of the present invention;

[0023] Figure 2 It is a schematic diagram of the steps of an intelligent destruction method of a storage motherboard based on the Xilinx platform and RAID technology of the present invention;

[0024] Figure 3 This is a flowchart of an embodiment of the intelligent destruction method of a storage motherboard based on the Xilinx platform and RAID technology of the present invention.

[0025] Figure 4 It is a schematic diagram of the structure of the embedded chip of the present invention;

[0026] Figure 5 is a schematic structural diagram of an embodiment of an embedded chip of the present invention;

[0027] Figure 6 It is a schematic diagram of the process of the storage mainboard of the present invention;

[0028] Figure 7 It is a structural schematic diagram of the intelligent destruction strip of the storage motherboard of the present invention;

[0029] Figure 8 yes Figure 4 The internal pin diagram of the embedded chip shown;

[0030] Fig. 9 yes Figure 7 The BGA package pin diagram shown;

[0031] Fig.10 It is a voltage timing control circuit diagram of the power supply module of the present invention. [Specific implementation method]

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] Please refer to Figure 1 ,to Figure 2 The present invention provides an intelligent destruction method for a storage motherboard based on a Xilinx platform and RAID technology, wherein the storage motherboard 100 based on the Xilinx platform and RAID technology includes a Xilinx processor 1 and a RAID module, the RAID module includes a plurality of embedded storage chips 2 attached to the Xilinx platform, the Xilinx processor 1 includes a RAID algorithm, and the plurality of embedded storage chips 2 store data according to the RAID algorithm, and the intelligent destruction method includes the steps of:

[0034] In the first step, a plurality of embedded storage chips 2 receive a destruction signal;

[0035] In the second step, a plurality of embedded storage chips 2 monitor the duration of the destruction signal;

[0036] In the third step, the embedded storage chips 2 determine whether the duration meets the preset time;

[0037] Step 4: If the duration meets the preset time, it is determined to enter the erase execution state, and the stored data is erased based on the erase execution state;

[0038] Step 5: judging whether the erasing operation is completed according to a preset judgment condition;

[0039] Step 6: If it is determined that the erasing operation is completed, enter the standby state.

[0040] In the first step, the Xilinx processor 1 may send a kill signal to the embedded memory chip 2 , where the kill signal is a low level signal.

[0041] In the first step, the intelligent destruction socket connected to the embedded storage chip 2 can also be set on the Xilinx platform, such as Figure 7 As shown, a destruction signal is sent to the embedded storage chip 2 by short-circuiting the intelligent destruction socket.

[0042] In the third step, in order to improve the efficiency of smart destruction, the preset time is preferably one second to determine whether to perform an erase operation, that is, the smart destruction function is triggered when the duration of the low-level signal is one second.

[0043] In the sixth step, after the erasing operation is completed, the embedded storage chip 2 changes to an initialization state, that is, enters a standby state to continue receiving data for storage.

[0044] In the fourth step, when the embedded storage chip 2 is in the erase execution state, if any control signal of the Xilinx processor 1 is received, the embedded storage chip 2 enters the fault handling state from the erase execution state; the any control signal is used to instruct the embedded storage chip 2 to enter the corresponding task execution state; the embedded storage chip 2 generates an error signal in response to the any control signal, and returns the error signal to the Xilinx processor 1, the error signal is used to indicate that the embedded storage chip 2 fails to enter the corresponding task execution state. After sending the error signal, the embedded storage chip 2 enters the erase execution state from the fault handling state to continue the erase operation.

[0045] In order to improve the security of data, the embedded memory chip 2 sets the erase execution state to the highest level. When the embedded memory chip 2 is in the erase execution state, any control signal sent by the processor will not be executed. At this time, the embedded memory chip 2 enters the fault handling state, generates an error signal in this fault handling state and returns it to the processor, and continues to perform the erase operation after returning the error signal to ensure that the stored data is completely erased.

[0046] In the fourth step, when the embedded memory chip 2 is in the erase execution state, if a power cycle signal is received, the erase execution state enters the erase suspension state, and the power cycle signal is used to instruct the embedded memory chip 2 to perform a power cycle operation. The embedded memory chip 2 performs a power cycle operation according to the power cycle signal. When the power cycle operation is completed, the embedded memory chip 2 enters the erase execution state from the erase suspension state to continue the erase operation.

[0047] In order to ensure the smooth execution of the erase operation, a power cycle function is configured in the embedded memory chip 2. When the power consumption of the embedded memory chip 2 is insufficient, the embedded memory chip 2 is powered in time. When the embedded memory chip 2 starts the power cycle function, it receives a power cycle signal or a power cycle instruction. At this time, the erase execution state is suspended and the erase pause state is entered. After the power cycle operation is completed, the erase execution state is re-entered from the erase pause state to continue the erase operation.

[0048] The Xilinx processor 1 includes a DMA controller (Direct Memory Access controller). The DMA controller has 8 signal channels. Each signal channel includes a first differential signal pin group, and the embedded memory chip 2 includes a second differential signal pin group corresponding thereto, and the first differential signal pin group is electrically connected to the second differential signal pin group to establish a signal channel.

[0049] In this embodiment, the number of embedded memory chips 2 is eight, but in other embodiments, the number of embedded memory chips 2 may also be two, four, or six.

[0050] The embedded storage chip 2 also includes a QE pin, namely a Quick erase pin, which can trigger intelligent destruction when the QE pin is at a low level.

[0051] In this embodiment, the level of the RAID algorithm is RAID1, that is, when writing data to one embedded storage chip, a mirror file will be generated on another embedded storage chip. As long as at least one embedded storage chip in any pair of mirror disks is available, the system can operate normally even when half of the embedded storage chips have problems. Through such a design, the reliability and repairability of the system can be guaranteed to the maximum extent without affecting performance.

[0052] However, in other embodiments, the RAID algorithm may also adopt other levels, such as RAID2, RAID3, RAID4, etc.

[0053] The intelligent destruction method of the present invention can enable a plurality of embedded storage chips 2 to realize the intelligent destruction function at the same time, and can effectively protect data security.

[0054] like Figure 3 As shown in FIG. 1 , in this embodiment, the embedded storage chip 2 implements a flow chart of the intelligent destruction function. The specific description is as follows.

[0055] The embedded storage chip 2 is in the QE0 state before the intelligent destruction function is started. QE0: Device_IDLE: When the embedded storage chip 2 is successfully powered on or successfully executes any command, the embedded storage chip 2 enters this state after completing the initialization process. Exemplarily, the QE1 state is also called the standby state.

[0056] Transition QE0:QE1 process: When the embedded memory chip 2 detects that QEE is set for at least 1 second, the device should transition to QE1:Quick_Erase_Execute. QEE is used to monitor the duration of the low level.

[0057] QE1: Quick_Erase_Execute state: QE1 is the erase execution state, which is entered when QEE- is asserted within the last second. In the erase execution state, the embedded storage chip starts searching for the stored data in all data blocks and then erases the stored data. When entering the erase execution state, QEB- is asserted by the device, and QEB is used to determine whether the erase operation is completed.

[0058] Transition QE1: QE1 process: is in the abort state. When there is a power cycle in the state, the embedded memory chip 2 should continue the erase process after completing the initialization process.

[0059] Transition QE1:QE2 process: When all data blocks are successfully erased, the embedded memory chip 2 should transition to QE2:Quick_Erase_Finish.

[0060] Transition QE1: QE3 process: When the Xilinx processor or other processor issues any command in the erase execution state, the command can be understood as a control signal, and the embedded memory chip 2 should be converted to QE3: Command_Error, a fault handling state.

[0061] QE2: Quick_Erase_Finish state: This is the end of the erase state. This state is entered after all data blocks are successfully erased. When entering this state, QEB will be cancelled by the embedded storage chip.

[0062] Transition QE2:QE0 process: After completing erasing all data blocks, the embedded memory chip 2 should transition to QE0:Device_IDLE state.

[0063] QE3: Command_Error state: When the Xilinx processor 1 issues any command through the connected control pin or the CF / PATA hard disk device issues a HRST / SRST command through the parallel port or the SATA hard disk device issues a SRST / COMREST command through the serial port, if the embedded storage chip 2 is in the erase execution state of erasing all data blocks, it enters this pause state, and the embedded storage chip 2 regards the erase process as the highest priority and uses ABRT to return the ERR state (fault state) to the Xilinx processor, where ABRT is the abort signal.

[0064] Transition QE3:QE1:When returning to the ERR state, the embedded memory chip shall continue the erase process and transition to QE1:Quick_Erase_Execute.

[0065] Embedded storage chip 2 needs to pay attention to the following when the intelligent destruction function is activated:

[0066] (1) Before the embedded storage chip 2 executes the intelligent destruction function, the program of the erase function is imported into the embedded storage chip through the MPtool tool, and the embedded storage chip 2 is set to never enter the sleep mode when the erase function is implemented. The MPtool tool can perform operations such as formatting and mass production on storage devices.

[0067] (2) The erase function of the embedded storage chip 2 has the highest priority. Therefore, in this state, the embedded storage chip 2 will not stop executing the erase function when receiving any command from any processor, including commands directly transmitted by the Xilinx processor 1, HRST / SRST commands transmitted through the parallel port of the CF / PATA hard disk device, and SRST / COMREST commands transmitted through the serial port of the SATA hard disk device. The serial port and the parallel port are input and output modules.

[0068] (3) If the pin QEE- is controlled by the GPIO (General-purpose input / output) pin of the Xilinx processor 1, the erase function is executed when the embedded memory chip 2 enters the idle state and activates the QEE pin for at least 1 second. The idle state can be understood as a standby state.

[0069] (4) If the pin QEE- is controlled manually, for example, if the pin is accidentally pressed, the erase function is executed when the QEE- pin is activated for at least 3 seconds.

[0070] (5) The busy time to erase all data blocks depends on the flash configuration:

[0071] Busy time = (erase time * block number) + (program time * block number) + (clean pair time * current pair number). Wherein, erase time is the erase time of a single data block tested in advance; block number is the number of the data block that needs to be erased currently; program time is the time to start the erase function program when erasing each data block; clean pair time is the time to erase each data pair; current pair number is the number of data pairs currently stored in the embedded storage chip. A data pair includes multiple data blocks. When storing data, some data requires multiple data blocks to store to form a data pair.

[0072] In this embodiment, the busy time of the erase function can be controlled to at least five seconds to improve the erase efficiency.

[0073] (6) Status description:

[0074] When the intelligent destruction is completed, the LBA (Logical Block Address) logical block address of the embedded storage chip 2 is all 0. You can use the WinHex tool to check whether the embedded storage chip is completely destroyed to ensure that the embedded storage chip 2 cannot be restored after destruction and returns to the unused (pre-factory) state. The WinHex tool is used to check and repair various files, recover deleted files, and data lost due to hard disk damage.

[0075] (7) Before implementing the smart destruction function, the GPIO interface pin of the Xilinx platform is soldered to the QE pin of the embedded storage chip. The Xilinx processor provides a destruction signal to the embedded chip through the GPIO interface pin. The QE pin is set to be effective at a low level to trigger the smart destruction function. All previous stored data will be erased even during a power cycle, and the device can continue to be used to store data and reformatted by the host after the function is completed.

[0076] like Figure 4 As shown, the embedded memory chip 2 includes a control module 21, a flash memory module 22, a cache module 23, and an interface module 24. The control module 21, the flash memory module 22, the cache module 23, and the interface module 24 are packaged inside the embedded memory chip 2 by BGA technology.

[0077] BGA (Ball Grid Array) packaging technology is a ball grid array packaging technology, which is a high-density surface mount packaging technology. Embedded memory chips using BGA packaging technology have smaller size, faster and more effective heat dissipation and electrical performance at the same capacity.

[0078] like Figure 5 As shown, in this embodiment, the control module includes a bus controller, a microprocessor and a DMA controller, the flash memory module includes a flash memory controller and a flash memory chip array, and the cache module includes a DRAM controller and a DDR3 cache. The interface module includes a SATA interface and a UART interface. The embedded storage chip also includes a security encoder / decoder, a main system buffer and a JTAG.

[0079] The microprocessor is connected to the bus controller and JTAG. The bus controller is respectively connected to the security encoder / decoder, UART interface, main system buffer, DMA controller, DRAM controller and flash controller. The flash controller is connected to the flash chip array, the DRAM controller is connected to the DDR3 cache, and the security encoder / decoder is connected to the SATA interface.

[0080] JTAG stands for Joint Test Action Group, which is used for internal chip testing. UART stands for Universal Asynchronous Receiver / Transmitter, which is a serial communication interface. SATA stands for Serial Advanced Technology Attachment, which is a serial hardware driver interface based on industry standards.

[0081] like Figure 6 As shown, a storage motherboard 100 based on the Xilinx platform and RAID technology of the present invention further includes a power supply module 3 for supplying power to the embedded storage chip 2 .

[0082] The differential signal pins of the Xilinx processor 1 are connected to the differential signal pins of the embedded memory chip 2 to form a signal channel, so that data can be transmitted between the Xilinx processor 1 and the embedded memory chip 2 .

[0083] The embedded storage chip 2 further includes a plurality of power pins, which are respectively connected to the control module 21 , the flash memory module 22 , the cache module 23 and the interface module 24 .

[0084] The power supply module 3 outputs a first voltage, a second voltage, a third voltage, and a fourth voltage to the control module 21 , the flash memory module 22 , the cache module 23 , and the interface module 24 , respectively.

[0085] like Figures 8 to 10 As shown, in this embodiment, preferably the first voltage is 1.1V, the second voltage is 1.8V, the third voltage is 1.5V, and the fourth voltage is 3.3V.

[0086] The power supply module 3 also includes a voltage timing control circuit, which includes a plurality of capacitors for delay. The voltage timing control circuit can provide the first voltage, the second voltage, the third voltage, and the fourth voltage to the embedded storage chip 2 according to the preset power-on timing. If the timing is correct, the disk can be recognized, and if it is incorrect, the disk cannot be recognized.

[0087] The preset power-on sequence is 1.1V>1.5V>1.8V>3.3V, that is, the power-on sequence is preset to be 1.1V voltage powered on earlier than 1.5V voltage, 1.5V voltage powered on earlier than 1.8V voltage, and 1.8V voltage powered on earlier than 3.3V voltage. If the preset power-on sequence is not met, the disk will not be recognized, that is, the Xilinx processor 1 will not recognize the embedded storage chip 2. Through such a design, the stability of the connection between the Xilinx processor 1 and the embedded storage chip 2 is guaranteed, so that the Xilinx processor 1 can read the data of the embedded storage chip 2 normally. The setting of the voltage timing control circuit can ensure that the external power supply circuit can supply power to each module of the embedded storage chip according to the preset power-on sequence, uniformly and effectively manage the power-on of each module of the embedded storage chip, effectively reduce the impact on the power supply network when each module is powered on at the same time, and ensure the stability and safety of power use.

[0088] In this embodiment, the model of the Xilinx processor 1 used is XC7Z045-2FFFG900I, but not limited thereto. The model of the embedded memory chip 2 used is AS619GEE, which is a BGA packaged embedded memory chip independently developed by the applicant that integrates NAND flash memory, DRAM cache, and independently developed controller, but not limited thereto.

[0089] During installation, the embedded memory chip 2 is mounted on the Xilinx platform via a board. Since the size of the embedded memory chip 2 is 16X20mm, the layout space is greatly reduced, and the heat dissipation performance is good. Moreover, since the embedded memory chip 2 is packaged in the form of BGA and mounted on the Xilinx platform, the shock resistance is good.

[0090] In summary, the present invention has the following beneficial effects: large-capacity expansion is achieved based on the Xilinx platform, and the embedded storage chip occupies a small space and has good shock resistance, and as the storage capacity increases, the security of the data can be guaranteed when the Xilinx processor is attacked.

[0091] Finally, it should be noted that the above embodiments are only intended to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An intelligent destruction method for a storage motherboard based on the Xilinx platform and RAID technology, characterized in that: The storage motherboard based on the Xilinx platform and RAID technology includes a Xilinx processor and a RAID module, the RAID module includes a plurality of embedded storage chips attached to the Xilinx platform, the Xilinx processor includes a RAID algorithm, and the plurality of embedded storage chips store data according to the RAID algorithm, wherein the level of the RAID algorithm is RAID1, that is, while the data is written into one of the embedded storage chips, a mirror file is generated on another of the embedded storage chips, and the intelligent destruction method includes the following steps: a first step, the plurality of embedded storage chips receive a destruction signal, wherein the Xilinx processor sends the destruction signal to the embedded storage chip; In the second step, the plurality of embedded storage chips monitor the duration of the destruction signal; In the third step, the plurality of embedded storage chips determine whether the duration meets a preset time; Step 4: if the duration meets the preset time, determine to enter the erase execution state, and perform an erase operation on the stored data based on the erase execution state; Step 5: judging whether the erasing operation is completed according to a preset judgment condition; Step 6: If it is determined that the erasing operation is completed, enter the standby state.

2. According to claim 1, a method for intelligent destruction of a storage motherboard based on the Xilinx platform and RAID technology, characterized in that: The storage motherboard based on the Xilinx platform and RAID technology also includes an intelligent destruction socket connected to the embedded storage chip. In the first step, the destruction signal is sent to the embedded storage chip by short-circuiting the intelligent destruction socket.

3. According to claim 1, a method for intelligent destruction of a storage motherboard based on the Xilinx platform and RAID technology, characterized in that: In the fourth step, when the embedded storage chip is in the erase execution state, if any control signal of the Xilinx processor is received, the embedded storage chip enters the fault handling state from the erase execution state; any control signal is used to instruct the embedded storage chip to enter the corresponding task execution state; The embedded storage chip generates an error signal in response to any one of the control signals, and returns the error signal to the Xilinx processor, wherein the error signal is used to indicate that the embedded storage chip fails to enter the corresponding task execution state; after sending the error signal, the embedded storage chip enters the erase execution state from the fault handling state to continue the erase operation.

4. According to claim 1, a method for intelligent destruction of a storage motherboard based on the Xilinx platform and RAID technology, characterized in that: In the fourth step, when the embedded storage chip is in the erase execution state, if a power cycle signal is received, the embedded storage chip enters the erase suspension state from the erase execution state, and the power cycle signal is used to instruct the embedded storage chip to perform a power cycle operation; The embedded storage chip performs a power cycle operation according to the power cycle signal; And when the power cycle operation is completed, the embedded storage chip enters the erase execution state from the erase suspension state to continue the erase operation.

5. According to claim 1 or 4, a method for intelligent destruction of a storage motherboard based on the Xilinx platform and RAID technology, characterized in that: The embedded storage chip includes a control module, a flash memory module, a cache module and an interface module which are packaged therein by BGA technology. The control module includes a bus controller, a microprocessor and a DMA controller. The flash memory module includes a flash memory controller and a flash memory chip. The cache module includes a DRAM controller and a DDR3 cache. The interface module includes a SATA interface and a UART interface.

6. The intelligent destruction method of a storage motherboard based on the Xilinx platform and RAID technology according to claim 5 is characterized in that: The Xilinx processor includes 8 signal channels, and the number of the embedded memory chips is 2, 4, 6 or 8.

7. The intelligent destruction method of a storage motherboard based on the Xilinx platform and RAID technology according to claim 6 is characterized in that: The embedded storage chip includes a QE pin, and when the QE pin is at a low level, intelligent destruction is triggered.

8. The intelligent destruction method of a storage motherboard based on the Xilinx platform and RAID technology according to claim 7 is characterized in that: The storage mainboard based on the Xilinx platform and RAID technology also includes a power supply module for supplying power to the embedded storage chip.

9. The intelligent destruction method of a storage motherboard based on the Xilinx platform and RAID technology according to claim 8, characterized in that: The power supply module includes a voltage timing control circuit, which can output a first voltage to the control module, a second voltage to the flash memory module, a third voltage to the cache module, and a fourth voltage to the interface module according to a preset power-on timing.

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