A synchronization method, device and medium of arbitrary waveform generator

Abstract

The present application discloses a synchronization method, device and medium for an arbitrary waveform generator, the method comprising: the arbitrary waveform generator receives a cycle ratio setting instruction sent from a measurement and control terminal, the cycle ratio being the ratio of an external trigger signal cycle to an FPGA clock cycle; the cycle ratio is set according to the cycle ratio setting instruction, and an external trigger signal sent from a system trigger signal module is obtained; a rising edge of a signal sampled to the external trigger signal is determined, and the FPGA clock cycle is counted with the rising edge of the signal as a starting time node; when the count value of the FPGA clock cycle is determined to reach the cycle ratio, an internal trigger signal is generated inside the FPGA of the arbitrary waveform generator, and the FPGA clock cycle is recounted; and loaded waveform data sent from the measurement and control terminal is received, and a waveform is sent under the triggering of the internal trigger signal.

Description

Technical Field

[0001] The present application relates to the field of instrument technology, and in particular to a synchronization method, device and medium for an arbitrary waveform generator. Background Art

[0002] Waveform generators are widely used in the fields of electronic circuits, automatic control and scientific experiments. They are electrical signal devices that meet strict technical requirements for electronic measurement work. Like oscilloscopes, voltmeters, frequency meters and other instruments, they are one of the most common, basic and widely used electronic instruments. Waveform generators are used in almost all electrical parameter measurements. With the continuous development of communications and radars, more and more requirements are put forward for the frequency stability, spectrum purity, frequency range and number of output frequencies of signal sources and the shape of signal waveforms. Not only are standard waveforms such as sine waves and square waves required to be generated, but also arbitrary waveforms can be generated as needed, and the operation is convenient, the output waveform quality is good, the output frequency range is wide, the output frequency stability, accuracy and resolution are high, the frequency conversion speed is fast and the output waveform phase is continuous during frequency conversion. It can be seen that it is very necessary and of great significance to study and produce high-performance arbitrary waveform generators.

[0003] In some cutting-edge scientific research fields, multiple arbitrary waveform generators are required to work together. When the number of arbitrary waveform generators increases, the waveforms sent by multiple arbitrary waveform generators will have phase jitter, which is not allowed in applications with high requirements for synchronization. Therefore, a synchronization method for arbitrary waveform generators is urgently needed. Summary of the invention

[0004] In order to solve the above problems, the present application proposes a synchronization method, device and medium for an arbitrary waveform generator, wherein the method is applied to a synchronization system of an arbitrary waveform generator, the system comprising a measurement and control terminal, a clock source, a delay generator and a PXIe chassis, the PXIe chassis being provided with a system trigger signal module and a plurality of arbitrary waveform generators, the method comprising:

[0005] The arbitrary waveform generator receives a cycle ratio setting instruction sent from the measurement and control terminal, where the cycle ratio is the ratio of the external trigger signal cycle to the FPGA clock cycle; sets the cycle ratio according to the cycle ratio setting instruction, and obtains the external trigger signal sent from the system trigger signal module; determines the rising edge of the signal sampled from the external trigger signal, and uses the rising edge of the signal as the starting time node to count the FPGA clock cycle; determines that the count value of the FPGA clock cycle reaches the cycle ratio, generates an internal trigger signal inside the FPGA of the arbitrary waveform generator, and recounts the FPGA clock cycle; receives the loaded waveform data sent from the measurement and control terminal, and sends the waveform under the triggering of the internal trigger signal.

[0006] In one example, the external trigger signal periods corresponding to the plurality of arbitrary waveform generators are the same as the FPGA clock period.

[0007] In one example, before obtaining the external trigger signal sent by the system trigger signal module, the method also includes: the PXIe chassis obtains the external trigger signal sent by the delay generator through the trigger signal input port on the front panel, and transmits the external trigger signal to the system trigger signal module through the chassis backplane.

[0008] In one example, the system trigger signal module is located in the system timing slot of the PXIe chassis, and distributes the external trigger signal to the plurality of arbitrary waveform generators via a star trigger bus.

[0009] In one example, after sending the waveform under the trigger of the internal trigger signal, the method also includes: determining that there is a phase difference among the several arbitrary waveform generators, and the phase difference is caused by the difference in the internal trigger signal; and padding the waveform data with zeros through upper-level software until the phase difference is eliminated.

[0010] In one example, after acquiring the external trigger signal sent from the system trigger signal module, the method further includes: stopping acquiring the external trigger signal until receiving a new cycle ratio setting instruction sent from the measurement and control terminal.

[0011] In one example, after acquiring the external trigger signal sent from the system trigger signal module, the method further includes: determining whether the external trigger signal includes the signal rising edge, and if not, continuously acquiring the external trigger signal.

[0012] In one example, the clock source provides a reference clock for the delay generator and the PXIe chassis.

[0013] The present application also provides a synchronization device for an arbitrary waveform generator, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute: the arbitrary waveform generator receives a cycle ratio setting instruction sent from a measurement and control terminal, wherein the cycle ratio is the ratio of an external trigger signal cycle to an FPGA clock cycle; sets the cycle ratio according to the cycle ratio setting instruction, and obtains an external trigger signal sent from a system trigger signal module; determines a rising edge of a signal sampled from the external trigger signal, and uses the rising edge of the signal as a starting time node to count the FPGA clock cycle; determines that the count value of the FPGA clock cycle reaches the cycle ratio, generates an internal trigger signal inside the FPGA of the arbitrary waveform generator, and recounts the FPGA clock cycle; receives loaded waveform data sent from the measurement and control terminal, and sends a waveform under the triggering of the internal trigger signal.

[0014] The present application also provides a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured as follows: an arbitrary waveform generator receives a cycle ratio setting instruction sent from a measurement and control terminal, wherein the cycle ratio is a ratio of an external trigger signal cycle to an FPGA clock cycle; the cycle ratio is set according to the cycle ratio setting instruction, and an external trigger signal sent from a system trigger signal module is obtained; a rising edge of a signal sampled from the external trigger signal is determined, and the FPGA clock cycle is counted using the rising edge of the signal as a starting time node; when a count value of the FPGA clock cycle is determined to reach the cycle ratio, an internal trigger signal is generated inside the FPGA of the arbitrary waveform generator, and the FPGA clock cycle is recounted; loaded waveform data sent from the measurement and control terminal is received, and a waveform is sent under the triggering of the internal trigger signal.

[0015] The method proposed in this application can unify the time for multiple arbitrary waveform generators to send waveforms by setting an internal trigger signal, thereby preventing the occurrence of phase jitter. In addition, this method is simple to implement. Even if there is a phase difference, the phase difference can be eliminated by zero-filling operation through the upper-level software, thereby improving the accuracy of the research data. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 This is a schematic flow chart of a synchronization method for an arbitrary waveform generator in an embodiment of the present application;

[0018] Figure 2 This is a flow chart of another synchronization method of an arbitrary waveform generator in an embodiment of the present application;

[0019] Figure 3 This is a schematic diagram of the structure of a synchronization device of an arbitrary waveform generator in an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0021] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0022] It should be noted that in the prior art, when multiple arbitrary waveform generators need to work together, the synchronization methods are mainly the following two: because multiple arbitrary waveform generators are connected to the measurement and control terminal with multiple wires of the same length in the chassis, and the waveform instructions, i.e., trigger signals, are transmitted to multiple arbitrary waveform generators at the same time through the measurement and control terminal, but this method will cause phase jitter. Or when the waveform period is short but the amount of waveform data is extremely large, when the arbitrary waveform generator samples the trigger signal and identifies the rising edge to determine the trigger time, it is very likely that the error in trigger signal recognition is caused by the device error of a certain arbitrary waveform generator itself during a certain identification process, resulting in phase jitter in multiple arbitrary waveform generators. Therefore, the present application provides another waveform trigger instruction, i.e., an internal trigger instruction, to enable each arbitrary waveform generator to send a waveform at the same time.

[0023] Figure 1 A flowchart of a synchronization method for an arbitrary waveform generator provided for one or more embodiments of this specification. The implementation of the analysis method involved in the embodiments of the present application can be a terminal device or a server, and the present application does not impose any special restrictions on this. For the convenience of understanding and description, the following embodiments are described in detail using the server as an example. It should be noted that the server can be a single device or a system composed of multiple devices, that is, a distributed server, and the present application does not impose any specific restrictions on this.

[0024] like Figure 1 As shown, an embodiment of the present application provides a synchronization method of an arbitrary waveform generator, which is applied to a synchronization system of an arbitrary waveform generator, characterized in that the system includes a measurement and control terminal, a clock source, a delay generator and a PXIe chassis, and a system trigger signal module and a plurality of arbitrary waveform generators are provided in the PXIe chassis, and the method includes:

[0025] S101: The arbitrary waveform generator receives a period ratio setting instruction sent from the measurement and control terminal, where the period ratio is the ratio of the external trigger signal period to the FPGA clock period.

[0026] The present application first sends a cycle ratio setting instruction to multiple arbitrary waveform generators through a measurement and control terminal. It should be noted that the cycle ratio setting instruction here is the ratio of the external trigger signal cycle to the FPGA clock cycle.

[0027] S102: setting the cycle ratio according to the cycle ratio setting instruction, and acquiring an external trigger signal sent by the system trigger signal module.

[0028] After receiving the cycle ratio setting instruction, multiple arbitrary waveform generators will design themselves according to the cycle ratio in the instruction. After being triggered by the cycle ratio, they will obtain the external trigger signal sent by the system trigger signal module and sample the external trigger signal. The sampling here means that the arbitrary waveform generator FPGA uses the rising edge of the clock with a short period of time to sample the rising edge of the external trigger signal. The "short period of time" here is the FPGA clock period.

[0029] S103: Determine the rising edge of the signal sampled from the external trigger signal, and use the rising edge of the signal as a starting time node to count the FPGA clock cycle.

[0030] When the rising edge of the external trigger signal is sampled, the time node corresponding to the rising edge is used as the starting time node, and the FPGA clock cycle is counted, that is, how many FPGA clock cycles have passed after the starting time node.

[0031] S104: Determine that the count value of the FPGA clock cycle reaches the cycle ratio, generate an internal trigger signal inside the FPGA of the arbitrary waveform generator, and recount the FPGA clock cycle.

[0032] When it is found that the FPGA clock cycles of the period ratio number have passed, the FPGA inside the arbitrary waveform generator generates an internal trigger signal and re-counts the FPGA clock cycles.

[0033] S105: receiving the loading waveform data sent from the measurement and control terminal, and sending the waveform under the triggering of the internal trigger signal.

[0034] The arbitrary waveform generator receives the loaded waveform data sent from the measurement and control terminal, starts the waveform transmission, and then transmits the waveform under the triggering of the internal trigger signal, thereby realizing the waveform synchronization between different arbitrary waveform generators.

[0035] The present application establishes a timing constraint relationship between the external trigger signal period and the FPGA clock period by setting the period ratio, that is, a constraint relationship is established between the sampling signal of the arbitrary waveform generator during sampling and the external trigger signal established externally, thereby preventing phase jitter caused by jitter of the external trigger signal.

[0036] In one embodiment, the external trigger signal period and FPGA clock period corresponding to several arbitrary waveform generators in the synchronization system of arbitrary waveform generators are the same, that is, the period ratios corresponding to the arbitrary waveform generators set in the PXIe chassis are also the same. By setting the same external trigger signal period and FPGA clock period, since the time taken for the count value of the FPGA clock period to reach the ratio is equal to the external trigger signal period, each arbitrary waveform generator can be set while keeping the external trigger signal enabled to obtain several timing starting points that are approximately different by an integer number of external trigger signal periods.

[0037] In one embodiment, before the arbitrary waveform generator obtains the external trigger signal sent by the system trigger signal module, the delay generator inputs the external trigger signal to the trigger signal input port on the front panel of the PXIe chassis, and transmits the external trigger signal to the system trigger signal module through the chassis backplane.

[0038] In one embodiment, the system trigger signal module is located in the system timing slot of the PXIe chassis, and distributes the external trigger signal to the plurality of arbitrary waveform generators via a star trigger bus, namely, PXI_STAR.

[0039] In one embodiment, since the method provided by the present application can greatly reduce the occurrence of phase jitter, but phase differences may still occur, after multiple arbitrary waveform generators send waveforms, if there are still phase differences, the waveform data can be padded with zeros through the upper-layer software until the phase difference is eliminated. Taking AWG1 and AWG2 as two arbitrary waveform generators, if AWG2 generates an internal trigger signal 4ns later than AWG1, 4ns of zeros can be padded before the waveform data of AWG1 for filling, or the waveform data of AWG1 can be shifted back by 4ns as a whole to correspond to the waveform data of AWG2.

[0040] In one embodiment, after the arbitrary waveform generator samples the rising edge of the external trigger signal, it stops sampling the external trigger signal. However, if it is determined that there is no rising edge in the acquired external trigger signal, it is necessary to continue acquiring the external trigger signal and sample the rising edge of the external trigger signal using the rising edge of the clock cycle through the arbitrary waveform generator FPGA.

[0041] In one embodiment, the clock source is used to provide a reference clock for the delay generator and the PXIe chassis. By setting a unified reference clock, since the internal trigger signal of the arbitrary waveform generator only depends on whether the timing start point and the FPGA clock cycle count reach the set ratio, the timing start point is obtained through one sampling, and the clocks of different arbitrary waveform generators are synchronized, so the internal trigger signals of different arbitrary waveform generators are synchronized, and the differences in the internal trigger signals of different arbitrary waveform generators caused by the differences in the timing start points will not accumulate.

[0042] Figure 2 This is a synchronization method for an arbitrary waveform generator in an embodiment of the present application. When implementing it, you can refer to the following specific embodiments:

[0043] The system consists of a measurement and control terminal, a clock source, a delay generator, and a PXIe chassis. The clock source provides a 10MHz reference clock for the delay generator and the PXIe chassis. The system trigger signal module and the arbitrary waveform generator are synchronized to the clock used by the PXIe chassis. The delay generator trigger signal is a square wave with a period of 200us, which is input to the trigger signal input port on the front panel of the PXIe chassis. The system trigger signal module distributes the external trigger signal to each arbitrary waveform generator through PXI_STAR. The arbitrary waveform generator FPGA uses the rising edge of the clock with a clock period of 4ns to sample the rising edge of the external trigger signal. Assume that there are two arbitrary waveform generators, AWG1 and AWG2.

[0044] The measurement and control terminal sends an instruction to set the ratio of the external trigger signal period to the FPGA clock period to AWG1 and AWG2. The ratio is 200000 / 4=50000, and the setting order is to set AWG1 first and then AWG2. AWG1 receives and executes the instruction to set the period ratio. After the instruction is executed, it samples the external trigger signal. AWG1 samples the rising edge of the external trigger signal and starts counting the FPGA clock period, with its timing starting point as 0. AWG2 receives and executes the instruction to set the period ratio. After the instruction is executed, it samples the external trigger signal. AWG2 samples the rising edge of the external trigger signal and starts counting the FPGA clock cycles. Assume that the time it takes for AWG2 to sample the rising edge of the external trigger signal is 50000*m±4*n (where m=1,2,...,n=0,1,...,N, and N is generally not more than 2, considering software usage and execution time). This means that after AWG1 samples the external trigger signal and starts timing, after m external trigger signal cycles plus or minus n FPGA clock cycles, AWG2 samples the external trigger signal and starts timing. m is determined by the time interval between the two arbitrary waveform generators set by the measurement and control terminal, and n is caused by the difference in the time when the external trigger signal reaches the two arbitrary waveform generators and the judgment of the edge of the external trigger signal when the two arbitrary waveform generators sample the external trigger signal.

[0045] Since AWG1 is counting, AWG1 has counted the FPGA clock cycle m times to reach the ratio of the external trigger signal cycle to the FPGA clock cycle. Therefore, when AWG1 and AWG2 both start to send waveforms, the phase difference of the waveforms is mainly related to the difference in the time when the external trigger signal reaches the two arbitrary waveform generators and the n FPGA clock cycles caused by the judgment of the edge of the external trigger signal when the two arbitrary waveform generators sample the external trigger signal. The difference in the internal trigger signals of AWG1 and AWG2 caused by the difference in the timing starting point of AWG1 and AWG2 will not accumulate. The phase difference of the waveforms of AWG1 and AWG2 caused by the difference in the internal trigger signals of AWG1 and AWG2 can be eliminated by the upper-level software by filling the waveform data of the arbitrary waveform generator with 0. Whenever the count value of the FPGA clock cycle reaches 50,000, AWG1 and AWG2 each generate an internal trigger signal and re-count the FPGA clock cycle; the measurement and control terminal loads waveform data for AWG1 and AWG2 and starts waveform transmission; AWG1 and AWG2 send waveforms under the trigger of their respective internal trigger signals.

[0046] like Figure 3 As shown, the embodiment of the present application also provides a synchronization device for an arbitrary waveform generator, including:

[0047] at least one processor; and,

[0048] a memory communicatively connected to the at least one processor; wherein,

[0049] The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to:

[0050] The arbitrary waveform generator receives a cycle ratio setting instruction sent from a measurement and control terminal, wherein the cycle ratio is the ratio of an external trigger signal cycle to an FPGA clock cycle; sets the cycle ratio according to the cycle ratio setting instruction, and obtains an external trigger signal sent from a system trigger signal module; determines a rising edge of a signal sampled from the external trigger signal, and uses the rising edge of the signal as a starting time node to count the FPGA clock cycle; determines that the count value of the FPGA clock cycle reaches the cycle ratio, generates an internal trigger signal inside the FPGA of the arbitrary waveform generator, and recounts the FPGA clock cycle; receives loaded waveform data sent from the measurement and control terminal, and sends a waveform under the triggering of the internal trigger signal.

[0051] The embodiment of the present application further provides a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured as follows:

[0052] The arbitrary waveform generator receives a cycle ratio setting instruction sent from a measurement and control terminal, wherein the cycle ratio is the ratio of an external trigger signal cycle to an FPGA clock cycle; sets the cycle ratio according to the cycle ratio setting instruction, and obtains an external trigger signal sent from a system trigger signal module; determines a rising edge of a signal sampled from the external trigger signal, and uses the rising edge of the signal as a starting time node to count the FPGA clock cycle; determines that the count value of the FPGA clock cycle reaches the cycle ratio, generates an internal trigger signal inside the FPGA of the arbitrary waveform generator, and recounts the FPGA clock cycle; receives loaded waveform data sent from the measurement and control terminal, and sends a waveform under the triggering of the internal trigger signal.

[0053] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0054] The devices and media provided in the embodiments of the present application correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0055] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0056] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0057] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0058] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0059] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0060] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0061] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0062] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0063] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A synchronization method for an arbitrary waveform generator, applied to a synchronization system of an arbitrary waveform generator, characterized in that: The system includes a measurement and control terminal, a clock source, a delay generator and a PXIe chassis, wherein a system trigger signal module and a plurality of arbitrary waveform generators are arranged in the PXIe chassis, and the method includes: The arbitrary waveform generator receives a period ratio setting instruction sent from the measurement and control terminal, wherein the period ratio is a ratio of an external trigger signal period to an FPGA clock period; Setting the cycle ratio according to the cycle ratio setting instruction, and acquiring an external trigger signal sent by the system trigger signal module; Determine the rising edge of the signal sampled from the external trigger signal, and use the rising edge of the signal as the starting time node to count the FPGA clock cycle; Determining that the count value of the FPGA clock cycle reaches the cycle ratio, the FPGA of the arbitrary waveform generator generates an internal trigger signal inside, and recounts the FPGA clock cycle; Receive the loading waveform data sent from the measurement and control terminal, and send the waveform under the triggering of the internal trigger signal.

2. The method according to claim 1, characterized in that: The external trigger signal periods corresponding to the plurality of arbitrary waveform generators are the same as the FPGA clock period.

3. The method according to claim 1, characterized in that Before acquiring the external trigger signal sent by the system trigger signal module, the method further includes: The PXIe chassis obtains the external trigger signal from the delay generator through a trigger signal input port on the front panel, and transmits the external trigger signal to the system trigger signal module through a chassis backplane.

4. The method according to claim 1, characterized in that The system trigger signal module is located in the system timing slot of the PXIe chassis and distributes the external trigger signal to the plurality of arbitrary waveform generators via a star trigger bus.

5. The method according to claim 1, characterized in that: After sending the waveform under the triggering of the internal trigger signal, the method further includes: Determining that a phase difference exists among the plurality of arbitrary waveform generators, wherein the phase difference is caused by a difference in the internal trigger signal; The waveform data is padded with zeros by upper-level software until the phase difference is eliminated.

6. The method according to claim 1, characterized in that After acquiring the external trigger signal sent by the system trigger signal module, the method further includes: Stop acquiring the external trigger signal until a new cycle ratio setting instruction sent from the measurement and control terminal is received.

7. The method according to claim 1, characterized in that After acquiring the external trigger signal sent by the system trigger signal module, the method further includes: Determine whether the external trigger signal includes the signal rising edge, and if not, continue to acquire the external trigger signal.

8. The method according to claim 1, characterized in that The clock source provides a reference clock for the delay generator and the PXIe chassis.

9. A synchronization device for an arbitrary waveform generator, characterized in that: include: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to execute: The arbitrary waveform generator receives a cycle ratio setting instruction sent from the measurement and control terminal, wherein the cycle ratio is a ratio of an external trigger signal cycle to an FPGA clock cycle; Setting the cycle ratio according to the cycle ratio setting instruction, and acquiring an external trigger signal sent by a system trigger signal module; Determine the rising edge of the signal sampled from the external trigger signal, and use the rising edge of the signal as the starting time node to count the FPGA clock cycle; Determining that the count value of the FPGA clock cycle reaches the cycle ratio, the FPGA of the arbitrary waveform generator generates an internal trigger signal inside, and recounts the FPGA clock cycle; Receive the loading waveform data sent from the measurement and control terminal, and send the waveform under the triggering of the internal trigger signal.

10. A non-volatile computer storage medium storing computer executable instructions, characterized in that: The computer executable instructions are configured to: The arbitrary waveform generator receives a cycle ratio setting instruction sent from the measurement and control terminal, wherein the cycle ratio is a ratio of an external trigger signal cycle to an FPGA clock cycle; Setting the cycle ratio according to the cycle ratio setting instruction, and acquiring an external trigger signal sent by a system trigger signal module; Determine the rising edge of the signal sampled from the external trigger signal, and use the rising edge of the signal as the starting time node to count the FPGA clock cycle; Determining that the count value of the FPGA clock cycle reaches the cycle ratio, the FPGA of the arbitrary waveform generator generates an internal trigger signal inside, and recounts the FPGA clock cycle; Receive the loading waveform data sent from the measurement and control terminal, and send the waveform under the triggering of the internal trigger signal.

Images